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Commit 92e11ddb authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-msm-display-for-6.2' of https://gitlab.freedesktop.org/lumag/msm into drm-next 

drm/msm updates for 6.2

Core:
- MSM_INFO_GET_FLAGS support
- Cleaned up MSM IOMMU wrapper code

DPU:
- Added support for XR30 and P010 image formats
- Reworked MDSS/DPU schema, added SM8250 MDSS bindings
- Added Qualcomm SM6115 support

DP:
- Dropped unsane sanity checks

DSI:
- Fix calculation of DSC pps payload

DSI PHY:
- DSI PHY support for QCM2290

HDMI:
- Reworked dev init path
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20221126102141.721353-1-dmitry.baryshkov@linaro.org
parents f513a19a 8d1d17d4
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Documentation/devicetree/bindings/display/msm/dpu-common.yaml 0 → 100644
View file @ 92e11ddb
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dpu-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU common properties
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
- Rob Clark <robdclark@gmail.com>
description: |
Common properties for QCom DPU display controller.
properties:
interrupts:
maxItems: 1
power-domains:
maxItems: 1
operating-points-v2: true
opp-table:
type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
Contains the list of output ports from DPU device. These ports
connect to interfaces that are external to the DPU hardware,
such as DSI, DP etc.
patternProperties:
"^port@[0-9a-f]+$":
$ref: /schemas/graph.yaml#/properties/port
# at least one port is required
required:
- port@0
required:
- compatible
- reg
- reg-names
- clocks
- interrupts
- power-domains
- operating-points-v2
- ports
additionalProperties: true
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml deleted 100644 → 0
View file @ f513a19a
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SC7180 target
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description: |
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for SC7180 target.
properties:
compatible:
items:
- const: qcom,sc7180-mdss
reg:
maxItems: 1
reg-names:
const: mdss
power-domains:
maxItems: 1
clocks:
items:
- description: Display AHB clock from gcc
- description: Display AHB clock from dispcc
- description: Display core clock
clock-names:
items:
- const: iface
- const: ahb
- const: core
interrupts:
maxItems: 1
interrupt-controller: true
"#address-cells": true
"#size-cells": true
"#interrupt-cells":
const: 1
iommus:
items:
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
ranges: true
interconnects:
items:
- description: Interconnect path specifying the port ids for data bus
interconnect-names:
const: mdp0-mem
resets:
items:
- description: MDSS_CORE reset
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
additionalProperties: false
properties:
compatible:
items:
- const: qcom,sc7180-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi clock
- description: Display ahb clock
- description: Display rotator clock
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: bus
- const: iface
- const: rot
- const: lut
- const: core
- const: vsync
interrupts:
maxItems: 1
power-domains:
maxItems: 1
operating-points-v2: true
opp-table:
type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
Contains the list of output ports from DPU device. These ports
connect to interfaces that are external to the DPU hardware,
such as DSI, DP etc. Each output port contains an endpoint that
describes how it is connected to an external interface.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF1 (DSI1)
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF0 (DP)
required:
- port@0
required:
- compatible
- reg
- reg-names
- clocks
- interrupts
- power-domains
- operating-points-v2
- ports
required:
- compatible
- reg
- reg-names
- power-domains
- clocks
- interrupts
- interrupt-controller
- iommus
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sc7180-mdss";
reg = <0xae00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "ahb", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
interconnect-names = "mdp0-mem";
iommus = <&apps_smmu 0x800 0x2>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sc7180-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "rot", "lut", "core",
"vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@2 {
reg = <2>;
dpu_intf0_out: endpoint {
remote-endpoint = <&dp_in>;
};
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml deleted 100644 → 0
View file @ f513a19a
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SC7280
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description: |
Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for SC7280.
properties:
compatible:
const: qcom,sc7280-mdss
reg:
maxItems: 1
reg-names:
const: mdss
power-domains:
maxItems: 1
clocks:
items:
- description: Display AHB clock from gcc
- description: Display AHB clock from dispcc
- description: Display core clock
clock-names:
items:
- const: iface
- const: ahb
- const: core
interrupts:
maxItems: 1
interrupt-controller: true
"#address-cells": true
"#size-cells": true
"#interrupt-cells":
const: 1
iommus:
items:
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
ranges: true
interconnects:
items:
- description: Interconnect path specifying the port ids for data bus
interconnect-names:
const: mdp0-mem
resets:
items:
- description: MDSS_CORE reset
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
additionalProperties: false
properties:
compatible:
const: qcom,sc7280-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi clock
- description: Display sf axi clock
- description: Display ahb clock
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: bus
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
interrupts:
maxItems: 1
power-domains:
maxItems: 1
operating-points-v2: true
opp-table:
type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
Contains the list of output ports from DPU device. These ports
connect to interfaces that are external to the DPU hardware,
such as DSI, DP etc. Each output port contains an endpoint that
describes how it is connected to an external interface.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF1 (DSI)
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF5 (EDP)
required:
- port@0
required:
- compatible
- reg
- reg-names
- clocks
- interrupts
- power-domains
- operating-points-v2
- ports
required:
- compatible
- reg
- reg-names
- power-domains
- clocks
- interrupts
- interrupt-controller
- iommus
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sc7280-mdss";
reg = <0xae00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface",
"ahb",
"core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
interconnect-names = "mdp0-mem";
iommus = <&apps_smmu 0x900 0x402>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sc7280-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf5_out: endpoint {
remote-endpoint = <&edp_in>;
};
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml deleted 100644 → 0
View file @ f513a19a
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SDM845 target
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description: |
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for SDM845 target.
properties:
compatible:
items:
- const: qcom,sdm845-mdss
reg:
maxItems: 1
reg-names:
const: mdss
power-domains:
maxItems: 1
clocks:
items:
- description: Display AHB clock from gcc
- description: Display core clock
clock-names:
items:
- const: iface
- const: core
interrupts:
maxItems: 1
interrupt-controller: true
"#address-cells": true
"#size-cells": true
"#interrupt-cells":
const: 1
iommus:
items:
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
ranges: true
resets:
items:
- description: MDSS_CORE reset
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
description: Node containing the properties of DPU.
additionalProperties: false
properties:
compatible:
items:
- const: qcom,sdm845-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display ahb clock
- description: Display axi clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: iface
- const: bus
- const: core
- const: vsync
interrupts:
maxItems: 1
power-domains:
maxItems: 1
operating-points-v2: true
opp-table:
type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
Contains the list of output ports from DPU device. These ports
connect to interfaces that are external to the DPU hardware,
such as DSI, DP etc. Each output port contains an endpoint that
describes how it is connected to an external interface.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF1 (DSI1)
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF2 (DSI2)
required:
- port@0
- port@1
required:
- compatible
- reg
- reg-names
- clocks
- interrupts
- power-domains
- operating-points-v2
- ports
required:
- compatible
- reg
- reg-names
- power-domains
- clocks
- interrupts
- interrupt-controller
- iommus
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sdm845-mdss";
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x880 0x8>,
<&apps_smmu 0xc80 0x8>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sdm845-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface", "bus", "core", "vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
View file @ 92e11ddb
...@@ -49,6 +49,7 @@ properties: ...@@ -49,6 +49,7 @@ properties:
maxItems: 1 maxItems: 1
phy-names: phy-names:
deprecated: true
const: dsi const: dsi
"#address-cells": true "#address-cells": true
...@@ -80,6 +81,9 @@ properties: ...@@ -80,6 +81,9 @@ properties:
operating-points-v2: true operating-points-v2: true
opp-table:
type: object
ports: ports:
$ref: "/schemas/graph.yaml#/properties/ports" $ref: "/schemas/graph.yaml#/properties/ports"
description: | description: |
...@@ -131,7 +135,6 @@ required: ...@@ -131,7 +135,6 @@ required:
- clocks - clocks
- clock-names - clock-names
- phys - phys
- phy-names
- assigned-clocks - assigned-clocks
- assigned-clock-parents - assigned-clock-parents
- power-domains - power-domains
......
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
View file @ 92e11ddb
...@@ -16,6 +16,7 @@ properties: ...@@ -16,6 +16,7 @@ properties:
compatible: compatible:
enum: enum:
- qcom,dsi-phy-14nm - qcom,dsi-phy-14nm
- qcom,dsi-phy-14nm-2290
- qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-660
- qcom,dsi-phy-14nm-8953 - qcom,dsi-phy-14nm-8953
......
Documentation/devicetree/bindings/display/msm/mdp5.txt
View file @ 92e11ddb
...@@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller ...@@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller
Description: Description:
This is the bindings documentation for the Mobile Display Subsytem(MDSS) that This is the bindings documentation for the MDP5 display
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996. controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
MDSS:
Required properties:
- compatible:
* "qcom,mdss" - MDSS
- reg: Physical base address and length of the controller's registers.
- reg-names: The names of register regions. The following regions are required:
* "mdss_phys"
* "vbif_phys"
- interrupts: The interrupt signal from MDSS.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: specifies the number of cells needed to encode an interrupt
source, should be 1.
- power-domains: a power domain consumer specifier according to
Documentation/devicetree/bindings/power/power_domain.txt
- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
* "iface"
* "bus"
* "vsync"
- #address-cells: number of address cells for the MDSS children. Should be 1.
- #size-cells: Should be 1.
- ranges: parent bus address space is the same as the child bus address space.
Optional properties:
- clock-names: the following clocks are optional:
* "lut"
MDP5: MDP5:
Required properties: Required properties:
- compatible: - compatible:
......
Documentation/devicetree/bindings/display/msm/mdss-common.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display MDSS common properties
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
- Rob Clark <robdclark@gmail.com>
description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc.
properties:
reg:
maxItems: 1
reg-names:
const: mdss
power-domains:
maxItems: 1
clocks:
minItems: 2
maxItems: 4
clock-names:
minItems: 2
maxItems: 4
interrupts:
maxItems: 1
interrupt-controller: true
"#address-cells": true
"#size-cells": true
"#interrupt-cells":
const: 1
iommus:
minItems: 1
items:
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
ranges: true
interconnects:
minItems: 1
items:
- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
- description: Interconnect path from mdp1 port to the data bus
interconnect-names:
minItems: 1
items:
- const: mdp0-mem
- const: mdp1-mem
resets:
items:
- description: MDSS_CORE reset
required:
- compatible
- reg
- reg-names
- power-domains
- clocks
- interrupts
- interrupt-controller
- iommus
- ranges
additionalProperties: true
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Mobile Display SubSystem (MDSS)
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
- Rob Clark <robdclark@gmail.com>
description:
This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
properties:
compatible:
enum:
- qcom,mdss
reg:
minItems: 2
maxItems: 3
reg-names:
minItems: 2
items:
- const: mdss_phys
- const: vbif_phys
- const: vbif_nrt_phys
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 1
power-domains:
maxItems: 1
description: |
The MDSS power domain provided by GCC
clocks:
minItems: 1
items:
- description: Display abh clock
- description: Display axi clock
- description: Display vsync clock
clock-names:
minItems: 1
items:
- const: iface
- const: bus
- const: vsync
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
resets:
items:
- description: MDSS_CORE reset
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-controller
- "#interrupt-cells"
- power-domains
- clocks
- clock-names
- "#address-cells"
- "#size-cells"
- ranges
patternProperties:
"^mdp@[1-9a-f][0-9a-f]*$":
type: object
properties:
compatible:
const: qcom,mdp5
"^dsi@[1-9a-f][0-9a-f]*$":
type: object
properties:
compatible:
const: qcom,mdss-dsi-ctrl
"^phy@[1-9a-f][0-9a-f]*$":
type: object
properties:
compatible:
enum:
- qcom,dsi-phy-14nm
- qcom,dsi-phy-14nm-660
- qcom,dsi-phy-14nm-8953
- qcom,dsi-phy-20nm
- qcom,dsi-phy-28nm-hpm
- qcom,dsi-phy-28nm-lp
"^hdmi-phy@[1-9a-f][0-9a-f]*$":
type: object
properties:
compatible:
enum:
- qcom,hdmi-phy-8084
- qcom,hdmi-phy-8660
- qcom,hdmi-phy-8960
- qcom,hdmi-phy-8974
- qcom,hdmi-phy-8996
"^hdmi-tx@[1-9a-f][0-9a-f]*$":
type: object
properties:
compatible:
enum:
- qcom,hdmi-tx-8084
- qcom,hdmi-tx-8660
- qcom,hdmi-tx-8960
- qcom,hdmi-tx-8974
- qcom,hdmi-tx-8994
- qcom,hdmi-tx-8996
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mdss@1a00000 {
compatible = "qcom,mdss";
reg = <0x1a00000 0x1000>,
<0x1ac8000 0x3000>;
reg-names = "mdss_phys", "vbif_phys";
power-domains = <&gcc MDSS_GDSC>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"vsync";
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mdp@1a01000 {
compatible = "qcom,mdp5";
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync";
iommus = <&apps_iommu 4>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp5_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,msm8998-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for MSM8998 target
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
items:
- const: qcom,msm8998-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for regdma register set
- description: Address offset and size for vbif register set
- description: Address offset and size for non-realtime vbif register set
reg-names:
items:
- const: mdp
- const: regdma
- const: vbif
- const: vbif_nrt
clocks:
items:
- description: Display ahb clock
- description: Display axi clock
- description: Display mem-noc clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: iface
- const: bus
- const: mnoc
- const: core
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@c901000 {
compatible = "qcom,msm8998-dpu";
reg = <0x0c901000 0x8f000>,
<0x0c9a8e00 0xf0>,
<0x0c9b0000 0x2008>,
<0x0c9b8000 0x1040>;
reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MNOC_AHB_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface", "bus", "mnoc", "core", "vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd MSM8998_VDDMX>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/dpu-msm8998.yaml → Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2 %YAML 1.2
--- ---
$id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for MSM8998 target title: Qualcomm MSM8998 Display MDSS
maintainers: maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
description: | description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS and DPU are mentioned for MSM8998 target. bindings of MDSS are mentioned for MSM8998 target.
$ref: /schemas/display/msm/mdss-common.yaml#
properties: properties:
compatible: compatible:
items: items:
- const: qcom,msm8998-mdss - const: qcom,msm8998-mdss
reg:
maxItems: 1
reg-names:
const: mdss
power-domains:
maxItems: 1
clocks: clocks:
items: items:
- description: Display AHB clock - description: Display AHB clock
...@@ -40,126 +33,38 @@ properties: ...@@ -40,126 +33,38 @@ properties:
- const: bus - const: bus
- const: core - const: core
interrupts:
maxItems: 1
interrupt-controller: true
"#address-cells": true
"#size-cells": true
"#interrupt-cells":
const: 1
iommus: iommus:
items: maxItems: 1
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
ranges: true
patternProperties: patternProperties:
"^display-controller@[0-9a-f]+$": "^display-controller@[0-9a-f]+$":
type: object type: object
description: Node containing the properties of DPU. properties:
additionalProperties: false compatible:
const: qcom,msm8998-dpu
"^dsi@[0-9a-f]+$":
type: object
properties: properties:
compatible: compatible:
items: const: qcom,mdss-dsi-ctrl
- const: qcom,msm8998-dpu
"^phy@[0-9a-f]+$":
reg: type: object
items: properties:
- description: Address offset and size for mdp register set compatible:
- description: Address offset and size for regdma register set const: qcom,dsi-phy-10nm-8998
- description: Address offset and size for vbif register set
- description: Address offset and size for non-realtime vbif register set unevaluatedProperties: false
reg-names:
items:
- const: mdp
- const: regdma
- const: vbif
- const: vbif_nrt
clocks:
items:
- description: Display ahb clock
- description: Display axi clock
- description: Display mem-noc clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: iface
- const: bus
- const: mnoc
- const: core
- const: vsync
interrupts:
maxItems: 1
power-domains:
maxItems: 1
operating-points-v2: true
opp-table:
type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
Contains the list of output ports from DPU device. These ports
connect to interfaces that are external to the DPU hardware,
such as DSI, DP etc. Each output port contains an endpoint that
describes how it is connected to an external interface.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF1 (DSI1)
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF2 (DSI2)
required:
- port@0
- port@1
required:
- compatible
- reg
- reg-names
- clocks
- interrupts
- power-domains
- operating-points-v2
- ports
required:
- compatible
- reg
- reg-names
- power-domains
- clocks
- interrupts
- interrupt-controller
- iommus
- ranges
additionalProperties: false
examples: examples:
- | - |
#include <dt-bindings/clock/qcom,mmcc-msm8998.h> #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
mdss: display-subsystem@c900000 { display-subsystem@c900000 {
compatible = "qcom,msm8998-mdss"; compatible = "qcom,msm8998-mdss";
reg = <0x0c900000 0x1000>; reg = <0x0c900000 0x1000>;
reg-names = "mdss"; reg-names = "mdss";
...@@ -219,5 +124,145 @@ examples: ...@@ -219,5 +124,145 @@ examples:
}; };
}; };
}; };
dsi@c994000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x0c994000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&mmcc MDSS_BYTE0_CLK>,
<&mmcc MDSS_BYTE0_INTF_CLK>,
<&mmcc MDSS_PCLK0_CLK>,
<&mmcc MDSS_ESC0_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd MSM8998_VDDCX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi0_phy: phy@c994400 {
compatible = "qcom,dsi-phy-10nm-8998";
reg = <0x0c994400 0x200>,
<0x0c994600 0x280>,
<0x0c994a00 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
vdds-supply = <&pm8998_l1>;
};
dsi@c996000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x0c996000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&mmcc MDSS_BYTE1_CLK>,
<&mmcc MDSS_BYTE1_INTF_CLK>,
<&mmcc MDSS_PCLK1_CLK>,
<&mmcc MDSS_ESC1_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd MSM8998_VDDCX>;
phys = <&dsi1_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
};
};
};
};
dsi1_phy: phy@c996400 {
compatible = "qcom,dsi-phy-10nm-8998";
reg = <0x0c996400 0x200>,
<0x0c996600 0x280>,
<0x0c996a00 0x10e>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
vdds-supply = <&pm8998_l1>;
};
}; };
... ...
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for QCM2290 target
maintainers:
- Loic Poulain <loic.poulain@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
items:
- const: qcom,qcm2290-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display AXI clock from gcc
- description: Display AHB clock from dispcc
- description: Display core clock from dispcc
- description: Display lut clock from dispcc
- description: Display vsync clock from dispcc
clock-names:
items:
- const: bus
- const: iface
- const: core
- const: lut
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@5e01000 {
compatible = "qcom,qcm2290-dpu";
reg = <0x05e01000 0x8f000>,
<0x05eb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "core", "lut", "vsync";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml → Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2 %YAML 1.2
--- ---
$id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml# $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for QCM2290 target title: Qualcomm QCM220 Display MDSS
maintainers: maintainers:
- Loic Poulain <loic.poulain@linaro.org> - Loic Poulain <loic.poulain@linaro.org>
description: | description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
and DPU are mentioned for QCM2290 target. are mentioned for QCM2290 target.
$ref: /schemas/display/msm/mdss-common.yaml#
properties: properties:
compatible: compatible:
items: items:
- const: qcom,qcm2290-mdss - const: qcom,qcm2290-mdss
reg:
maxItems: 1
reg-names:
const: mdss
power-domains:
maxItems: 1
clocks: clocks:
items: items:
- description: Display AHB clock from gcc - description: Display AHB clock from gcc
...@@ -40,131 +33,46 @@ properties: ...@@ -40,131 +33,46 @@ properties:
- const: bus - const: bus
- const: core - const: core
interrupts:
maxItems: 1
interrupt-controller: true
"#address-cells": true
"#size-cells": true
"#interrupt-cells":
const: 1
iommus: iommus:
items: maxItems: 2
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
ranges: true
interconnects: interconnects:
items: maxItems: 1
- description: Interconnect path specifying the port ids for data bus
interconnect-names: interconnect-names:
const: mdp0-mem maxItems: 1
resets:
items:
- description: MDSS_CORE reset
patternProperties: patternProperties:
"^display-controller@[0-9a-f]+$": "^display-controller@[0-9a-f]+$":
type: object type: object
description: Node containing the properties of DPU. properties:
additionalProperties: false compatible:
const: qcom,qcm2290-dpu
"^dsi@[0-9a-f]+$":
type: object
properties: properties:
compatible: compatible:
items: const: qcom,dsi-ctrl-6g-qcm2290
- const: qcom,qcm2290-dpu
"^phy@[0-9a-f]+$":
reg: type: object
items: properties:
- description: Address offset and size for mdp register set compatible:
- description: Address offset and size for vbif register set const: qcom,dsi-phy-14nm-2290
reg-names: unevaluatedProperties: false
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display AXI clock from gcc
- description: Display AHB clock from dispcc
- description: Display core clock from dispcc
- description: Display lut clock from dispcc
- description: Display vsync clock from dispcc
clock-names:
items:
- const: bus
- const: iface
- const: core
- const: lut
- const: vsync
interrupts:
maxItems: 1
power-domains:
maxItems: 1
operating-points-v2: true
opp-table:
type: object
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: |
Contains the list of output ports from DPU device. These ports
connect to interfaces that are external to the DPU hardware,
such as DSI. Each output port contains an endpoint that
describes how it is connected to an external interface.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPU_INTF1 (DSI1)
required:
- port@0
required:
- compatible
- reg
- reg-names
- clocks
- interrupts
- power-domains
- operating-points-v2
- ports
required:
- compatible
- reg
- reg-names
- power-domains
- clocks
- interrupts
- interrupt-controller
- iommus
- ranges
additionalProperties: false
examples: examples:
- | - |
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h> #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,qcm2290.h> #include <dt-bindings/interconnect/qcom,qcm2290.h>
#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/power/qcom-rpmpd.h>
mdss: mdss@5e00000 { mdss@5e00000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "qcom,qcm2290-mdss"; compatible = "qcom,qcm2290-mdss";
...@@ -187,36 +95,104 @@ examples: ...@@ -187,36 +95,104 @@ examples:
<&apps_smmu 0x421 0x0>; <&apps_smmu 0x421 0x0>;
ranges; ranges;
mdss_mdp: display-controller@5e01000 { display-controller@5e01000 {
compatible = "qcom,qcm2290-dpu"; compatible = "qcom,qcm2290-dpu";
reg = <0x05e01000 0x8f000>, reg = <0x05e01000 0x8f000>,
<0x05eb0000 0x2008>; <0x05eb0000 0x2008>;
reg-names = "mdp", "vbif"; reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>, clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>; <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "core", "lut", "vsync"; clock-names = "bus", "iface", "core", "lut", "vsync";
operating-points-v2 = <&mdp_opp_table>; operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>; power-domains = <&rpmpd QCM2290_VDDCX>;
interrupt-parent = <&mdss>; interrupt-parent = <&mdss>;
interrupts = <0>; interrupts = <0>;
ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { port@0 {
reg = <0>; reg = <0>;
dpu_intf1_out: endpoint { dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>; remote-endpoint = <&dsi0_in>;
}; };
}; };
};
};
dsi@5e94000 {
compatible = "qcom,dsi-ctrl-6g-qcm2290";
reg = <0x05e94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd QCM2290_VDDCX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
}; };
}; };
};
dsi0_phy: phy@5e94400 {
compatible = "qcom,dsi-phy-14nm-2290";
reg = <0x05e94400 0x100>,
<0x05e94500 0x300>,
<0x05e94800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
vcca-supply = <&vreg_dsi_phy>;
};
}; };
... ...
Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SC7180 target
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
items:
- const: qcom,sc7180-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi clock
- description: Display ahb clock
- description: Display rotator clock
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: bus
- const: iface
- const: rot
- const: lut
- const: core
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@ae01000 {
compatible = "qcom,sc7180-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "rot", "lut", "core",
"vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&dp_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7180 Display MDSS
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS are mentioned for SC7180 target.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
items:
- const: qcom,sc7180-mdss
clocks:
items:
- description: Display AHB clock from gcc
- description: Display AHB clock from dispcc
- description: Display core clock
clock-names:
items:
- const: iface
- const: ahb
- const: core
iommus:
maxItems: 1
interconnects:
maxItems: 1
interconnect-names:
maxItems: 1
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,sc7180-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,sc7180-dp
"^dsi@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,mdss-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,dsi-phy-10nm
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sc7180-mdss";
reg = <0xae00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "ahb", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
interconnect-names = "mdp0-mem";
iommus = <&apps_smmu 0x800 0x2>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sc7180-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "rot", "lut", "core",
"vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SC7180_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@2 {
reg = <2>;
dpu_intf0_out: endpoint {
remote-endpoint = <&dp_in>;
};
};
};
};
dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x0ae94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
phys = <&dsi_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
dsi_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94a00 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_dsi_phy>;
};
displayport-controller@ae90000 {
compatible = "qcom,sc7180-dp";
reg = <0xae90000 0x200>,
<0xae90200 0x200>,
<0xae90400 0xc00>,
<0xae91000 0x400>,
<0xae91400 0x400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface", "core_aux", "ctrl_link",
"ctrl_link_iface", "stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
phys = <&dp_phy>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SC7180_CX>;
#sound-dai-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
dp_out: endpoint { };
};
};
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SC7280
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sc7280-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display hf axi clock
- description: Display sf axi clock
- description: Display ahb clock
- description: Display lut clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: bus
- const: nrt_bus
- const: iface
- const: lut
- const: core
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@ae01000 {
compatible = "qcom,sc7280-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&edp_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SDM845 target
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
items:
- const: qcom,sdm845-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display GCC bus clock
- description: Display ahb clock
- description: Display axi clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: gcc-bus
- const: iface
- const: bus
- const: core
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@ae01000 {
compatible = "qcom,sdm845-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM845 Display MDSS
maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS are mentioned for SDM845 target.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
items:
- const: qcom,sdm845-mdss
clocks:
items:
- description: Display AHB clock from gcc
- description: Display core clock
clock-names:
items:
- const: iface
- const: core
iommus:
maxItems: 2
interconnects:
maxItems: 2
interconnect-names:
maxItems: 2
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,sdm845-dpu
"^dsi@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,mdss-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,dsi-phy-10nm
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sdm845-mdss";
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x880 0x8>,
<&apps_smmu 0xc80 0x8>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sdm845-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
interrupt-parent = <&mdss>;
interrupts = <0>;
power-domains = <&rpmhpd SDM845_CX>;
operating-points-v2 = <&mdp_opp_table>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x0ae94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94a00 0x1e0>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_dsi_phy>;
};
dsi@ae96000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x0ae96000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SDM845_CX>;
phys = <&dsi1_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
};
};
};
};
dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-10nm";
reg = <0x0ae96400 0x200>,
<0x0ae96600 0x280>,
<0x0ae96a00 0x10e>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_dsi_phy>;
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sm6115-dpu.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DPU dt properties for SM6115 target
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
items:
- const: qcom,sm6115-dpu
reg:
items:
- description: MDP register set
- description: VBIF register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display AXI
- description: Display AHB
- description: Display core
- description: Display lut
- description: Display rotator
- description: Display vsync
clock-names:
items:
- const: bus
- const: iface
- const: core
- const: lut
- const: rot
- const: vsync
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@5e01000 {
compatible = "qcom,sm6115-dpu";
reg = <0x05e01000 0x8f000>,
<0x05eb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd SM6115_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM6115 Display MDSS
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
are mentioned for SM6115 target.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
items:
- const: qcom,sm6115-mdss
clocks:
items:
- description: Display AHB clock from gcc
- description: Display AXI clock
- description: Display core clock
iommus:
maxItems: 2
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,sm6115-dpu
"^dsi@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,dsi-ctrl-6g-qcm2290
"^phy@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,dsi-phy-14nm-2290
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
mdss@5e00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "qcom,sm6115-mdss";
reg = <0x05e00000 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
ranges;
display-controller@5e01000 {
compatible = "qcom,sm6115-dpu";
reg = <0x05e01000 0x8f000>,
<0x05eb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_ROT_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmpd SM6115_VDDCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
dsi@5e94000 {
compatible = "qcom,dsi-ctrl-6g-qcm2290";
reg = <0x05e94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd SM6115_VDDCX>;
phys = <&dsi0_phy>;
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi0_phy: phy@5e94400 {
compatible = "qcom,dsi-phy-14nm-2290";
reg = <0x05e94400 0x100>,
<0x05e94500 0x300>,
<0x05e94800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-dpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8250 Display DPU
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
$ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,sm8250-dpu
reg:
items:
- description: Address offset and size for mdp register set
- description: Address offset and size for vbif register set
reg-names:
items:
- const: mdp
- const: vbif
clocks:
items:
- description: Display ahb clock
- description: Display hf axi clock
- description: Display core clock
- description: Display vsync clock
clock-names:
items:
- const: iface
- const: bus
- const: core
- const: vsync
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-controller@ae01000 {
compatible = "qcom,sm8250-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface", "bus", "core", "vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
...
Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml 0 → 100644
View file @ 92e11ddb
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8250 Display MDSS
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
bindings of MDSS are mentioned for SM8250 target.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
items:
- const: qcom,sm8250-mdss
clocks:
items:
- description: Display AHB clock from gcc
- description: Display hf axi clock
- description: Display sf axi clock
- description: Display core clock
clock-names:
items:
- const: iface
- const: bus
- const: nrt_bus
- const: core
iommus:
maxItems: 1
interconnects:
maxItems: 2
interconnect-names:
maxItems: 2
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,sm8250-dpu
"^dsi@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,mdss-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
properties:
compatible:
const: qcom,dsi-phy-7nm
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/power/qcom-rpmpd.h>
display-subsystem@ae00000 {
compatible = "qcom,sm8250-mdss";
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>,
<&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "bus", "nrt_bus", "core";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
iommus = <&apps_smmu 0x820 0x402>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
display-controller@ae01000 {
compatible = "qcom,sm8250-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface", "bus", "core", "vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-345000000 {
opp-hz = /bits/ 64 <345000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x0ae94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
dsi0_phy: phy@ae94400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0x0ae94400 0x200>,
<0x0ae94600 0x280>,
<0x0ae94900 0x260>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_dsi_phy>;
};
dsi@ae96000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x0ae96000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5>;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SM8250_MMCX>;
phys = <&dsi1_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
};
};
};
};
dsi1_phy: phy@ae96400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0x0ae96400 0x200>,
<0x0ae96600 0x280>,
<0x0ae96900 0x260>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
vdds-supply = <&vreg_dsi_phy>;
};
};
...
drivers/gpu/drm/msm/adreno/a3xx_gpu.c
View file @ 92e11ddb
...@@ -500,7 +500,7 @@ static const struct adreno_gpu_funcs funcs = { ...@@ -500,7 +500,7 @@ static const struct adreno_gpu_funcs funcs = {
#endif #endif
.gpu_state_get = a3xx_gpu_state_get, .gpu_state_get = a3xx_gpu_state_get,
.gpu_state_put = adreno_gpu_state_put, .gpu_state_put = adreno_gpu_state_put,
.create_address_space = adreno_iommu_create_address_space, .create_address_space = adreno_create_address_space,
.get_rptr = a3xx_get_rptr, .get_rptr = a3xx_get_rptr,
}, },
}; };
......
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
View file @ 92e11ddb
...@@ -635,7 +635,7 @@ static const struct adreno_gpu_funcs funcs = { ...@@ -635,7 +635,7 @@ static const struct adreno_gpu_funcs funcs = {
#endif #endif
.gpu_state_get = a4xx_gpu_state_get, .gpu_state_get = a4xx_gpu_state_get,
.gpu_state_put = adreno_gpu_state_put, .gpu_state_put = adreno_gpu_state_put,
.create_address_space = adreno_iommu_create_address_space, .create_address_space = adreno_create_address_space,
.get_rptr = a4xx_get_rptr, .get_rptr = a4xx_get_rptr,
}, },
.get_timestamp = a4xx_get_timestamp, .get_timestamp = a4xx_get_timestamp,
......
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
View file @ 92e11ddb
...@@ -1705,7 +1705,7 @@ static const struct adreno_gpu_funcs funcs = { ...@@ -1705,7 +1705,7 @@ static const struct adreno_gpu_funcs funcs = {
.gpu_busy = a5xx_gpu_busy, .gpu_busy = a5xx_gpu_busy,
.gpu_state_get = a5xx_gpu_state_get, .gpu_state_get = a5xx_gpu_state_get,
.gpu_state_put = a5xx_gpu_state_put, .gpu_state_put = a5xx_gpu_state_put,
.create_address_space = adreno_iommu_create_address_space, .create_address_space = adreno_create_address_space,
.get_rptr = a5xx_get_rptr, .get_rptr = a5xx_get_rptr,
}, },
.get_timestamp = a5xx_get_timestamp, .get_timestamp = a5xx_get_timestamp,
......
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View file @ 92e11ddb
...@@ -1213,19 +1213,17 @@ static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo, ...@@ -1213,19 +1213,17 @@ static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
{ {
struct iommu_domain *domain;
struct msm_mmu *mmu; struct msm_mmu *mmu;
domain = iommu_domain_alloc(&platform_bus_type); mmu = msm_iommu_new(gmu->dev, 0);
if (!domain) if (!mmu)
return -ENODEV; return -ENODEV;
if (IS_ERR(mmu))
return PTR_ERR(mmu);
mmu = msm_iommu_new(gmu->dev, domain);
gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000); gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
if (IS_ERR(gmu->aspace)) { if (IS_ERR(gmu->aspace))
iommu_domain_free(domain);
return PTR_ERR(gmu->aspace); return PTR_ERR(gmu->aspace);
}
return 0; return 0;
} }
......
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View file @ 92e11ddb
...@@ -1786,43 +1786,16 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) ...@@ -1786,43 +1786,16 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
{ {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct iommu_domain *iommu; unsigned long quirks = 0;
struct msm_mmu *mmu;
struct msm_gem_address_space *aspace;
u64 start, size;
iommu = iommu_domain_alloc(&platform_bus_type);
if (!iommu)
return NULL;
/* /*
* This allows GPU to set the bus attributes required to use system * This allows GPU to set the bus attributes required to use system
* cache on behalf of the iommu page table walker. * cache on behalf of the iommu page table walker.
*/ */
if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
adreno_set_llc_attributes(iommu); quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA;
mmu = msm_iommu_new(&pdev->dev, iommu);
if (IS_ERR(mmu)) {
iommu_domain_free(iommu);
return ERR_CAST(mmu);
}
/*
* Use the aperture start or SZ_16M, whichever is greater. This will
* ensure that we align with the allocated pagetable range while still
* allowing room in the lower 32 bits for GMEM and whatnot
*/
start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
size = iommu->geometry.aperture_end - start + 1;
aspace = msm_gem_address_space_create(mmu, "gpu",
start & GENMASK_ULL(48, 0), size);
if (IS_ERR(aspace) && !IS_ERR(mmu))
mmu->funcs->destroy(mmu);
return aspace; return adreno_iommu_create_address_space(gpu, pdev, quirks);
} }
static struct msm_gem_address_space * static struct msm_gem_address_space *
......
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View file @ 92e11ddb
...@@ -191,37 +191,38 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) ...@@ -191,37 +191,38 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
} }
void adreno_set_llc_attributes(struct iommu_domain *iommu) struct msm_gem_address_space *
adreno_create_address_space(struct msm_gpu *gpu,
struct platform_device *pdev)
{ {
iommu_set_pgtable_quirks(iommu, IO_PGTABLE_QUIRK_ARM_OUTER_WBWA); return adreno_iommu_create_address_space(gpu, pdev, 0);
} }
struct msm_gem_address_space * struct msm_gem_address_space *
adreno_iommu_create_address_space(struct msm_gpu *gpu, adreno_iommu_create_address_space(struct msm_gpu *gpu,
struct platform_device *pdev) struct platform_device *pdev,
unsigned long quirks)
{ {
struct iommu_domain *iommu; struct iommu_domain_geometry *geometry;
struct msm_mmu *mmu; struct msm_mmu *mmu;
struct msm_gem_address_space *aspace; struct msm_gem_address_space *aspace;
u64 start, size; u64 start, size;
iommu = iommu_domain_alloc(&platform_bus_type); mmu = msm_iommu_new(&pdev->dev, quirks);
if (!iommu) if (IS_ERR_OR_NULL(mmu))
return NULL;
mmu = msm_iommu_new(&pdev->dev, iommu);
if (IS_ERR(mmu)) {
iommu_domain_free(iommu);
return ERR_CAST(mmu); return ERR_CAST(mmu);
}
geometry = msm_iommu_get_geometry(mmu);
if (IS_ERR(geometry))
return ERR_CAST(geometry);
/* /*
* Use the aperture start or SZ_16M, whichever is greater. This will * Use the aperture start or SZ_16M, whichever is greater. This will
* ensure that we align with the allocated pagetable range while still * ensure that we align with the allocated pagetable range while still
* allowing room in the lower 32 bits for GMEM and whatnot * allowing room in the lower 32 bits for GMEM and whatnot
*/ */
start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); start = max_t(u64, SZ_16M, geometry->aperture_start);
size = iommu->geometry.aperture_end - start + 1; size = geometry->aperture_end - start + 1;
aspace = msm_gem_address_space_create(mmu, "gpu", aspace = msm_gem_address_space_create(mmu, "gpu",
start & GENMASK_ULL(48, 0), size); start & GENMASK_ULL(48, 0), size);
......
drivers/gpu/drm/msm/adreno/adreno_gpu.h
View file @ 92e11ddb
...@@ -335,10 +335,13 @@ void adreno_show_object(struct drm_printer *p, void **ptr, int len, ...@@ -335,10 +335,13 @@ void adreno_show_object(struct drm_printer *p, void **ptr, int len,
* attached targets * attached targets
*/ */
struct msm_gem_address_space * struct msm_gem_address_space *
adreno_iommu_create_address_space(struct msm_gpu *gpu, adreno_create_address_space(struct msm_gpu *gpu,
struct platform_device *pdev); struct platform_device *pdev);
void adreno_set_llc_attributes(struct iommu_domain *iommu); struct msm_gem_address_space *
adreno_iommu_create_address_space(struct msm_gpu *gpu,
struct platform_device *pdev,
unsigned long quirks);
int adreno_read_speedbin(struct device *dev, u32 *speedbin); int adreno_read_speedbin(struct device *dev, u32 *speedbin);
......
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
View file @ 92e11ddb
...@@ -434,6 +434,12 @@ static const struct dpu_format dpu_format_map[] = { ...@@ -434,6 +434,12 @@ static const struct dpu_format dpu_format_map[] = {
DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV, DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2), DPU_FETCH_LINEAR, 2),
PSEUDO_YUV_FMT_LOOSE(P010,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr,
DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
DPU_FETCH_LINEAR, 2),
INTERLEAVED_YUV_FMT(VYUY, INTERLEAVED_YUV_FMT(VYUY,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
...@@ -524,12 +530,26 @@ static const struct dpu_format dpu_format_map_ubwc[] = { ...@@ -524,12 +530,26 @@ static const struct dpu_format dpu_format_map_ubwc[] = {
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
PSEUDO_YUV_FMT_TILED(NV12, PSEUDO_YUV_FMT_TILED(NV12,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr, C1_B_Cb, C2_R_Cr,
DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV | DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED, DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12), DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
PSEUDO_YUV_FMT_TILED(P010,
0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
C1_B_Cb, C2_R_Cr,
DPU_CHROMA_420, DPU_FORMAT_FLAG_DX |
DPU_FORMAT_FLAG_YUV |
DPU_FORMAT_FLAG_COMPRESSED,
DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
}; };
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support /* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
...@@ -571,13 +591,15 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt) ...@@ -571,13 +591,15 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
{DRM_FORMAT_XBGR8888, COLOR_FMT_RGBA8888_UBWC}, {DRM_FORMAT_XBGR8888, COLOR_FMT_RGBA8888_UBWC},
{DRM_FORMAT_XRGB8888, COLOR_FMT_RGBA8888_UBWC}, {DRM_FORMAT_XRGB8888, COLOR_FMT_RGBA8888_UBWC},
{DRM_FORMAT_ABGR2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_ABGR2101010, COLOR_FMT_RGBA1010102_UBWC},
{DRM_FORMAT_XRGB2101010, COLOR_FMT_RGBA1010102_UBWC},
{DRM_FORMAT_XBGR2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_XBGR2101010, COLOR_FMT_RGBA1010102_UBWC},
{DRM_FORMAT_BGR565, COLOR_FMT_RGB565_UBWC}, {DRM_FORMAT_BGR565, COLOR_FMT_RGB565_UBWC},
}; };
int color_fmt = -1; int color_fmt = -1;
int i; int i;
if (fmt->base.pixel_format == DRM_FORMAT_NV12) { if (fmt->base.pixel_format == DRM_FORMAT_NV12 ||
fmt->base.pixel_format == DRM_FORMAT_P010) {
if (DPU_FORMAT_IS_DX(fmt)) { if (DPU_FORMAT_IS_DX(fmt)) {
if (fmt->unpack_tight) if (fmt->unpack_tight)
color_fmt = COLOR_FMT_NV12_BPP10_UBWC; color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View file @ 92e11ddb
...@@ -156,6 +156,7 @@ static const uint32_t plane_formats[] = { ...@@ -156,6 +156,7 @@ static const uint32_t plane_formats[] = {
DRM_FORMAT_RGBX8888, DRM_FORMAT_RGBX8888,
DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRX8888,
DRM_FORMAT_XBGR8888, DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_RGB888, DRM_FORMAT_RGB888,
DRM_FORMAT_BGR888, DRM_FORMAT_BGR888,
DRM_FORMAT_RGB565, DRM_FORMAT_RGB565,
...@@ -184,6 +185,7 @@ static const uint32_t plane_formats_yuv[] = { ...@@ -184,6 +185,7 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBA8888,
DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRX8888,
DRM_FORMAT_BGRA8888, DRM_FORMAT_BGRA8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888, DRM_FORMAT_XBGR8888,
DRM_FORMAT_RGBX8888, DRM_FORMAT_RGBX8888,
...@@ -208,6 +210,7 @@ static const uint32_t plane_formats_yuv[] = { ...@@ -208,6 +210,7 @@ static const uint32_t plane_formats_yuv[] = {
DRM_FORMAT_RGBX4444, DRM_FORMAT_RGBX4444,
DRM_FORMAT_BGRX4444, DRM_FORMAT_BGRX4444,
DRM_FORMAT_P010,
DRM_FORMAT_NV12, DRM_FORMAT_NV12,
DRM_FORMAT_NV21, DRM_FORMAT_NV21,
DRM_FORMAT_NV16, DRM_FORMAT_NV16,
...@@ -318,6 +321,18 @@ static const struct dpu_caps sc7180_dpu_caps = { ...@@ -318,6 +321,18 @@ static const struct dpu_caps sc7180_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
}; };
static const struct dpu_caps sm6115_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0x4,
.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
.ubwc_version = DPU_HW_UBWC_VER_20,
.has_dim_layer = true,
.has_idle_pc = true,
.max_linewidth = 2160,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
static const struct dpu_caps sm8150_dpu_caps = { static const struct dpu_caps sm8150_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb, .max_mixer_blendstages = 0xb,
...@@ -472,6 +487,19 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = { ...@@ -472,6 +487,19 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = {
}, },
}; };
static const struct dpu_mdp_cfg sm6115_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
.highest_bank_bit = 0x1,
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2ac, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
.reg_off = 0x2ac, .bit_off = 8},
},
};
static const struct dpu_mdp_cfg sm8250_mdp[] = { static const struct dpu_mdp_cfg sm8250_mdp[] = {
{ {
.name = "top_0", .id = MDP_TOP, .name = "top_0", .id = MDP_TOP,
...@@ -849,6 +877,16 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { ...@@ -849,6 +877,16 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
}; };
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
_VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_cfg sm6115_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
};
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
...@@ -1175,6 +1213,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { ...@@ -1175,6 +1213,13 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1), -1),
}; };
static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
};
static struct dpu_pingpong_cfg qcm2290_pp[] = { static struct dpu_pingpong_cfg qcm2290_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
...@@ -1198,13 +1243,6 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { ...@@ -1198,13 +1243,6 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
}; };
static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
};
/************************************************************* /*************************************************************
* DSC sub blocks config * DSC sub blocks config
*************************************************************/ *************************************************************/
...@@ -1587,6 +1625,35 @@ static const struct dpu_perf_cfg sc7180_perf_data = { ...@@ -1587,6 +1625,35 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
.bw_inefficiency_factor = 120, .bw_inefficiency_factor = 120,
}; };
static const struct dpu_perf_cfg sm6115_perf_data = {
.max_bw_low = 3100000,
.max_bw_high = 4000000,
.min_core_ib = 2400000,
.min_llcc_ib = 800000,
.min_dram_ib = 800000,
.min_prefill_lines = 24,
.danger_lut_tbl = {0xff, 0xffff, 0x0},
.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
},
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
.entries = sc7180_qos_macrotile
},
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
.entries = sc7180_qos_nrt
},
/* TODO: macrotile-qseed is different from macrotile */
},
.cdp_cfg = {
{.rd_enable = 1, .wr_enable = 1},
{.rd_enable = 1, .wr_enable = 0}
},
.clk_inefficiency_factor = 105,
.bw_inefficiency_factor = 120,
};
static const struct dpu_perf_cfg sm8150_perf_data = { static const struct dpu_perf_cfg sm8150_perf_data = {
.max_bw_low = 12800000, .max_bw_low = 12800000,
.max_bw_high = 12800000, .max_bw_high = 12800000,
...@@ -1798,6 +1865,28 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = { ...@@ -1798,6 +1865,28 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
.mdss_irqs = IRQ_SC7180_MASK, .mdss_irqs = IRQ_SC7180_MASK,
}; };
static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
.caps = &sm6115_dpu_caps,
.mdp_count = ARRAY_SIZE(sm6115_mdp),
.mdp = sm6115_mdp,
.ctl_count = ARRAY_SIZE(qcm2290_ctl),
.ctl = qcm2290_ctl,
.sspp_count = ARRAY_SIZE(sm6115_sspp),
.sspp = sm6115_sspp,
.mixer_count = ARRAY_SIZE(qcm2290_lm),
.mixer = qcm2290_lm,
.dspp_count = ARRAY_SIZE(qcm2290_dspp),
.dspp = qcm2290_dspp,
.pingpong_count = ARRAY_SIZE(qcm2290_pp),
.pingpong = qcm2290_pp,
.intf_count = ARRAY_SIZE(qcm2290_intf),
.intf = qcm2290_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.perf = &sm6115_perf_data,
.mdss_irqs = IRQ_SC7180_MASK,
};
static const struct dpu_mdss_cfg sm8150_dpu_cfg = { static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
.caps = &sm8150_dpu_caps, .caps = &sm8150_dpu_caps,
.mdp_count = ARRAY_SIZE(sdm845_mdp), .mdp_count = ARRAY_SIZE(sdm845_mdp),
...@@ -1932,6 +2021,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { ...@@ -1932,6 +2021,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg}, { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg},
{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
}; };
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View file @ 92e11ddb
...@@ -44,6 +44,7 @@ ...@@ -44,6 +44,7 @@
#define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ #define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */
#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
View file @ 92e11ddb
...@@ -42,7 +42,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, ...@@ -42,7 +42,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
u32 initial_lines) u32 initial_lines)
{ {
struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
u32 data, lsb, bpp; u32 data;
u32 slice_last_group_size; u32 slice_last_group_size;
u32 det_thresh_flatness; u32 det_thresh_flatness;
bool is_cmd_mode = !(mode & DSC_MODE_VIDEO); bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
...@@ -56,14 +56,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, ...@@ -56,14 +56,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
data = (initial_lines << 20); data = (initial_lines << 20);
data |= ((slice_last_group_size - 1) << 18); data |= ((slice_last_group_size - 1) << 18);
/* bpp is 6.4 format, 4 LSBs bits are for fractional part */ /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
data |= dsc->bits_per_pixel << 12; data |= (dsc->bits_per_pixel << 8);
lsb = dsc->bits_per_pixel % 4;
bpp = dsc->bits_per_pixel / 4;
bpp *= 4;
bpp <<= 4;
bpp |= lsb;
data |= bpp << 8;
data |= (dsc->block_pred_enable << 7); data |= (dsc->block_pred_enable << 7);
data |= (dsc->line_buf_depth << 3); data |= (dsc->line_buf_depth << 3);
data |= (dsc->simple_422 << 2); data |= (dsc->simple_422 << 2);
......
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View file @ 92e11ddb
...@@ -194,7 +194,7 @@ struct dpu_debugfs_regset32 { ...@@ -194,7 +194,7 @@ struct dpu_debugfs_regset32 {
struct dpu_kms *dpu_kms; struct dpu_kms *dpu_kms;
}; };
static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) static int dpu_regset32_show(struct seq_file *s, void *data)
{ {
struct dpu_debugfs_regset32 *regset = s->private; struct dpu_debugfs_regset32 *regset = s->private;
struct dpu_kms *dpu_kms = regset->dpu_kms; struct dpu_kms *dpu_kms = regset->dpu_kms;
...@@ -227,19 +227,7 @@ static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data) ...@@ -227,19 +227,7 @@ static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
return 0; return 0;
} }
DEFINE_SHOW_ATTRIBUTE(dpu_regset32);
static int dpu_debugfs_open_regset32(struct inode *inode,
struct file *file)
{
return single_open(file, _dpu_debugfs_show_regset32, inode->i_private);
}
static const struct file_operations dpu_fops_regset32 = {
.open = dpu_debugfs_open_regset32,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
void dpu_debugfs_create_regset32(const char *name, umode_t mode, void dpu_debugfs_create_regset32(const char *name, umode_t mode,
void *parent, void *parent,
...@@ -259,7 +247,7 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode, ...@@ -259,7 +247,7 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode,
regset->blk_len = length; regset->blk_len = length;
regset->dpu_kms = dpu_kms; regset->dpu_kms = dpu_kms;
debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32); debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
} }
static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
...@@ -1304,6 +1292,7 @@ static const struct of_device_id dpu_dt_match[] = { ...@@ -1304,6 +1292,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc7180-dpu", }, { .compatible = "qcom,sc7180-dpu", },
{ .compatible = "qcom,sc7280-dpu", }, { .compatible = "qcom,sc7280-dpu", },
{ .compatible = "qcom,sc8180x-dpu", }, { .compatible = "qcom,sc8180x-dpu", },
{ .compatible = "qcom,sm6115-dpu", },
{ .compatible = "qcom,sm8150-dpu", }, { .compatible = "qcom,sm8150-dpu", },
{ .compatible = "qcom,sm8250-dpu", }, { .compatible = "qcom,sm8250-dpu", },
{} {}
......
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
View file @ 92e11ddb
...@@ -69,9 +69,11 @@ static const uint32_t qcom_compressed_supported_formats[] = { ...@@ -69,9 +69,11 @@ static const uint32_t qcom_compressed_supported_formats[] = {
DRM_FORMAT_ARGB8888, DRM_FORMAT_ARGB8888,
DRM_FORMAT_XBGR8888, DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888, DRM_FORMAT_XRGB8888,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_BGR565, DRM_FORMAT_BGR565,
DRM_FORMAT_NV12, DRM_FORMAT_NV12,
DRM_FORMAT_P010,
}; };
/** /**
......
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
View file @ 92e11ddb
...@@ -387,7 +387,7 @@ static int mdp4_kms_init(struct drm_device *dev) ...@@ -387,7 +387,7 @@ static int mdp4_kms_init(struct drm_device *dev)
struct msm_drm_private *priv = dev->dev_private; struct msm_drm_private *priv = dev->dev_private;
struct mdp4_kms *mdp4_kms; struct mdp4_kms *mdp4_kms;
struct msm_kms *kms = NULL; struct msm_kms *kms = NULL;
struct iommu_domain *iommu; struct msm_mmu *mmu;
struct msm_gem_address_space *aspace; struct msm_gem_address_space *aspace;
int irq, ret; int irq, ret;
u32 major, minor; u32 major, minor;
...@@ -499,10 +499,15 @@ static int mdp4_kms_init(struct drm_device *dev) ...@@ -499,10 +499,15 @@ static int mdp4_kms_init(struct drm_device *dev)
mdp4_disable(mdp4_kms); mdp4_disable(mdp4_kms);
mdelay(16); mdelay(16);
iommu = iommu_domain_alloc(pdev->dev.bus); mmu = msm_iommu_new(&pdev->dev, 0);
if (iommu) { if (IS_ERR(mmu)) {
struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, iommu); ret = PTR_ERR(mmu);
goto fail;
} else if (!mmu) {
DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
"contig buffers for scanout\n");
aspace = NULL;
} else {
aspace = msm_gem_address_space_create(mmu, aspace = msm_gem_address_space_create(mmu,
"mdp4", 0x1000, 0x100000000 - 0x1000); "mdp4", 0x1000, 0x100000000 - 0x1000);
...@@ -514,10 +519,6 @@ static int mdp4_kms_init(struct drm_device *dev) ...@@ -514,10 +519,6 @@ static int mdp4_kms_init(struct drm_device *dev)
} }
kms->aspace = aspace; kms->aspace = aspace;
} else {
DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
"contig buffers for scanout\n");
aspace = NULL;
} }
ret = modeset_init(mdp4_kms); ret = modeset_init(mdp4_kms);
......
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
View file @ 92e11ddb
...@@ -203,7 +203,7 @@ static int mdp5_set_split_display(struct msm_kms *kms, ...@@ -203,7 +203,7 @@ static int mdp5_set_split_display(struct msm_kms *kms,
slave_encoder); slave_encoder);
} }
static void mdp5_destroy(struct platform_device *pdev); static void mdp5_destroy(struct mdp5_kms *mdp5_kms);
static void mdp5_kms_destroy(struct msm_kms *kms) static void mdp5_kms_destroy(struct msm_kms *kms)
{ {
...@@ -223,7 +223,7 @@ static void mdp5_kms_destroy(struct msm_kms *kms) ...@@ -223,7 +223,7 @@ static void mdp5_kms_destroy(struct msm_kms *kms)
} }
mdp_kms_destroy(&mdp5_kms->base); mdp_kms_destroy(&mdp5_kms->base);
mdp5_destroy(mdp5_kms->pdev); mdp5_destroy(mdp5_kms);
} }
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
...@@ -559,6 +559,8 @@ static int mdp5_kms_init(struct drm_device *dev) ...@@ -559,6 +559,8 @@ static int mdp5_kms_init(struct drm_device *dev)
int irq, i, ret; int irq, i, ret;
ret = mdp5_init(to_platform_device(dev->dev), dev); ret = mdp5_init(to_platform_device(dev->dev), dev);
if (ret)
return ret;
/* priv->kms would have been populated by the MDP5 driver */ /* priv->kms would have been populated by the MDP5 driver */
kms = priv->kms; kms = priv->kms;
...@@ -632,9 +634,8 @@ static int mdp5_kms_init(struct drm_device *dev) ...@@ -632,9 +634,8 @@ static int mdp5_kms_init(struct drm_device *dev)
return ret; return ret;
} }
static void mdp5_destroy(struct platform_device *pdev) static void mdp5_destroy(struct mdp5_kms *mdp5_kms)
{ {
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev);
int i; int i;
if (mdp5_kms->ctlm) if (mdp5_kms->ctlm)
...@@ -648,7 +649,7 @@ static void mdp5_destroy(struct platform_device *pdev) ...@@ -648,7 +649,7 @@ static void mdp5_destroy(struct platform_device *pdev)
kfree(mdp5_kms->intfs[i]); kfree(mdp5_kms->intfs[i]);
if (mdp5_kms->rpm_enabled) if (mdp5_kms->rpm_enabled)
pm_runtime_disable(&pdev->dev); pm_runtime_disable(&mdp5_kms->pdev->dev);
drm_atomic_private_obj_fini(&mdp5_kms->glob_state); drm_atomic_private_obj_fini(&mdp5_kms->glob_state);
drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); drm_modeset_lock_fini(&mdp5_kms->glob_state_lock);
...@@ -797,8 +798,6 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) ...@@ -797,8 +798,6 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
goto fail; goto fail;
} }
platform_set_drvdata(pdev, mdp5_kms);
spin_lock_init(&mdp5_kms->resource_lock); spin_lock_init(&mdp5_kms->resource_lock);
mdp5_kms->dev = dev; mdp5_kms->dev = dev;
...@@ -839,6 +838,9 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) ...@@ -839,6 +838,9 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
*/ */
clk_set_rate(mdp5_kms->core_clk, 200000000); clk_set_rate(mdp5_kms->core_clk, 200000000);
/* set uninit-ed kms */
priv->kms = &mdp5_kms->base.base;
pm_runtime_enable(&pdev->dev); pm_runtime_enable(&pdev->dev);
mdp5_kms->rpm_enabled = true; mdp5_kms->rpm_enabled = true;
...@@ -890,13 +892,10 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) ...@@ -890,13 +892,10 @@ static int mdp5_init(struct platform_device *pdev, struct drm_device *dev)
if (ret) if (ret)
goto fail; goto fail;
/* set uninit-ed kms */
priv->kms = &mdp5_kms->base.base;
return 0; return 0;
fail: fail:
if (mdp5_kms) if (mdp5_kms)
mdp5_destroy(pdev); mdp5_destroy(mdp5_kms);
return ret; return ret;
} }
...@@ -953,7 +952,8 @@ static int mdp5_dev_remove(struct platform_device *pdev) ...@@ -953,7 +952,8 @@ static int mdp5_dev_remove(struct platform_device *pdev)
static __maybe_unused int mdp5_runtime_suspend(struct device *dev) static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
{ {
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); struct msm_drm_private *priv = platform_get_drvdata(pdev);
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
DBG(""); DBG("");
...@@ -963,7 +963,8 @@ static __maybe_unused int mdp5_runtime_suspend(struct device *dev) ...@@ -963,7 +963,8 @@ static __maybe_unused int mdp5_runtime_suspend(struct device *dev)
static __maybe_unused int mdp5_runtime_resume(struct device *dev) static __maybe_unused int mdp5_runtime_resume(struct device *dev)
{ {
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); struct msm_drm_private *priv = platform_get_drvdata(pdev);
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms));
DBG(""); DBG("");
......
drivers/gpu/drm/msm/dp/dp_display.c
View file @ 92e11ddb
...@@ -1600,20 +1600,10 @@ static int dp_display_get_next_bridge(struct msm_dp *dp) ...@@ -1600,20 +1600,10 @@ static int dp_display_get_next_bridge(struct msm_dp *dp)
int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
struct drm_encoder *encoder) struct drm_encoder *encoder)
{ {
struct msm_drm_private *priv; struct msm_drm_private *priv = dev->dev_private;
struct dp_display_private *dp_priv; struct dp_display_private *dp_priv;
int ret; int ret;
if (WARN_ON(!encoder) || WARN_ON(!dp_display) || WARN_ON(!dev))
return -EINVAL;
priv = dev->dev_private;
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
DRM_DEV_ERROR(dev->dev, "too many bridges\n");
return -ENOSPC;
}
dp_display->drm_dev = dev; dp_display->drm_dev = dev;
dp_priv = container_of(dp_display, struct dp_display_private, dp_display); dp_priv = container_of(dp_display, struct dp_display_private, dp_display);
......
drivers/gpu/drm/msm/dp/dp_link.c
View file @ 92e11ddb
...@@ -49,23 +49,26 @@ static int dp_aux_link_power_up(struct drm_dp_aux *aux, ...@@ -49,23 +49,26 @@ static int dp_aux_link_power_up(struct drm_dp_aux *aux,
struct dp_link_info *link) struct dp_link_info *link)
{ {
u8 value; u8 value;
int err; ssize_t len;
int i;
if (link->revision < 0x11) if (link->revision < 0x11)
return 0; return 0;
err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); len = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
if (err < 0) if (len < 0)
return err; return len;
value &= ~DP_SET_POWER_MASK; value &= ~DP_SET_POWER_MASK;
value |= DP_SET_POWER_D0; value |= DP_SET_POWER_D0;
err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); /* retry for 1ms to give the sink time to wake up */
if (err < 0) for (i = 0; i < 3; i++) {
return err; len = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
usleep_range(1000, 2000);
usleep_range(1000, 2000); if (len == 1)
break;
}
return 0; return 0;
} }
......
drivers/gpu/drm/msm/dsi/dsi.c
View file @ 92e11ddb
...@@ -211,14 +211,9 @@ void __exit msm_dsi_unregister(void) ...@@ -211,14 +211,9 @@ void __exit msm_dsi_unregister(void)
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
struct drm_encoder *encoder) struct drm_encoder *encoder)
{ {
struct msm_drm_private *priv; struct msm_drm_private *priv = dev->dev_private;
int ret; int ret;
if (WARN_ON(!encoder) || WARN_ON(!msm_dsi) || WARN_ON(!dev))
return -EINVAL;
priv = dev->dev_private;
if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) { if (priv->num_bridges == ARRAY_SIZE(priv->bridges)) {
DRM_DEV_ERROR(dev->dev, "too many bridges\n"); DRM_DEV_ERROR(dev->dev, "too many bridges\n");
return -ENOSPC; return -ENOSPC;
......
drivers/gpu/drm/msm/dsi/dsi_host.c
View file @ 92e11ddb
...@@ -21,6 +21,7 @@ ...@@ -21,6 +21,7 @@
#include <video/mipi_display.h> #include <video/mipi_display.h>
#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_of.h> #include <drm/drm_of.h>
#include "dsi.h" #include "dsi.h"
...@@ -33,7 +34,7 @@ ...@@ -33,7 +34,7 @@
#define DSI_RESET_TOGGLE_DELAY_MS 20 #define DSI_RESET_TOGGLE_DELAY_MS 20
static int dsi_populate_dsc_params(struct drm_dsc_config *dsc); static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
{ {
...@@ -842,17 +843,15 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, ...@@ -842,17 +843,15 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
{ {
struct drm_dsc_config *dsc = msm_host->dsc; struct drm_dsc_config *dsc = msm_host->dsc;
u32 reg, intf_width, reg_ctrl, reg_ctrl2; u32 reg, reg_ctrl, reg_ctrl2;
u32 slice_per_intf, total_bytes_per_intf; u32 slice_per_intf, total_bytes_per_intf;
u32 pkt_per_line; u32 pkt_per_line;
u32 bytes_in_slice;
u32 eol_byte_num; u32 eol_byte_num;
/* first calculate dsc parameters and then program /* first calculate dsc parameters and then program
* compress mode registers * compress mode registers
*/ */
intf_width = hdisplay; slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width);
slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
/* If slice_per_pkt is greater than slice_per_intf /* If slice_per_pkt is greater than slice_per_intf
* then default to 1. This can happen during partial * then default to 1. This can happen during partial
...@@ -861,12 +860,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod ...@@ -861,12 +860,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod
if (slice_per_intf > dsc->slice_count) if (slice_per_intf > dsc->slice_count)
dsc->slice_count = 1; dsc->slice_count = 1;
slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bits_per_pixel, 8);
dsc->slice_chunk_size = bytes_in_slice;
total_bytes_per_intf = bytes_in_slice * slice_per_intf;
eol_byte_num = total_bytes_per_intf % 3; eol_byte_num = total_bytes_per_intf % 3;
pkt_per_line = slice_per_intf / dsc->slice_count; pkt_per_line = slice_per_intf / dsc->slice_count;
...@@ -892,7 +886,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod ...@@ -892,7 +886,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod
reg_ctrl |= reg; reg_ctrl |= reg;
reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(bytes_in_slice); reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
...@@ -915,6 +909,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) ...@@ -915,6 +909,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
u32 va_end = va_start + mode->vdisplay; u32 va_end = va_start + mode->vdisplay;
u32 hdisplay = mode->hdisplay; u32 hdisplay = mode->hdisplay;
u32 wc; u32 wc;
int ret;
DBG(""); DBG("");
...@@ -950,7 +945,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) ...@@ -950,7 +945,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
/* we do the calculations for dsc parameters here so that /* we do the calculations for dsc parameters here so that
* panel can use these parameters * panel can use these parameters
*/ */
dsi_populate_dsc_params(dsc); ret = dsi_populate_dsc_params(msm_host, dsc);
if (ret)
return;
/* Divide the display by 3 but keep back/font porch and /* Divide the display by 3 but keep back/font porch and
* pulse width same * pulse width same
...@@ -1754,18 +1751,20 @@ static char bpg_offset[DSC_NUM_BUF_RANGES] = { ...@@ -1754,18 +1751,20 @@ static char bpg_offset[DSC_NUM_BUF_RANGES] = {
2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
}; };
static int dsi_populate_dsc_params(struct drm_dsc_config *dsc) static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
{ {
int mux_words_size;
int groups_per_line, groups_total;
int min_rate_buffer_size;
int hrd_delay;
int pre_num_extra_mux_bits, num_extra_mux_bits;
int slice_bits;
int target_bpp_x16;
int data;
int final_value, final_scale;
int i; int i;
u16 bpp = dsc->bits_per_pixel >> 4;
if (dsc->bits_per_pixel & 0xf) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
return -EINVAL;
}
if (dsc->bits_per_component != 8) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n");
return -EOPNOTSUPP;
}
dsc->rc_model_size = 8192; dsc->rc_model_size = 8192;
dsc->first_line_bpg_offset = 12; dsc->first_line_bpg_offset = 12;
...@@ -1783,16 +1782,21 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc) ...@@ -1783,16 +1782,21 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
dsc->rc_range_params[i].range_min_qp = min_qp[i]; dsc->rc_range_params[i].range_min_qp = min_qp[i];
dsc->rc_range_params[i].range_max_qp = max_qp[i]; dsc->rc_range_params[i].range_max_qp = max_qp[i];
dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i]; /*
* Range BPG Offset contains two's-complement signed values that fill
* 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
*/
dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
} }
dsc->initial_offset = 6144; /* Not bpp 12 */ dsc->initial_offset = 6144; /* Not bpp 12 */
if (dsc->bits_per_pixel != 8) if (bpp != 8)
dsc->initial_offset = 2048; /* bpp = 12 */ dsc->initial_offset = 2048; /* bpp = 12 */
mux_words_size = 48; /* bpc == 8/10 */ if (dsc->bits_per_component <= 10)
if (dsc->bits_per_component == 12) dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
mux_words_size = 64; else
dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
dsc->initial_xmit_delay = 512; dsc->initial_xmit_delay = 512;
dsc->initial_scale_value = 32; dsc->initial_scale_value = 32;
...@@ -1804,63 +1808,8 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc) ...@@ -1804,63 +1808,8 @@ static int dsi_populate_dsc_params(struct drm_dsc_config *dsc)
dsc->flatness_max_qp = 12; dsc->flatness_max_qp = 12;
dsc->rc_quant_incr_limit0 = 11; dsc->rc_quant_incr_limit0 = 11;
dsc->rc_quant_incr_limit1 = 11; dsc->rc_quant_incr_limit1 = 11;
dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
/* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
* params are calculated
*/
groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3);
dsc->slice_chunk_size = dsc->slice_width * dsc->bits_per_pixel / 8;
if ((dsc->slice_width * dsc->bits_per_pixel) % 8)
dsc->slice_chunk_size++;
/* rbs-min */ return drm_dsc_compute_rc_parameters(dsc);
min_rate_buffer_size = dsc->rc_model_size - dsc->initial_offset +
dsc->initial_xmit_delay * dsc->bits_per_pixel +
groups_per_line * dsc->first_line_bpg_offset;
hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->bits_per_pixel);
dsc->initial_dec_delay = hrd_delay - dsc->initial_xmit_delay;
dsc->initial_scale_value = 8 * dsc->rc_model_size /
(dsc->rc_model_size - dsc->initial_offset);
slice_bits = 8 * dsc->slice_chunk_size * dsc->slice_height;
groups_total = groups_per_line * dsc->slice_height;
data = dsc->first_line_bpg_offset * 2048;
dsc->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->slice_height - 1));
pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->bits_per_component + 4) - 2);
num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
data = 2048 * (dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits);
dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
/* bpp * 16 + 0.5 */
data = dsc->bits_per_pixel * 16;
data *= 2;
data++;
data /= 2;
target_bpp_x16 = data;
data = (dsc->initial_xmit_delay * target_bpp_x16) / 16;
final_value = dsc->rc_model_size - data + num_extra_mux_bits;
dsc->final_offset = final_value;
final_scale = 8 * dsc->rc_model_size / (dsc->rc_model_size - final_value);
data = (final_scale - 9) * (dsc->nfl_bpg_offset + dsc->slice_bpg_offset);
dsc->scale_increment_interval = (2048 * dsc->final_offset) / data;
dsc->scale_decrement_interval = groups_per_line / (dsc->initial_scale_value - 8);
return 0;
} }
static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
......
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
View file @ 92e11ddb
...@@ -549,6 +549,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { ...@@ -549,6 +549,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
{ .compatible = "qcom,dsi-phy-14nm", { .compatible = "qcom,dsi-phy-14nm",
.data = &dsi_phy_14nm_cfgs }, .data = &dsi_phy_14nm_cfgs },
{ .compatible = "qcom,dsi-phy-14nm-2290",
.data = &dsi_phy_14nm_2290_cfgs },
{ .compatible = "qcom,dsi-phy-14nm-660", { .compatible = "qcom,dsi-phy-14nm-660",
.data = &dsi_phy_14nm_660_cfgs }, .data = &dsi_phy_14nm_660_cfgs },
{ .compatible = "qcom,dsi-phy-14nm-8953", { .compatible = "qcom,dsi-phy-14nm-8953",
......
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
View file @ 92e11ddb
...@@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; ...@@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
......
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
View file @ 92e11ddb
...@@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { ...@@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
.io_start = { 0x1a94400, 0x1a96400 }, .io_start = { 0x1a94400, 0x1a96400 },
.num_dsi_phy = 2, .num_dsi_phy = 2,
}; };
const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_14nm_17mA_regulators,
.num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators),
.ops = {
.enable = dsi_14nm_phy_enable,
.disable = dsi_14nm_phy_disable,
.pll_init = dsi_pll_14nm_init,
.save_pll_state = dsi_14nm_pll_save_state,
.restore_pll_state = dsi_14nm_pll_restore_state,
},
.min_pll_rate = VCO_MIN_RATE,
.max_pll_rate = VCO_MAX_RATE,
.io_start = { 0x5e94400 },
.num_dsi_phy = 1,
};
drivers/gpu/drm/msm/hdmi/hdmi.c
View file @ 92e11ddb
This diff is collapsed.
drivers/gpu/drm/msm/hdmi/hdmi.h
View file @ 92e11ddb
...@@ -86,9 +86,6 @@ struct hdmi { ...@@ -86,9 +86,6 @@ struct hdmi {
/* platform config data (ie. from DT, or pdata) */ /* platform config data (ie. from DT, or pdata) */
struct hdmi_platform_config { struct hdmi_platform_config {
const char *mmio_name;
const char *qfprom_mmio_name;
/* regulators that need to be on for hpd: */ /* regulators that need to be on for hpd: */
const char **hpd_reg_names; const char **hpd_reg_names;
int hpd_reg_cnt; int hpd_reg_cnt;
......
drivers/gpu/drm/msm/msm_drv.c
View file @ 92e11ddb
...@@ -277,7 +277,6 @@ static int msm_drm_uninit(struct device *dev) ...@@ -277,7 +277,6 @@ static int msm_drm_uninit(struct device *dev)
struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
{ {
struct iommu_domain *domain;
struct msm_gem_address_space *aspace; struct msm_gem_address_space *aspace;
struct msm_mmu *mmu; struct msm_mmu *mmu;
struct device *mdp_dev = dev->dev; struct device *mdp_dev = dev->dev;
...@@ -293,22 +292,21 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev) ...@@ -293,22 +292,21 @@ struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
else else
iommu_dev = mdss_dev; iommu_dev = mdss_dev;
domain = iommu_domain_alloc(iommu_dev->bus); mmu = msm_iommu_new(iommu_dev, 0);
if (!domain) { if (IS_ERR(mmu))
return ERR_CAST(mmu);
if (!mmu) {
drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n"); drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
return NULL; return NULL;
} }
mmu = msm_iommu_new(iommu_dev, domain);
if (IS_ERR(mmu)) {
iommu_domain_free(domain);
return ERR_CAST(mmu);
}
aspace = msm_gem_address_space_create(mmu, "mdp_kms", aspace = msm_gem_address_space_create(mmu, "mdp_kms",
0x1000, 0x100000000 - 0x1000); 0x1000, 0x100000000 - 0x1000);
if (IS_ERR(aspace)) if (IS_ERR(aspace)) {
dev_err(mdp_dev, "aspace create, error %pe\n", aspace);
mmu->funcs->destroy(mmu); mmu->funcs->destroy(mmu);
}
return aspace; return aspace;
} }
...@@ -819,6 +817,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data, ...@@ -819,6 +817,7 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
case MSM_INFO_GET_OFFSET: case MSM_INFO_GET_OFFSET:
case MSM_INFO_GET_IOVA: case MSM_INFO_GET_IOVA:
case MSM_INFO_SET_IOVA: case MSM_INFO_SET_IOVA:
case MSM_INFO_GET_FLAGS:
/* value returned as immediate, not pointer, so len==0: */ /* value returned as immediate, not pointer, so len==0: */
if (args->len) if (args->len)
return -EINVAL; return -EINVAL;
...@@ -846,6 +845,15 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data, ...@@ -846,6 +845,15 @@ static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
case MSM_INFO_SET_IOVA: case MSM_INFO_SET_IOVA:
ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value); ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
break; break;
case MSM_INFO_GET_FLAGS:
if (obj->import_attach) {
ret = -EINVAL;
break;
}
/* Hide internal kernel-only flags: */
args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
ret = 0;
break;
case MSM_INFO_SET_NAME: case MSM_INFO_SET_NAME:
/* length check should leave room for terminating null: */ /* length check should leave room for terminating null: */
if (args->len >= sizeof(msm_obj->name)) { if (args->len >= sizeof(msm_obj->name)) {
......
drivers/gpu/drm/msm/msm_iommu.c
View file @ 92e11ddb
...@@ -186,6 +186,13 @@ int msm_iommu_pagetable_params(struct msm_mmu *mmu, ...@@ -186,6 +186,13 @@ int msm_iommu_pagetable_params(struct msm_mmu *mmu,
return 0; return 0;
} }
struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu)
{
struct msm_iommu *iommu = to_msm_iommu(mmu);
return &iommu->domain->geometry;
}
static const struct msm_mmu_funcs pagetable_funcs = { static const struct msm_mmu_funcs pagetable_funcs = {
.map = msm_iommu_pagetable_map, .map = msm_iommu_pagetable_map,
.unmap = msm_iommu_pagetable_unmap, .unmap = msm_iommu_pagetable_unmap,
...@@ -367,17 +374,23 @@ static const struct msm_mmu_funcs funcs = { ...@@ -367,17 +374,23 @@ static const struct msm_mmu_funcs funcs = {
.resume_translation = msm_iommu_resume_translation, .resume_translation = msm_iommu_resume_translation,
}; };
struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks)
{ {
struct iommu_domain *domain;
struct msm_iommu *iommu; struct msm_iommu *iommu;
int ret; int ret;
domain = iommu_domain_alloc(dev->bus);
if (!domain) if (!domain)
return ERR_PTR(-ENODEV); return NULL;
iommu_set_pgtable_quirks(domain, quirks);
iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
if (!iommu) if (!iommu) {
iommu_domain_free(domain);
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
}
iommu->domain = domain; iommu->domain = domain;
msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU);
...@@ -386,6 +399,7 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) ...@@ -386,6 +399,7 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
ret = iommu_attach_device(iommu->domain, dev); ret = iommu_attach_device(iommu->domain, dev);
if (ret) { if (ret) {
iommu_domain_free(domain);
kfree(iommu); kfree(iommu);
return ERR_PTR(ret); return ERR_PTR(ret);
} }
......
drivers/gpu/drm/msm/msm_mdss.c
View file @ 92e11ddb
This diff is collapsed.
drivers/gpu/drm/msm/msm_mmu.h
View file @ 92e11ddb
...@@ -40,7 +40,7 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev, ...@@ -40,7 +40,7 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,
mmu->type = type; mmu->type = type;
} }
struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks);
struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu); struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
...@@ -58,5 +58,6 @@ void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, ...@@ -58,5 +58,6 @@ void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr, int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
int *asid); int *asid);
struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu);
#endif /* __MSM_MMU_H__ */ #endif /* __MSM_MMU_H__ */
include/uapi/drm/msm_drm.h
View file @ 92e11ddb
...@@ -138,6 +138,7 @@ struct drm_msm_gem_new { ...@@ -138,6 +138,7 @@ struct drm_msm_gem_new {
#define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */ #define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
#define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */ #define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
#define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */ #define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
#define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
struct drm_msm_gem_info { struct drm_msm_gem_info {
__u32 handle; /* in */ __u32 handle; /* in */
......
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