Commit 93613b9f authored by Krzysztof Helt's avatar Krzysztof Helt Committed by Linus Torvalds

s3c2410fb: byte ordering fixes

This patch sets correct bits related to the byte ordering of the
framebuffer.  This was tested on little endian kernel only.  The big endian
kernel may require different settings.

The patch also adds 32 bpp mode which is called 24 bpp by Samsung.  One
pixel takes 32 bits but only 24 bits are used in this mode.
Signed-off-by: default avatarKrzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: default avatarAntonino Daplas <adaplas@gmail.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 7ee0fe41
...@@ -265,8 +265,8 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var, ...@@ -265,8 +265,8 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
var->blue.length = 5; var->blue.length = 5;
} }
break; break;
case 24: case 32:
/* 24 bpp 888 */ /* 24 bpp 888 and 8 dummy */
var->red.length = 8; var->red.length = 8;
var->red.offset = 16; var->red.offset = 16;
var->green.length = 8; var->green.length = 8;
...@@ -274,8 +274,6 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var, ...@@ -274,8 +274,6 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
var->blue.length = 8; var->blue.length = 8;
var->blue.offset = 0; var->blue.offset = 0;
break; break;
} }
return 0; return 0;
} }
...@@ -374,11 +372,21 @@ static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info, ...@@ -374,11 +372,21 @@ static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
break; break;
case 8: case 8:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP; regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
S3C2410_LCDCON5_FRM565;
regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
break; break;
case 16: case 16:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP; regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
break;
case 32:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
S3C2410_LCDCON5_HWSWP |
S3C2410_LCDCON5_BPP24BL);
break; break;
default: default:
/* invalid pixel depth */ /* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n", dev_err(fbi->dev, "invalid bpp %d\n",
...@@ -475,7 +483,9 @@ static int s3c2410fb_set_par(struct fb_info *info) ...@@ -475,7 +483,9 @@ static int s3c2410fb_set_par(struct fb_info *info)
struct fb_var_screeninfo *var = &info->var; struct fb_var_screeninfo *var = &info->var;
switch (var->bits_per_pixel) { switch (var->bits_per_pixel) {
case 32:
case 16: case 16:
case 12:
info->fix.visual = FB_VISUAL_TRUECOLOR; info->fix.visual = FB_VISUAL_TRUECOLOR;
break; break;
case 1: case 1:
......
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