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Commit 9435294c authored by Pierre Gondois's avatar Pierre Gondois Committed by Bjorn Andersson
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arm64: dts: qcom: Update cache properties 

The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
  cache-unified:
  If present, specifies the cache has a unified or-
  ganization. If not present, specifies that the
  cache has a Harvard architecture with separate
  caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).

To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.
Signed-off-by: default avatarPierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
parent dcc7cd5c
Hide whitespace changes
Inline Side-by-side
Showing with 83 additions and 56 deletions
arch/arm64/boot/dts/qcom/msm8953.dtsi
View file @ 9435294c
......@@ -42,13 +42,6 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
CPU1: cpu@1 {
......@@ -59,13 +52,6 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
CPU2: cpu@2 {
......@@ -76,13 +62,6 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
CPU3: cpu@3 {
......@@ -93,13 +72,6 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
CPU4: cpu@100 {
......@@ -110,13 +82,6 @@ CPU4: cpu@100 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
CPU5: cpu@101 {
......@@ -127,13 +92,6 @@ CPU5: cpu@101 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
CPU6: cpu@102 {
......@@ -144,13 +102,6 @@ CPU6: cpu@102 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
CPU7: cpu@103 {
......@@ -161,13 +112,6 @@ CPU7: cpu@103 {
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
l1-icache {
compatible = "cache";
};
l1-dcache {
compatible = "cache";
};
};
cpu-map {
......
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ 9435294c
......@@ -146,9 +146,11 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -171,6 +173,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -193,6 +196,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -215,6 +219,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -237,6 +242,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -259,6 +265,7 @@ &LITTLE_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -281,6 +288,7 @@ &BIG_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -303,6 +311,7 @@ &BIG_CPU_SLEEP_1
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file @ 9435294c
......@@ -180,9 +180,11 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -203,6 +205,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -223,6 +226,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -243,6 +247,7 @@ &LITTLE_CPU_SLEEP_1
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -263,6 +268,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -283,6 +289,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -303,6 +310,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -323,6 +331,7 @@ &BIG_CPU_SLEEP_1
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file @ 9435294c
......@@ -234,9 +234,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -256,6 +258,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -275,6 +278,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -294,6 +298,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -313,6 +318,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -332,6 +338,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -351,6 +358,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -370,6 +378,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 9435294c
......@@ -209,9 +209,11 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -233,6 +235,7 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -254,6 +257,7 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -275,6 +279,7 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -296,6 +301,7 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -317,6 +323,7 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -338,6 +345,7 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -359,6 +367,7 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm6125.dtsi
View file @ 9435294c
......@@ -45,6 +45,7 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
......@@ -84,6 +85,7 @@ CPU4: cpu@100 {
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
......
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file @ 9435294c
......@@ -50,9 +50,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -69,6 +71,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -85,6 +88,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -101,6 +105,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -117,6 +122,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -133,6 +139,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
......@@ -150,6 +157,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -166,6 +174,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 9435294c
......@@ -60,9 +60,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -84,6 +86,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
......@@ -106,6 +109,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -127,6 +131,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -148,6 +153,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -169,6 +175,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -190,6 +197,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -211,6 +219,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file @ 9435294c
......@@ -110,9 +110,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -134,6 +136,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -155,6 +158,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -176,6 +180,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -197,6 +202,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -218,6 +224,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
......@@ -240,6 +247,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -261,6 +269,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file @ 9435294c
......@@ -73,9 +73,11 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -92,6 +94,7 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -108,6 +111,7 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -124,6 +128,7 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -140,6 +145,7 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -156,6 +162,7 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
......@@ -173,6 +180,7 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -189,6 +197,7 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file @ 9435294c
......@@ -57,9 +57,11 @@ CPU0: cpu@0 {
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
};
};
};
......@@ -77,6 +79,7 @@ CPU1: cpu@100 {
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -94,6 +97,7 @@ CPU2: cpu@200 {
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -111,6 +115,7 @@ CPU3: cpu@300 {
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -128,6 +133,7 @@ CPU4: cpu@400 {
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -145,6 +151,7 @@ CPU5: cpu@500 {
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
......@@ -163,6 +170,7 @@ CPU6: cpu@600 {
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......@@ -180,6 +188,7 @@ CPU7: cpu@700 {
clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
......
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