Merge changes from Tom Rini

arch/ppc/boot/common/crt0.S

@@ -70,7 +70,7 @@ __start:
 	## Set up the stack
 
 	lis	r9,_start@h		# r9 = &_start (text section entry)
-	addi	r9,r9,_start@l
+	ori	r9,r9,_start@l
 	subi	r1,r9,64		# Start the stack 64 bytes below _start
 	clrrwi	r1,r1,4			# Make sure it is aligned on 16 bytes.
 	li	r0,0

arch/ppc/boot/prep/head.S

 #include <asm/ppc_asm.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 #include <asm/cache.h>
 
 	.text

arch/ppc/boot/simple/head.S

@@ -14,7 +14,7 @@
  */
 
 #include <linux/config.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 #include <asm/cache.h>
 #include <asm/ppc_asm.h>
 

arch/ppc/boot/simple/misc-embedded.c

@@ -13,7 +13,6 @@
 #include <asm/bootinfo.h>
 #include <asm/mmu.h>
 #include <asm/page.h>
-#include <asm/processor.h>
 #include <asm/residual.h>
 #if defined(CONFIG_4xx)
 #include <asm/ibm4xx.h>

arch/ppc/boot/simple/misc-ev64260.S

@@ -13,7 +13,6 @@
  */
 
 #include <asm/ppc_asm.h>
-#include <asm/processor.h>
 #include <asm/cache.h>
 #include <asm/gt64260_defs.h>
 

arch/ppc/boot/simple/misc-spruce.c

@@ -20,7 +20,6 @@
 #include <linux/pci.h>
 
 #include <asm/page.h>
-#include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/bootinfo.h>
 

arch/ppc/boot/simple/misc.c

@@ -22,12 +22,12 @@
 #include <linux/string.h>
 
 #include <asm/page.h>
-#include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/bootinfo.h>
 #ifdef CONFIG_44x
 #include <asm/ibm4xx.h>
 #endif
+#include <asm/reg.h>
 
 #include "nonstdio.h"
 #include "zlib.h"

arch/ppc/boot/simple/relocate.S

@@ -16,7 +16,6 @@
  */
 
 #include <linux/config.h>
-#include <asm/processor.h>
 #include <asm/cache.h>
 #include <asm/ppc_asm.h>
 

arch/ppc/kernel/entry.S

@@ -844,7 +844,7 @@ _GLOBAL(enter_rtas)
 	LOAD_MSR_KERNEL(r0,MSR_KERNEL)
 	SYNC			/* disable interrupts so SRR0/1 */
 	MTMSRD(r0)		/* don't get trashed */
-	li	r9,MSR_
+	li	r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
 	mtlr	r6
 	CLR_TOP32(r7)
 	mtspr	SPRG2,r7

arch/ppc/kernel/head.S

@@ -315,7 +315,7 @@ __secondary_hold:
 	stw	r1,GPR1(r11);	\
 	stw	r1,0(r11);	\
 	tovirt(r1,r11);			/* set new kernel sp */	\
-	li	r10,MSR_;		/* can now take exceptions again */ \
+	li	r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
 	MTMSRD(r10);			/* (except for mach check in rtas) */ \
 	stw	r0,GPR0(r11);	\
 	SAVE_4GPRS(3, r11);	\

arch/ppc/kernel/head_44x.S

@@ -974,7 +974,7 @@ _GLOBAL(giveup_fpu)
  */
 _GLOBAL(abort)
         mfspr   r13,SPRN_DBCR0
-        oris    r13,r13,DBCR_RST(DBCR_RST_SYSTEM)@h
+        oris    r13,r13,DBCR0_RST_SYSTEM@h
         mtspr   SPRN_DBCR0,r13
 
 _GLOBAL(set_context)

arch/ppc/kernel/head_4xx.S

@@ -983,7 +983,7 @@ initial_mmu:
 
 _GLOBAL(abort)
         mfspr   r13,SPRN_DBCR0
-        oris    r13,r13,DBCR_RST(DBCR_RST_SYSTEM)@h
+        oris    r13,r13,DBCR0_RST_SYSTEM@h
         mtspr   SPRN_DBCR0,r13
 
 _GLOBAL(set_context)

arch/ppc/kernel/idle.c

@@ -26,7 +26,6 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/cache.h>
 #include <asm/cputable.h>

arch/ppc/kernel/idle_6xx.S

@@ -32,8 +32,7 @@
  * values for some CPU specific registers. Called with r24
  * containing CPU number and r3 reloc offset
  */
- 	.globl	init_idle_6xx
-init_idle_6xx:
+_GLOBAL(init_idle_6xx)
 BEGIN_FTR_SECTION
 	mfspr	r4,SPRN_HID0
 	rlwinm	r4,r4,0,10,8	/* Clear NAP */
@@ -61,8 +60,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
  * split into several functions & changing the function pointer
  * depending on the various features.
  */
-	.globl	ppc6xx_idle
-ppc6xx_idle:
+_GLOBAL(ppc6xx_idle)
 	/* Check if we can nap or doze, put HID0 mask in r3
 	 */
 	lis	r3, 0
@@ -173,8 +171,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  * we are called with DR/IR still off and r2 containing physical
  * address of current.
  */
- 	.globl power_save_6xx_restore
-power_save_6xx_restore:
+_GLOBAL(power_save_6xx_restore)
 	mfspr	r11,SPRN_HID0
 	rlwinm.	r11,r11,0,10,8	/* Clear NAP & copy NAP bit !state to cr1 EQ */
 	cror	4*cr1+eq,4*cr0+eq,4*cr0+eq
@@ -217,26 +214,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
 
 	.data
 
-	.globl nap_save_msscr0
-nap_save_msscr0:
+_GLOBAL(nap_save_msscr0)
 	.space	4*NR_CPUS
 
-	.globl nap_save_hid1
-nap_save_hid1:
+_GLOBAL(nap_save_hid1)
 	.space	4*NR_CPUS
 
-	.globl powersave_nap
-powersave_nap:
+_GLOBAL(powersave_nap)
 	.long	0
-	.globl powersave_lowspeed
-powersave_lowspeed:
+_GLOBAL(powersave_lowspeed)
 	.long	0
 
 #ifdef DEBUG
-	.globl nap_enter_count
-nap_enter_count:
+_GLOBAL(nap_enter_count)
 	.space	4
-	.globl nap_return_count
-nap_return_count:
+_GLOBAL(nap_return_count)
 	.space	4
 #endif

arch/ppc/kernel/l2cr.S

@@ -387,9 +387,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
  * clobbers r0, r3, ctr, cr0
  *
  */
- 	.globl	__flush_disable_L1
- __flush_disable_L1:
-
+_GLOBAL(__flush_disable_L1)
 	/* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
 	DSSALL
@@ -435,8 +433,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  *
  * clobbers r3
  */
- 	.globl	__inval_enable_L1
- __inval_enable_L1:
+_GLOBAL(__inval_enable_L1)
 	/* Enable and then Flash inval the instruction & data cache */
 	mfspr	r3,SPRN_HID0
 	ori	r3,r3, HID0_ICE|HID0_ICFI|HID0_DCE|HID0_DCI

arch/ppc/kernel/ppc_htab.c

@@ -23,12 +23,12 @@
 #include <asm/uaccess.h>
 #include <asm/bitops.h>
 #include <asm/mmu.h>
-#include <asm/processor.h>
 #include <asm/residual.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/cputable.h>
 #include <asm/system.h>
+#include <asm/reg.h>
 
 static ssize_t ppc_htab_read(struct file * file, char __user * buf,
 			     size_t count, loff_t *ppos);
@@ -49,19 +49,6 @@ extern unsigned long pte_errors;
 extern unsigned int primary_pteg_full;
 extern unsigned int htab_hash_searches;
 
-/* these will go into processor.h when I'm done debugging -- Cort */
-#define MMCR0 952
-#define MMCR0_PMC1_CYCLES (0x1<<7)
-#define MMCR0_PMC1_ICACHEMISS (0x5<<7)
-#define MMCR0_PMC1_DTLB (0x6<<7)
-#define MMCR0_PMC2_DCACHEMISS (0x6)
-#define MMCR0_PMC2_CYCLES (0x1)
-#define MMCR0_PMC2_ITLB (0x7)
-#define MMCR0_PMC2_LOADMISSTIME (0x5)
-
-#define PMC1 953
-#define PMC2 954
-
 struct file_operations ppc_htab_operations = {
         .llseek =       ppc_htab_lseek,
         .read =         ppc_htab_read,
@@ -124,10 +111,9 @@ static ssize_t ppc_htab_read(struct file * file, char __user * buf,
 		return -EINVAL;
 
 	if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-		asm volatile ("mfspr %0,952 \n\t"
-		    "mfspr %1,953 \n\t"
-		    "mfspr %2,954 \n\t"
-		    : "=r" (mmcr0), "=r" (pmc1), "=r" (pmc2) );
+		mmcr0 = mfspr(SPRN_MMCR0);
+		pmc1 = mfspr(SPRN_PMC1);
+		pmc2 = mfspr(SPRN_PMC2);
 		n += sprintf( buffer + n,
 			      "604 Performance Monitoring\n"
 			      "MMCR0\t\t: %08lx %s%s ",
@@ -228,25 +214,12 @@ static ssize_t ppc_htab_write(struct file * file, const char __user * ubuffer,
 	if ( !strncmp( buffer, "size ", 5) )
 		return -EBUSY;
 
-	/* turn off performance monitoring */
-	if ( !strncmp( buffer, "off", 3) )
-	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			asm volatile ("mtspr %0, %3 \n\t"
-			    "mtspr %1, %3 \n\t"
-			    "mtspr %2, %3 \n\t"			
-			    :: "i" (MMCR0), "i" (PMC1), "i" (PMC2), "r" (0));
-		}
-	}
-
 	if ( !strncmp( buffer, "reset", 5) )
 	{
 		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
 			/* reset PMC1 and PMC2 */
-			asm volatile (
-				"mtspr 953, %0 \n\t"
-				"mtspr 954, %0 \n\t"
-				:: "r" (0));
+			mtspr(SPRN_PMC1, 0);
+			mtspr(SPRN_PMC2, 0);
 		}
 		htab_reloads = 0;
 		htab_evicts = 0;
@@ -254,116 +227,95 @@ static ssize_t ppc_htab_write(struct file * file, const char __user * ubuffer,
 		pte_errors = 0;
 	}
 
+	/* Everything below here requires the performance monitor feature. */
+	if ( !cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON )
+		return count;
+
+	/* turn off performance monitoring */
+	if ( !strncmp( buffer, "off", 3) )
+	{
+		mtspr(SPRN_MMCR0, 0);
+		mtspr(SPRN_PMC1, 0);
+		mtspr(SPRN_PMC2, 0);
+	}
+
 	if ( !strncmp( buffer, "user", 4) )
 	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			/* setup mmcr0 and clear the correct pmc */
-			asm("mfspr %0,%1\n\t"  : "=r" (tmp) : "i" (MMCR0));
-			tmp &= ~(0x60000000);
-			tmp |= 0x20000000;
-			asm volatile (
-				"mtspr %1,%0 \n\t"    /* set new mccr0 */
-				"mtspr %3,%4 \n\t"    /* reset the pmc */
-				"mtspr %5,%4 \n\t"    /* reset the pmc2 */
-				:: "r" (tmp), "i" (MMCR0), "i" (0),
-				"i" (PMC1),  "r" (0), "i"(PMC2) );
-		}
+		/* setup mmcr0 and clear the correct pmc */
+		tmp = (mfspr(SPRN_MMCR0) & ~(0x60000000)) | 0x20000000;
+		mtspr(SPRN_MMCR0, tmp);
+		mtspr(SPRN_PMC1, 0);
+		mtspr(SPRN_PMC2, 0);
 	}
 
 	if ( !strncmp( buffer, "kernel", 6) )
 	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			/* setup mmcr0 and clear the correct pmc */
-			asm("mfspr %0,%1\n\t"  : "=r" (tmp) : "i" (MMCR0));
-			tmp &= ~(0x60000000);
-			tmp |= 0x40000000;
-			asm volatile (
-				"mtspr %1,%0 \n\t"    /* set new mccr0 */
-				"mtspr %3,%4 \n\t"    /* reset the pmc */
-				"mtspr %5,%4 \n\t"    /* reset the pmc2 */
-				:: "r" (tmp), "i" (MMCR0), "i" (0),
-				"i" (PMC1),  "r" (0), "i"(PMC2) );
-		}
+		/* setup mmcr0 and clear the correct pmc */
+		tmp = (mfspr(SPRN_MMCR0) & ~(0x60000000)) | 0x40000000;
+		mtspr(SPRN_MMCR0, tmp);
+		mtspr(SPRN_PMC1, 0);
+		mtspr(SPRN_PMC2, 0);
 	}
 
 	/* PMC1 values */
 	if ( !strncmp( buffer, "dtlb", 4) )
 	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			/* setup mmcr0 and clear the correct pmc */
-			asm("mfspr %0,%1\n\t"  : "=r" (tmp) : "i" (MMCR0));
-			tmp &= ~(0x7f<<7);
-			tmp |= MMCR0_PMC1_DTLB;
-			asm volatile (
-				"mtspr %1,%0 \n\t"    /* set new mccr0 */
-				"mtspr %3,%4 \n\t"    /* reset the pmc */
-				:: "r" (tmp), "i" (MMCR0), "i" (MMCR0_PMC1_DTLB),
-				"i" (PMC1),  "r" (0) );
-		}
+		/* setup mmcr0 and clear the correct pmc */
+		tmp = (mfspr(SPRN_MMCR0) & ~(0x7F << 7)) | MMCR0_PMC1_DTLB;
+		mtspr(SPRN_MMCR0, tmp);
+		mtspr(SPRN_PMC1, 0);
 	}
 
 	if ( !strncmp( buffer, "ic miss", 7) )
 	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			/* setup mmcr0 and clear the correct pmc */
-			asm("mfspr %0,%1\n\t"  : "=r" (tmp) : "i" (MMCR0));
-			tmp &= ~(0x7f<<7);
-			tmp |= MMCR0_PMC1_ICACHEMISS;
-			asm volatile (
-				"mtspr %1,%0 \n\t"    /* set new mccr0 */
-				"mtspr %3,%4 \n\t"    /* reset the pmc */
-				:: "r" (tmp), "i" (MMCR0),
-				"i" (MMCR0_PMC1_ICACHEMISS), "i" (PMC1),  "r" (0));
-		}
+		/* setup mmcr0 and clear the correct pmc */
+		tmp = (mfspr(SPRN_MMCR0) & ~(0x7F<<7)) | MMCR0_PMC1_ICACHEMISS;
+		mtspr(SPRN_MMCR0, tmp);
+		mtspr(SPRN_PMC1, 0);
 	}
 
 	/* PMC2 values */
 	if ( !strncmp( buffer, "load miss time", 14) )
 	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			/* setup mmcr0 and clear the correct pmc */
-		       asm volatile(
-			       "mfspr %0,%1\n\t"     /* get current mccr0 */
-			       "rlwinm %0,%0,0,0,31-6\n\t"  /* clear bits [26-31] */
-			       "ori   %0,%0,%2 \n\t" /* or in mmcr0 settings */
-			       "mtspr %1,%0 \n\t"    /* set new mccr0 */
-			       "mtspr %3,%4 \n\t"    /* reset the pmc */
-			       : "=r" (tmp)
-			       : "i" (MMCR0), "i" (MMCR0_PMC2_LOADMISSTIME),
-			       "i" (PMC2),  "r" (0) );
-		}
+		/* setup mmcr0 and clear the correct pmc */
+	       asm volatile(
+		       "mfspr %0,%1\n\t"     /* get current mccr0 */
+		       "rlwinm %0,%0,0,0,31-6\n\t"  /* clear bits [26-31] */
+		       "ori   %0,%0,%2 \n\t" /* or in mmcr0 settings */
+		       "mtspr %1,%0 \n\t"    /* set new mccr0 */
+		       "mtspr %3,%4 \n\t"    /* reset the pmc */
+		       : "=r" (tmp)
+		       : "i" (SPRN_MMCR0),
+		       "i" (MMCR0_PMC2_LOADMISSTIME),
+		       "i" (SPRN_PMC2),  "r" (0) );
 	}
 
 	if ( !strncmp( buffer, "itlb", 4) )
 	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			/* setup mmcr0 and clear the correct pmc */
-		       asm volatile(
-			       "mfspr %0,%1\n\t"     /* get current mccr0 */
-			       "rlwinm %0,%0,0,0,31-6\n\t"  /* clear bits [26-31] */
-			       "ori   %0,%0,%2 \n\t" /* or in mmcr0 settings */
-			       "mtspr %1,%0 \n\t"    /* set new mccr0 */
-			       "mtspr %3,%4 \n\t"    /* reset the pmc */
-			       : "=r" (tmp)
-			       : "i" (MMCR0), "i" (MMCR0_PMC2_ITLB),
-			       "i" (PMC2),  "r" (0) );
-		}
+		/* setup mmcr0 and clear the correct pmc */
+	       asm volatile(
+		       "mfspr %0,%1\n\t"     /* get current mccr0 */
+		       "rlwinm %0,%0,0,0,31-6\n\t"  /* clear bits [26-31] */
+		       "ori   %0,%0,%2 \n\t" /* or in mmcr0 settings */
+		       "mtspr %1,%0 \n\t"    /* set new mccr0 */
+		       "mtspr %3,%4 \n\t"    /* reset the pmc */
+		       : "=r" (tmp)
+		       : "i" (SPRN_MMCR0), "i" (MMCR0_PMC2_ITLB),
+		       "i" (SPRN_PMC2),  "r" (0) );
 	}
 
 	if ( !strncmp( buffer, "dc miss", 7) )
 	{
-		if (cur_cpu_spec[0]->cpu_features & CPU_FTR_604_PERF_MON) {
-			/* setup mmcr0 and clear the correct pmc */
-		       asm volatile(
-			       "mfspr %0,%1\n\t"     /* get current mccr0 */
-			       "rlwinm %0,%0,0,0,31-6\n\t"  /* clear bits [26-31] */
-			       "ori   %0,%0,%2 \n\t" /* or in mmcr0 settings */
-			       "mtspr %1,%0 \n\t"    /* set new mccr0 */
-			       "mtspr %3,%4 \n\t"    /* reset the pmc */
-			       : "=r" (tmp)
-			       : "i" (MMCR0), "i" (MMCR0_PMC2_DCACHEMISS),
-			       "i" (PMC2),  "r" (0) );
-		}
+		/* setup mmcr0 and clear the correct pmc */
+	       asm volatile(
+		       "mfspr %0,%1\n\t"     /* get current mccr0 */
+		       "rlwinm %0,%0,0,0,31-6\n\t"  /* clear bits [26-31] */
+		       "ori   %0,%0,%2 \n\t" /* or in mmcr0 settings */
+		       "mtspr %1,%0 \n\t"    /* set new mccr0 */
+		       "mtspr %3,%4 \n\t"    /* reset the pmc */
+		       : "=r" (tmp)
+		       : "i" (SPRN_MMCR0), "i" (MMCR0_PMC2_DCACHEMISS),
+		       "i" (SPRN_PMC2),  "r" (0) );
 	}
 
 	return count;

arch/ppc/kernel/softemu8xx.c

@@ -30,7 +30,6 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 #include <asm/io.h>
-#include <asm/processor.h>
 
 extern void
 print_8xx_pte(struct mm_struct *mm, unsigned long addr);

arch/ppc/kernel/temp.c

@@ -23,7 +23,7 @@
 
 #include <asm/segment.h>
 #include <asm/io.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 #include <asm/nvram.h>
 #include <asm/cache.h>
 #include <asm/8xx_immap.h>

arch/ppc/kernel/time.c

@@ -59,7 +59,6 @@
 
 #include <asm/segment.h>
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/nvram.h>
 #include <asm/cache.h>
 #include <asm/8xx_immap.h>

arch/ppc/kernel/traps.c

@@ -35,7 +35,7 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 #include <asm/io.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 #include <asm/xmon.h>
 #ifdef CONFIG_PMAC_BACKLIGHT
 #include <asm/backlight.h>

arch/ppc/lib/locks.c

@@ -4,14 +4,11 @@
  * Written by Cort Dougan (cort@cs.nmt.edu)
  */
 
-
-#include <linux/kernel.h>
+#include <linux/config.h>
 #include <linux/sched.h>
-#include <linux/delay.h>
 #include <linux/spinlock.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/io.h>
+#include <asm/ppc_asm.h>
+#include <asm/smp.h>
 
 #ifdef CONFIG_DEBUG_SPINLOCK
 

arch/ppc/math-emu/math.c

@@ -9,7 +9,7 @@
 #include <linux/sched.h>
 
 #include <asm/uaccess.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 
 #include "sfp-machine.h"
 #include "double.h"

arch/ppc/mm/hashtable.S

@@ -49,8 +49,7 @@
  * Uses r0, r3 - r8, ctr, lr.
  */
 	.text
-	.globl	hash_page
-hash_page:
+_GLOBAL(hash_page)
 #ifdef CONFIG_PPC64BRIDGE
 	mfmsr	r0
 	clrldi	r0,r0,1		/* make sure it's in 32-bit mode */
@@ -337,8 +336,7 @@ _GLOBAL(create_hpte)
 	SET_V(r5)			/* set V (valid) bit */
 
 	/* Get the address of the primary PTE group in the hash table (r3) */
-	.globl	hash_page_patch_A
-hash_page_patch_A:
+_GLOBAL(hash_page_patch_A)
 	addis	r0,r7,Hash_base@h	/* base address of hash table */
 	rlwimi	r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT    /* VSID -> hash */
 	rlwinm	r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
@@ -368,8 +366,7 @@ hash_page_patch_A:
 
 	/* Search the secondary PTEG for a matching PTE */
 	ori	r5,r5,PTE_H		/* set H (secondary hash) bit */
-	.globl	hash_page_patch_B
-hash_page_patch_B:
+_GLOBAL(hash_page_patch_B)
 	xoris	r4,r3,Hash_msk>>16	/* compute secondary hash */
 	xori	r4,r4,(-PTEG_SIZE & 0xffff)
 	addi	r4,r4,-PTE_SIZE
@@ -396,8 +393,7 @@ hash_page_patch_B:
 
 	/* Search the secondary PTEG for an empty slot */
 	ori	r5,r5,PTE_H		/* set H (secondary hash) bit */
-	.globl	hash_page_patch_C
-hash_page_patch_C:
+_GLOBAL(hash_page_patch_C)
 	xoris	r4,r3,Hash_msk>>16	/* compute secondary hash */
 	xori	r4,r4,(-PTEG_SIZE & 0xffff)
 	addi	r4,r4,-PTE_SIZE
@@ -562,8 +558,7 @@ _GLOBAL(flush_hash_pages)
 	bne-	33b
 
 	/* Get the address of the primary PTE group in the hash table (r3) */
-	.globl	flush_hash_patch_A
-flush_hash_patch_A:
+_GLOBAL(flush_hash_patch_A)
 	addis	r8,r7,Hash_base@h	/* base address of hash table */
 	rlwimi	r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT    /* VSID -> hash */
 	rlwinm	r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
@@ -581,8 +576,7 @@ flush_hash_patch_A:
 	/* Search the secondary PTEG for a matching PTE */
 	ori	r11,r11,PTE_H		/* set H (secondary hash) bit */
 	li	r0,8			/* PTEs/group */
-	.globl	flush_hash_patch_B
-flush_hash_patch_B:
+_GLOBAL(flush_hash_patch_B)
 	xoris	r12,r8,Hash_msk>>16	/* compute secondary hash */
 	xori	r12,r12,(-PTEG_SIZE & 0xffff)
 	addi	r12,r12,-PTE_SIZE

arch/ppc/platforms/4xx/oak_setup.c

@@ -22,7 +22,6 @@
 #include <linux/irq.h>
 #include <linux/seq_file.h>
 
-#include <asm/processor.h>
 #include <asm/board.h>
 #include <asm/machdep.h>
 #include <asm/page.h>

arch/ppc/platforms/4xx/sycamore.c

@@ -24,7 +24,6 @@
 #include <asm/ppc4xx_pic.h>
 #include <asm/system.h>
 #include <asm/pci-bridge.h>
-#include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/page.h>
 #include <asm/time.h>

arch/ppc/platforms/4xx/walnut.c

@@ -24,7 +24,6 @@
 
 #include <asm/system.h>
 #include <asm/pci-bridge.h>
-#include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/page.h>
 #include <asm/time.h>

arch/ppc/platforms/chrp_setup.c

@@ -38,7 +38,6 @@
 #include <linux/root_dev.h>
 #include <linux/initrd.h>
 
-#include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/prom.h>

arch/ppc/platforms/chrp_time.c

@@ -24,7 +24,6 @@
 
 #include <asm/segment.h>
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/nvram.h>
 #include <asm/prom.h>
 #include <asm/sections.h>

arch/ppc/platforms/gemini_prom.S

@@ -9,13 +9,11 @@
  */
 
 #include <linux/config.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 #include <asm/page.h>
 #include <platforms/gemini.h>
 #include <asm/ppc_asm.h>
 
-#define HID0_ABE (1<<3)
-
 /*
  *  On 750's the MMU is on when Linux is booted, so we need to clear out the
  *  bootloader's BAT settings, make sure we're in supervisor state (gotcha!),

arch/ppc/platforms/pmac_setup.c

@@ -52,7 +52,7 @@
 #include <linux/seq_file.h>
 #include <linux/root_dev.h>
 
-#include <asm/processor.h>
+#include <asm/reg.h>
 #include <asm/sections.h>
 #include <asm/prom.h>
 #include <asm/system.h>

arch/ppc/platforms/pplus_pci.c

@@ -27,7 +27,6 @@
 #include <asm/ptrace.h>
 #include <asm/pci-bridge.h>
 #include <asm/residual.h>
-#include <asm/processor.h>
 #include <asm/irq.h>
 #include <asm/machdep.h>
 
@@ -529,4 +528,3 @@ pplus_setup_hose(void)
 	ppc_md.pci_swizzle = common_swizzle;
 	pplus_set_board_type();
 }
-

arch/ppc/platforms/pplus_setup.c

@@ -46,7 +46,6 @@
 
 #include <asm/sections.h>
 #include <asm/mmu.h>
-#include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/residual.h>
 #include <asm/io.h>

arch/ppc/platforms/prep_pci.c

@@ -19,7 +19,6 @@
 #include <asm/prom.h>
 #include <asm/pci-bridge.h>
 #include <asm/residual.h>
-#include <asm/processor.h>
 #include <asm/irq.h>
 #include <asm/machdep.h>
 #include <asm/open_pic.h>

arch/ppc/platforms/prep_time.c

@@ -24,7 +24,6 @@
 #include <asm/sections.h>
 #include <asm/segment.h>
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/prep_nvram.h>
 #include <asm/mk48t59.h>

arch/ppc/platforms/residual.c

@@ -42,7 +42,6 @@
 
 #include <asm/sections.h>
 #include <asm/mmu.h>
-#include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/ide.h>

arch/ppc/syslib/btext.c

@@ -17,7 +17,7 @@
 #include <asm/mmu.h>
 #include <asm/pgtable.h>
 #include <asm/io.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 
 #define NO_SCROLL
 

arch/ppc/syslib/cpc700_pic.c

@@ -21,7 +21,6 @@
 #include <linux/irq.h>
 
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/irq.h>
 

arch/ppc/syslib/gt64260_pic.c

@@ -41,7 +41,6 @@
 #include <linux/irq.h>
 
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/gt64260.h>
@@ -240,4 +239,3 @@ gt64260_mask_irq(unsigned int irq)
 		udelay(1);
 	}
 }
-

arch/ppc/syslib/ibm440gp_common.c

@@ -17,6 +17,7 @@
  */
 #include <linux/config.h>
 #include <linux/types.h>
+#include <asm/reg.h>
 #include <asm/ibm44x.h>
 #include <asm/mmu.h>
 

arch/ppc/syslib/m8260_setup.c

@@ -34,7 +34,6 @@
 #include <linux/seq_file.h>
 
 #include <asm/mmu.h>
-#include <asm/processor.h>
 #include <asm/residual.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
@@ -260,4 +259,3 @@ m8260_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	ppc_md.find_end_of_memory	= m8260_find_end_of_memory;
 	ppc_md.setup_io_mappings	= m8260_map_io;
 }
-

arch/ppc/syslib/m8xx_setup.c

@@ -35,7 +35,7 @@
 #include <linux/root_dev.h>
 
 #include <asm/mmu.h>
-#include <asm/processor.h>
+#include <asm/reg.h>
 #include <asm/residual.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
@@ -221,9 +221,7 @@ m8xx_restart(char *cmd)
 
 	/* Clear the ME bit in MSR to cause checkstop on machine check
 	*/
-	__asm__("mfmsr %0" : "=r" (msr) );
-	msr &= ~0x1000;
-	__asm__("mtmsr %0" : : "r" (msr) );
+	mtmsr(mfmsr(msr) & ~0x1000);
 
 	dummy = ((immap_t *)IMAP_ADDR)->im_clkrst.res[0];
 	printk("Restart failed\n");

arch/ppc/syslib/prep_nvram.c

@@ -17,7 +17,6 @@
 #include <asm/sections.h>
 #include <asm/segment.h>
 #include <asm/io.h>
-#include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/prep_nvram.h>
 
@@ -140,6 +139,3 @@ char __prep *prep_nvram_next_var(char *name)
 		return NULL;
 	}
 }
-
-
-

arch/ppc/syslib/prom_init.c

@@ -19,7 +19,6 @@
 #include <asm/sections.h>
 #include <asm/prom.h>
 #include <asm/page.h>
-#include <asm/processor.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/smp.h>

arch/ppc/xmon/start_8xx.c

@@ -12,7 +12,6 @@
 #include <asm/io.h>
 #include <asm/page.h>
 #include <linux/kernel.h>
-#include <asm/processor.h>
 #include <asm/8xx_immap.h>
 #include <asm/mpc8xx.h>
 #include <asm/commproc.h>

include/asm-ppc/cache.h

@@ -6,7 +6,6 @@
 #define __ARCH_PPC_CACHE_H
 
 #include <linux/config.h>
-#include <asm/processor.h>
 
 /* bytes per L1 cache line */
 #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)

include/asm-ppc/hw_irq.h

@@ -5,15 +5,14 @@
 #ifndef _PPC_HW_IRQ_H
 #define _PPC_HW_IRQ_H
 
+#include <asm/ptrace.h>
+#include <asm/reg.h>
+
 extern void timer_interrupt(struct pt_regs *);
 extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
 
 #define INLINE_IRQS
 
-#define mfmsr()		({unsigned int rval; \
-			asm volatile("mfmsr %0" : "=r" (rval)); rval;})
-#define mtmsr(v)	asm volatile("mtmsr %0" : : "r" (v))
-
 #define irqs_disabled()	((mfmsr() & MSR_EE) == 0)
 
 #ifdef INLINE_IRQS

include/asm-ppc/ibm4xx.h

@@ -16,48 +16,6 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_4xx
-
-#ifndef __ASSEMBLY__
-
-/* Device Control Registers */
-
-#define stringify(s)	tostring(s)
-#define tostring(s)	#s
-
-#define mfdcr(rn) mfdcr_or_dflt(rn, 0)
-
-#define mfdcr_or_dflt(rn,default_rval) \
-	({unsigned int rval;						\
-	if (rn == 0)							\
-		rval = default_rval;					\
-	else								\
-		asm volatile("mfdcr %0," stringify(rn) : "=r" (rval));	\
-	rval;})
-
-#define mtdcr(rn, v)  \
-do {                  \
-	if (rn != 0) \
-		asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v));	\
-} while (0)
-
-/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
-
-#define mfdcri(base, reg)			\
-({						\
-     mtdcr(base##_CFGADDR, base##_##reg);	\
-     mfdcr(base##_CFGDATA);			\
-})
-
-#define mtdcri(base, reg, data)			\
-do {						\
-     mtdcr(base##_CFGADDR, base##_##reg);	\
-     mtdcr(base##_CFGDATA, data);		\
-} while (0)
-#endif /* __ASSEMBLY__ */
-
-#endif /* CONFIG_4xx */
-
 #ifdef CONFIG_40x
 
 #if defined(CONFIG_ASH)

include/asm-ppc/ide.h

@@ -13,7 +13,6 @@
 #ifdef __KERNEL__
 
 #include <linux/sched.h>
-#include <asm/processor.h>
 #include <asm/mpc8xx.h>
 
 #ifndef MAX_HWIFS

include/asm-ppc/pgalloc.h

@@ -4,7 +4,6 @@
 
 #include <linux/config.h>
 #include <linux/threads.h>
-#include <asm/processor.h>
 
 extern void __bad_pte(pmd_t *pmd);
 

include/asm-ppc/serial.h

@@ -37,7 +37,6 @@
  * This is true for PReP and CHRP at least.
  */
 #include <asm/pc_serial.h>
-#include <asm/processor.h>
 
 #if defined(CONFIG_MAC_SERIAL)
 #define SERIAL_DEV_OFFSET	((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2)

include/asm-ppc/spinlock.h

@@ -2,7 +2,6 @@
 #define __ASM_SPINLOCK_H
 
 #include <asm/system.h>
-#include <asm/processor.h>
 
 /*
  * Simple spin lock operations.

include/asm-ppc/system.h

@@ -7,7 +7,6 @@
 #include <linux/config.h>
 #include <linux/kernel.h>
 
-#include <asm/processor.h>
 #include <asm/atomic.h>
 #include <asm/hw_irq.h>
 
@@ -50,6 +49,9 @@
 #endif /* CONFIG_SMP */
 
 #ifdef __KERNEL__
+struct task_struct;
+struct pt_regs;
+
 extern void print_backtrace(unsigned long *);
 extern void show_regs(struct pt_regs * regs);
 extern void flush_instruction_cache(void);
@@ -83,7 +85,6 @@ extern void cacheable_memzero(void *p, unsigned int nb);
 struct device_node;
 extern void note_scsi_host(struct device_node *, void *);
 
-struct task_struct;
 extern struct task_struct *__switch_to(struct task_struct *,
 	struct task_struct *);
 #define switch_to(prev, next, last)	((last) = __switch_to((prev), (next)))
@@ -94,7 +95,6 @@ extern struct task_struct *_switch(struct thread_struct *prev,
 
 extern unsigned int rtas_data;
 
-struct pt_regs;
 extern void dump_regs(struct pt_regs *);
 
 static __inline__ unsigned long

include/asm-ppc/thread_info.h

@@ -9,9 +9,6 @@
 #define _ASM_THREAD_INFO_H
 
 #ifdef __KERNEL__
-
-#include <asm/processor.h>
-
 #ifndef __ASSEMBLY__
 /*
  * low level task data.

include/asm-ppc/time.h

@@ -13,7 +13,7 @@
 #include <linux/mc146818rtc.h>
 #include <linux/threads.h>
 
-#include <asm/processor.h>
+#include <asm/reg.h>
 
 /* time.c */
 extern unsigned tb_ticks_per_jiffy;

include/asm-ppc/tlbflush.h

@@ -12,7 +12,6 @@
 
 #include <linux/config.h>
 #include <linux/mm.h>
-#include <asm/processor.h>
 
 extern void _tlbie(unsigned long address);
 extern void _tlbia(void);