Commit 94801e5c authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'pinctrl-v5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:
 "Here is a late set of pin control fixes for v5.10, most concern some
  minor and major issues found in the Intel drivers. Some are so hairy
  that I have no idea what is going on there, but luckily the maintainer
  knows what's up.

  We also have an interesting fix for AMD, which makes AMD-based laptops
  more stable IIUC.

  Summary:

   - Fix up some SPI group and a register offset on Intel Jasperlake

   - Set default bias on Intel Merrifield

   - Preserve debouncing on Intel Baytrail

   - Stop .set_type() irqchip callback in the AMD driver from fiddling
     with the debounce filter

   - Fix access to GPIO banks that are pass-thru on the Aspeed

   - Fix a fix for the Intel pin control driver to disable Rx/Tx when
     requesting a UART line as GPIO"

* tag 'pinctrl-v5.10-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: intel: Actually disable Tx and Rx buffers on GPIO request
  pinctrl: aspeed: Fix GPIO requests on pass-through banks
  pinctrl: amd: remove debounce filter setting in IRQ type setting
  pinctrl: baytrail: Avoid clearing debounce value when turning it off
  pinctrl: merrifield: Set default bias in case no particular value given
  pinctrl: jasperlake: Fix HOSTSW_OWN offset
  pinctrl: jasperlake: Unhide SPI group of pins
parents 6d47cdec e8873c0a
......@@ -286,14 +286,76 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)
{
/*
* The signal type is GPIO if the signal name has "GPI" as a prefix.
* strncmp (rather than strcmp) is used to implement the prefix
* requirement.
* We need to differentiate between GPIO and non-GPIO signals to
* implement the gpio_request_enable() interface. For better or worse
* the ASPEED pinctrl driver uses the expression names to determine
* whether an expression will mux a pin for GPIO.
*
* expr->signal might look like "GPIOB1" in the GPIO case.
* expr->signal might look like "GPIT0" in the GPI case.
* Generally we have the following - A GPIO such as B1 has:
*
* - expr->signal set to "GPIOB1"
* - expr->function set to "GPIOB1"
*
* Using this fact we can determine whether the provided expression is
* a GPIO expression by testing the signal name for the string prefix
* "GPIO".
*
* However, some GPIOs are input-only, and the ASPEED datasheets name
* them differently. An input-only GPIO such as T0 has:
*
* - expr->signal set to "GPIT0"
* - expr->function set to "GPIT0"
*
* It's tempting to generalise the prefix test from "GPIO" to "GPI" to
* account for both GPIOs and GPIs, but in doing so we run aground on
* another feature:
*
* Some pins in the ASPEED BMC SoCs have a "pass-through" GPIO
* function where the input state of one pin is replicated as the
* output state of another (as if they were shorted together - a mux
* configuration that is typically enabled by hardware strapping).
* This feature allows the BMC to pass e.g. power button state through
* to the host while the BMC is yet to boot, but take control of the
* button state once the BMC has booted by muxing each pin as a
* separate, pin-specific GPIO.
*
* Conceptually this pass-through mode is a form of GPIO and is named
* as such in the datasheets, e.g. "GPID0". This naming similarity
* trips us up with the simple GPI-prefixed-signal-name scheme
* discussed above, as the pass-through configuration is not what we
* want when muxing a pin as GPIO for the GPIO subsystem.
*
* On e.g. the AST2400, a pass-through function "GPID0" is grouped on
* balls A18 and D16, where we have:
*
* For ball A18:
* - expr->signal set to "GPID0IN"
* - expr->function set to "GPID0"
*
* For ball D16:
* - expr->signal set to "GPID0OUT"
* - expr->function set to "GPID0"
*
* By contrast, the pin-specific GPIO expressions for the same pins are
* as follows:
*
* For ball A18:
* - expr->signal looks like "GPIOD0"
* - expr->function looks like "GPIOD0"
*
* For ball D16:
* - expr->signal looks like "GPIOD1"
* - expr->function looks like "GPIOD1"
*
* Testing both the signal _and_ function names gives us the means
* differentiate the pass-through GPIO pinmux configuration from the
* pin-specific configuration that the GPIO subsystem is after: An
* expression is a pin-specific (non-pass-through) GPIO configuration
* if the signal prefix is "GPI" and the signal name matches the
* function name.
*/
return strncmp(expr->signal, "GPI", 3) == 0;
return !strncmp(expr->signal, "GPI", 3) &&
!strcmp(expr->signal, expr->function);
}
static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
......
......@@ -452,10 +452,11 @@ struct aspeed_sig_desc {
* evaluation of the descriptors.
*
* @signal: The signal name for the priority level on the pin. If the signal
* type is GPIO, then the signal name must begin with the string
* "GPIO", e.g. GPIOA0, GPIOT4 etc.
* type is GPIO, then the signal name must begin with the
* prefix "GPI", e.g. GPIOA0, GPIT0 etc.
* @function: The name of the function the signal participates in for the
* associated expression
* associated expression. For pin-specific GPIO, the function
* name must match the signal name.
* @ndescs: The number of signal descriptors in the expression
* @descs: Pointer to an array of signal descriptors that comprise the
* function expression
......
......@@ -1049,7 +1049,6 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
break;
case PIN_CONFIG_INPUT_DEBOUNCE:
debounce = readl(db_reg);
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
if (arg)
conf |= BYT_DEBOUNCE_EN;
......@@ -1058,24 +1057,31 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
switch (arg) {
case 375:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_375US;
break;
case 750:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_750US;
break;
case 1500:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_1500US;
break;
case 3000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_3MS;
break;
case 6000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_6MS;
break;
case 12000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_12MS;
break;
case 24000:
debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
debounce |= BYT_DEBOUNCE_PULSE_24MS;
break;
default:
......
......@@ -442,8 +442,8 @@ static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
value |= PADCFG0_PMODE_GPIO;
/* Disable input and output buffers */
value &= ~PADCFG0_GPIORXDIS;
value &= ~PADCFG0_GPIOTXDIS;
value |= PADCFG0_GPIORXDIS;
value |= PADCFG0_GPIOTXDIS;
/* Disable SCI/SMI/NMI generation */
value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
......
This diff is collapsed.
......@@ -745,6 +745,10 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
bits |= BUFCFG_PU_EN;
/* Set default strength value in case none is given */
if (arg == 1)
arg = 20000;
switch (arg) {
case 50000:
bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
......@@ -765,6 +769,10 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
bits |= BUFCFG_PD_EN;
/* Set default strength value in case none is given */
if (arg == 1)
arg = 20000;
switch (arg) {
case 50000:
bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
......
......@@ -429,7 +429,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
......@@ -437,7 +436,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
......@@ -445,7 +443,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
......@@ -453,8 +450,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
......@@ -462,8 +457,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
......
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