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Commit 955d8f3e authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'omap-for-v5.6/ti-sysc-drop-pdata-crypto-signed' of... 

Merge tag 'omap-for-v5.6/ti-sysc-drop-pdata-crypto-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late

Late changes for omap secure accelerators for v5.6 merge window

A series of changes to configure secure accelerators for omap4 & 5
to finally get hardware random number generator working.

Apologies on a late pull request on these changes, but this pull
request could not be sent out earlier because of a dependency to
recent clock changes. This is based on earlier changes to drop omap
legacy platform data with Tero Kristo's for-5.6-ti-clk branch merged
in.

* tag 'omap-for-v5.6/ti-sysc-drop-pdata-crypto-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (98 commits)
  ARM: OMAP2+: Drop legacy platform data for omap4 des
  ARM: OMAP2+: Drop legacy platform data for omap4 sham
  ARM: OMAP2+: Drop legacy platform data for omap4 aes
  ARM: dts: Configure interconnect target module for omap4 des
  ARM: dts: Configure interconnect target module for omap4 aes
  ARM: dts: Configure interconnect target module for omap4 sham
  ARM: dts: Configure omap5 rng to probe with ti-sysc
  ARM: dts: Configure omap4 rng to probe with ti-sysc
  ARM: dts: Add missing omap5 secure clocks
  ARM: dts: Add missing omap4 secure clocks
  clk: ti: clkctrl: Fix hidden dependency to node name
  clk: ti: add clkctrl data dra7 sgx
  clk: ti: omap5: Add missing AESS clock
  clk: ti: dra7: fix parent for gmac_clkctrl
  clk: ti: dra7: add vpe clkctrl data
  clk: ti: dra7: add cam clkctrl data
  dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock
  dmaengine: ti: omap-dma: don't allow a null od->plat pointer to be dereferenced
  ARM: OMAP2+: Drop legacy platform data for sdma
  ARM: OMAP2+: Drop legacy init for sdma
  ...

Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-2Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents d1eef1c6 885d21e4
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Showing with 1383 additions and 5226 deletions
Documentation/devicetree/bindings/clock/ti-clkctrl.txt
View file @ 955d8f3e
......@@ -16,18 +16,23 @@ For more information, please see the Linux clock framework binding at
Documentation/devicetree/bindings/clock/clock-bindings.txt.
Required properties :
- compatible : shall be "ti,clkctrl"
- compatible : shall be "ti,clkctrl" or a clock domain specific name:
"ti,clkctrl-l4-cfg"
"ti,clkctrl-l4-per"
"ti,clkctrl-l4-secure"
"ti,clkctrl-l4-wkup"
- #clock-cells : shall contain 2 with the first entry being the instance
offset from the clock domain base and the second being the
clock index
- reg : clock registers
Example: Clock controller node on omap 4430:
&cm2 {
l4per: cm@1400 {
cm_l4per@0 {
cm_l4per_clkctrl: clk@20 {
compatible = "ti,clkctrl";
cm_l4per_clkctrl: clock@20 {
compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
reg = <0x20 0x1b0>;
#clock-cells = <2>;
};
......
Documentation/devicetree/bindings/clock/ti/dra7-atl.txt
View file @ 955d8f3e
......@@ -43,7 +43,7 @@ Configuration of ATL instances:
- aws : Audio word select signal selection
};
For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include
For valid word select signals, see the dt-bindings/clock/ti-dra7-atl.h include
file.
Examples:
......@@ -83,7 +83,7 @@ atl: atl@4843c000 {
clock-names = "fck";
};
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/clock/ti-dra7-atl.h>
&atl {
......
arch/arm/boot/dts/am335x-sancloud-bbe.dts
View file @ 955d8f3e
......@@ -108,7 +108,7 @@ ethphy0: ethernet-phy@0 {
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-txid";
phy-mode = "rgmii-id";
};
&i2c0 {
......
arch/arm/boot/dts/am33xx-l4.dtsi
View file @ 955d8f3e
......@@ -225,7 +225,6 @@ i2c0: i2c@0 {
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
......@@ -1009,7 +1008,6 @@ i2c1: i2c@0 {
target-module@30000 { /* 0x48030000, ap 77 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
......@@ -1134,7 +1132,6 @@ timer2: timer@0 {
target-module@42000 { /* 0x48042000, ap 24 1c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
......@@ -1160,7 +1157,6 @@ timer3: timer@0 {
target-module@44000 { /* 0x48044000, ap 26 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
......@@ -1187,7 +1183,6 @@ timer4: timer@0 {
target-module@46000 { /* 0x48046000, ap 28 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
......@@ -1214,7 +1209,6 @@ timer5: timer@0 {
target-module@48000 { /* 0x48048000, ap 30 22.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
......@@ -1241,7 +1235,6 @@ timer6: timer@0 {
target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
......@@ -1344,7 +1337,6 @@ mmc1: mmc@0 {
target-module@80000 { /* 0x48080000, ap 38 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
......@@ -1412,7 +1404,6 @@ mbox_wkupm3: wkup_m3 {
target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
......@@ -1533,7 +1524,6 @@ i2c2: i2c@0 {
target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
......@@ -1749,7 +1739,6 @@ target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
......@@ -1773,7 +1762,6 @@ target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
......@@ -1863,7 +1851,6 @@ segment@300000 { /* 0x48300000 */
target-module@0 { /* 0x48300000, ap 66 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
......@@ -1916,7 +1903,6 @@ ehrpwm0: pwm@200 {
target-module@2000 { /* 0x48302000, ap 68 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
......@@ -1969,7 +1955,6 @@ ehrpwm1: pwm@200 {
target-module@4000 { /* 0x48304000, ap 70 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
......@@ -2022,7 +2007,6 @@ ehrpwm2: pwm@200 {
target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "lcdc";
reg = <0xe000 0x4>,
<0xe054 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/am33xx.dtsi
View file @ 955d8f3e
......@@ -439,23 +439,62 @@ gpmc: gpmc@50000000 {
status = "disabled";
};
sham: sham@53100000 {
compatible = "ti,omap4-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
};
};
aes: aes@53500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53500000 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53500080 0x4>,
<0x53500084 0x4>,
<0x53500088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53500000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
};
};
......
arch/arm/boot/dts/am4372.dtsi
View file @ 955d8f3e
......@@ -256,33 +256,92 @@ mmc3: mmc@0 {
};
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap5-sham";
reg = <0 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
};
aes: aes@53501000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53501000 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53501080 0x4>,
<0x53501084 0x4>,
<0x53501088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53501000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
des: des@53701000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x53701000 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
des_target: target-module@53701000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53701030 0x4>,
<0x53701034 0x4>,
<0x53701038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x53701000 0x1000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
};
};
gpmc: gpmc@50000000 {
......@@ -305,17 +364,34 @@ gpmc: gpmc@50000000 {
status = "disabled";
};
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
target-module@47900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x47900000 0x4>,
<0x47900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
interrupts = <0 138 0x4>;
num-cs = <4>;
status = "disabled";
#size-cells = <1>;
ranges = <0x0 0x47900000 0x1000>,
<0x30000000 0x30000000 0x4000000>;
qspi: spi@0 {
compatible = "ti,am4372-qspi";
reg = <0 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
clocks = <&dpll_per_m2_div4_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 138 0x4>;
num-cs = <4>;
};
};
dss: dss@4832a000 {
......
arch/arm/boot/dts/am437x-gp-evm.dts
View file @ 955d8f3e
......@@ -86,7 +86,7 @@ &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
};
lcd0: display {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
label = "lcd";
backlight = <&lcd_bl>;
......
arch/arm/boot/dts/am437x-l4.dtsi
View file @ 955d8f3e
......@@ -225,7 +225,6 @@ i2c0: i2c@0 {
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
......@@ -763,7 +762,6 @@ i2c1: i2c@0 {
target-module@30000 { /* 0x48030000, ap 65 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
......@@ -900,7 +898,6 @@ timer2: timer@0 {
target-module@42000 { /* 0x48042000, ap 20 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
......@@ -927,7 +924,6 @@ timer3: timer@0 {
target-module@44000 { /* 0x48044000, ap 22 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
......@@ -955,7 +951,6 @@ timer4: timer@0 {
target-module@46000 { /* 0x48046000, ap 24 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
......@@ -983,7 +978,6 @@ timer5: timer@0 {
target-module@48000 { /* 0x48048000, ap 26 1a.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
......@@ -1011,7 +1005,6 @@ timer6: timer@0 {
target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
......@@ -1107,7 +1100,6 @@ mmc1: mmc@0 {
target-module@80000 { /* 0x48080000, ap 32 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
......@@ -1169,7 +1161,6 @@ mbox_wkupm3: wkup_m3 {
target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
......@@ -1282,7 +1273,6 @@ i2c2: i2c@0 {
target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
......@@ -1313,7 +1303,6 @@ spi1: spi@0 {
target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi2";
reg = <0xa2000 0x4>,
<0xa2110 0x4>,
<0xa2114 0x4>;
......@@ -1344,7 +1333,6 @@ spi2: spi@0 {
target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi3";
reg = <0xa4000 0x4>,
<0xa4110 0x4>,
<0xa4114 0x4>;
......@@ -1527,7 +1515,6 @@ gpio3: gpio@0 {
target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0xc1000 0x4>,
<0xc1010 0x4>,
<0xc1014 0x4>;
......@@ -1556,7 +1543,6 @@ target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
......@@ -1577,7 +1563,6 @@ target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
......@@ -1695,7 +1680,6 @@ segment@300000 { /* 0x48300000 */
target-module@0 { /* 0x48300000, ap 56 40.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
......@@ -1748,7 +1732,6 @@ ehrpwm0: pwm@200 {
target-module@2000 { /* 0x48302000, ap 58 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
......@@ -1801,7 +1784,6 @@ ehrpwm1: pwm@200 {
target-module@4000 { /* 0x48304000, ap 60 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
......@@ -1854,7 +1836,6 @@ ehrpwm2: pwm@200 {
target-module@6000 { /* 0x48306000, ap 96 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss3";
reg = <0x6000 0x4>,
<0x6004 0x4>;
reg-names = "rev", "sysc";
......@@ -1896,7 +1877,6 @@ ehrpwm3: pwm@200 {
target-module@8000 { /* 0x48308000, ap 98 54.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss4";
reg = <0x8000 0x4>,
<0x8004 0x4>;
reg-names = "rev", "sysc";
......@@ -1938,7 +1918,6 @@ ehrpwm4: pwm@48308200 {
target-module@a000 { /* 0x4830a000, ap 100 60.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss5";
reg = <0xa000 0x4>,
<0xa004 0x4>;
reg-names = "rev", "sysc";
......@@ -2086,7 +2065,6 @@ gpio5: gpio@0 {
target-module@26000 { /* 0x48326000, ap 86 66.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe0";
reg = <0x26000 0x4>,
<0x26104 0x4>;
reg-names = "rev", "sysc";
......@@ -2113,7 +2091,6 @@ vpfe0: vpfe@0 {
target-module@28000 { /* 0x48328000, ap 75 0e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe1";
reg = <0x28000 0x4>,
<0x28104 0x4>;
reg-names = "rev", "sysc";
......@@ -2162,7 +2139,6 @@ target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3d000 0x4>,
<0x3d010 0x4>,
<0x3d014 0x4>;
......@@ -2189,7 +2165,6 @@ timer9: timer@0 {
target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x3f000 0x4>,
<0x3f010 0x4>,
<0x3f014 0x4>;
......@@ -2216,7 +2191,6 @@ timer10: timer@0 {
target-module@41000 { /* 0x48341000, ap 106 76.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x41000 0x4>,
<0x41010 0x4>,
<0x41014 0x4>;
......@@ -2243,7 +2217,6 @@ timer11: timer@0 {
target-module@45000 { /* 0x48345000, ap 108 6a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi4";
reg = <0x45000 0x4>,
<0x45110 0x4>,
<0x45114 0x4>;
......@@ -2358,7 +2331,6 @@ usb1: usb@10000 {
target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp0";
reg = <0xa8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
......@@ -2440,7 +2412,6 @@ usb2: usb@10000 {
target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp1";
reg = <0xe8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
......
arch/arm/boot/dts/am43x-epos-evm.dts
View file @ 955d8f3e
......@@ -42,7 +42,7 @@ vbat: fixedregulator0 {
};
lcd0: display {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
label = "lcd";
backlight = <&lcd_bl>;
......
arch/arm/boot/dts/dra7-evm-common.dtsi
View file @ 955d8f3e
......@@ -4,7 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/clock/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
/ {
......
arch/arm/boot/dts/dra7-l4.dtsi
View file @ 955d8f3e
......@@ -186,7 +186,6 @@ cm_core_clockdomains: clockdomains {
target-module@56000 { /* 0x4a056000, ap 9 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
......@@ -212,7 +211,7 @@ SYSC_OMAP2_SOFTRESET |
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
compatible = "ti,omap4430-sdma";
compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
......@@ -234,7 +233,6 @@ target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
target-module@80000 { /* 0x4a080000, ap 13 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "ocp2scp1";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
......@@ -302,7 +300,6 @@ usb3_phy1: phy@4400 {
target-module@90000 { /* 0x4a090000, ap 59 42.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "ocp2scp3";
reg = <0x90000 0x4>,
<0x90010 0x4>,
<0x90014 0x4>;
......@@ -394,7 +391,6 @@ target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0xd9038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
......@@ -414,7 +410,6 @@ target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0xdd038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
......@@ -471,7 +466,6 @@ mailbox1: mailbox@0 {
target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xf6000 0x4>,
<0xf6010 0x4>,
<0xf6014 0x4>;
......@@ -1233,7 +1227,6 @@ timer4: timer@0 {
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
......@@ -1748,7 +1741,6 @@ i2c2: i2c@0 {
target-module@78000 { /* 0x48078000, ap 39 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x78000 0x4>,
<0x78010 0x4>,
<0x78014 0x4>;
......@@ -1842,7 +1834,6 @@ i2c5: i2c@0 {
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>;
reg-names = "rev", "sysc";
......@@ -1870,7 +1861,6 @@ timer10: timer@0 {
target-module@88000 { /* 0x48088000, ap 43 66.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
......@@ -2044,6 +2034,37 @@ target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
<0x00001000 0x000a5000 0x00001000>;
};
des_target: target-module@a5000 { /* 0x480a5000 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0xa5030 0x4>,
<0xa5034 0x4>,
<0xa5038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa5000 0x00001000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
compatible = "ti,sysc";
status = "disabled";
......@@ -2490,7 +2511,6 @@ atl: atl@0 {
target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x3e000 0x4>,
<0x3e004 0x4>;
reg-names = "rev", "sysc";
......@@ -2537,7 +2557,6 @@ ehrpwm0: pwm@200 {
target-module@40000 { /* 0x48440000, ap 27 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x40000 0x4>,
<0x40004 0x4>;
reg-names = "rev", "sysc";
......@@ -2584,7 +2603,6 @@ ehrpwm1: pwm@200 {
target-module@42000 { /* 0x48442000, ap 29 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x42000 0x4>,
<0x42004 0x4>;
reg-names = "rev", "sysc";
......@@ -3326,7 +3344,6 @@ target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
target-module@20000 { /* 0x48820000, ap 5 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x20000 0x4>,
<0x20010 0x4>;
reg-names = "rev", "sysc";
......@@ -3354,7 +3371,6 @@ timer5: timer@0 {
target-module@22000 { /* 0x48822000, ap 7 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x22000 0x4>,
<0x22010 0x4>;
reg-names = "rev", "sysc";
......@@ -3382,7 +3398,6 @@ timer6: timer@0 {
target-module@24000 { /* 0x48824000, ap 9 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x24000 0x4>,
<0x24010 0x4>;
reg-names = "rev", "sysc";
......@@ -3410,7 +3425,6 @@ timer7: timer@0 {
target-module@26000 { /* 0x48826000, ap 11 0c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0x26000 0x4>,
<0x26010 0x4>;
reg-names = "rev", "sysc";
......@@ -3438,7 +3452,6 @@ timer8: timer@0 {
target-module@28000 { /* 0x48828000, ap 13 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer13";
reg = <0x28000 0x4>,
<0x28010 0x4>;
reg-names = "rev", "sysc";
......@@ -3466,7 +3479,6 @@ timer13: timer@0 {
target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer14";
reg = <0x2a000 0x4>,
<0x2a010 0x4>;
reg-names = "rev", "sysc";
......@@ -3494,7 +3506,6 @@ timer14: timer@0 {
target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer15";
reg = <0x2c000 0x4>,
<0x2c010 0x4>;
reg-names = "rev", "sysc";
......@@ -3522,7 +3533,6 @@ timer15: timer@0 {
target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer16";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
......@@ -4422,7 +4432,6 @@ segment@20000 { /* 0x4ae20000 */
target-module@0 { /* 0x4ae20000, ap 19 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer12";
reg = <0x0 0x4>,
<0x10 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/dra7.dtsi
View file @ 955d8f3e
......@@ -377,44 +377,120 @@ dmm@4e000000 {
ti,hwmods = "dmm";
};
mmu0_dsp1: mmu@40d01000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d01000 0x100>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
status = "disabled";
target-module@40d01000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x40d01000 0x4>,
<0x40d01010 0x4>,
<0x40d01014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp1 1>;
reset-names = "rstctrl";
ranges = <0x0 0x40d01000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu0_dsp1: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
};
};
mmu1_dsp1: mmu@40d02000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d02000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
status = "disabled";
target-module@40d02000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x40d02000 0x4>,
<0x40d02010 0x4>,
<0x40d02014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp1 1>;
reset-names = "rstctrl";
ranges = <0x0 0x40d02000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu1_dsp1: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
};
};
mmu_ipu1: mmu@58882000 {
compatible = "ti,dra7-iommu";
reg = <0x58882000 0x100>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu1";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
target-module@58882000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58882000 0x4>,
<0x58882010 0x4>,
<0x58882014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_ipu 2>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x58882000 0x100>;
mmu_ipu1: mmu@0 {
compatible = "ti,dra7-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
mmu_ipu2: mmu@55082000 {
compatible = "ti,dra7-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu2";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
<0x55082010 0x4>,
<0x55082014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x55082000 0x100>;
mmu_ipu2: mmu@0 {
compatible = "ti,dra7-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
abb_mpu: regulator-abb-mpu {
......@@ -652,48 +728,96 @@ hdmi: encoder@58060000 {
};
};
aes1: aes@4b500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes1";
reg = <0x4b500000 0xa0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
aes2: aes@4b700000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes2";
reg = <0x4b700000 0xa0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
aes1_target: target-module@4b500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b500080 0x4>,
<0x4b500084 0x4>,
<0x4b500088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b500000 0x1000>;
aes1: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x480a5000 0xa0>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
aes2_target: target-module@4b700000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b700080 0x4>,
<0x4b700084 0x4>,
<0x4b700088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b700000 0x1000>;
aes2: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x4b101000 0x300>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 119 0>;
dma-names = "rx";
clocks = <&l3_iclk_div>;
sham_target: target-module@4b101000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x4b101100 0x4>,
<0x4b101110 0x4>,
<0x4b101114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b101000 0x1000>;
sham: sham@0 {
compatible = "ti,omap5-sham";
reg = <0 0x300>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 119 0>;
dma-names = "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
opp_supply_mpu: opp-supply@4a003b20 {
......
arch/arm/boot/dts/dra72-evm-common.dtsi
View file @ 955d8f3e
......@@ -6,7 +6,7 @@
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/clock/ti-dra7-atl.h>
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
......
arch/arm/boot/dts/dra74x.dtsi
View file @ 955d8f3e
......@@ -66,24 +66,63 @@ usb4: usb@48950000 {
};
};
mmu0_dsp2: mmu@41501000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41501000 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
status = "disabled";
target-module@41501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x41501000 0x4>,
<0x41501010 0x4>,
<0x41501014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp2 1>;
reset-names = "rstctrl";
ranges = <0x0 0x41501000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu0_dsp2: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
};
};
mmu1_dsp2: mmu@41502000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41502000 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
status = "disabled";
target-module@41502000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x41502000 0x4>,
<0x41502010 0x4>,
<0x41502014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp2 1>;
reset-names = "rstctrl";
ranges = <0x0 0x41502000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu1_dsp2: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
};
};
};
};
......
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file @ 955d8f3e
......@@ -1734,6 +1734,20 @@ dss_clkctrl: dss-clkctrl@20 {
};
};
gpu_cm: gpu-cm@1200 {
compatible = "ti,omap4-cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1200 0x100>;
gpu_clkctrl: gpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l3init_cm: l3init-cm@1300 {
compatible = "ti,omap4-cm";
reg = <0x1300 0x100>;
......
arch/arm/boot/dts/motorola-mapphone-common.dtsi
View file @ 955d8f3e
......@@ -650,6 +650,11 @@ OMAP4_IOPAD(0x040, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
};
};
/* RNG is used by secure mode and not accessible */
&rng_target {
status = "disabled";
};
/* Configure pwm clock source for timers 8 & 9 */
&timer8 {
assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
......
arch/arm/boot/dts/omap2.dtsi
View file @ 955d8f3e
......@@ -8,6 +8,7 @@
* kind, whether express or implied.
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/omap.h>
......@@ -79,17 +80,37 @@ intc: interrupt-controller@1 {
reg = <0x480FE000 0x1000>;
};
sdma: dma-controller@48056000 {
compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
ti,hwmods = "dma";
reg = <0x48056000 0x1000>;
interrupts = <12>,
<13>,
<14>,
<15>;
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <64>;
target-module@48056000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x48056000 0x4>,
<0x4805602c 0x4>,
<0x48056028 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&core_l3_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48056000 0x1000>;
sdma: dma-controller@0 {
compatible = "ti,omap2420-sdma", "ti,omap-sdma";
reg = <0 0x1000>;
interrupts = <12>,
<13>,
<14>,
<15>;
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <64>;
};
};
i2c1: i2c@48070000 {
......
arch/arm/boot/dts/omap2430.dtsi
View file @ 955d8f3e
......@@ -309,6 +309,10 @@ wd_timer2: wdt@49016000 {
};
};
&sdma {
compatible = "ti,omap2430-sdma", "ti,omap-sdma";
};
&i2c1 {
compatible = "ti,omap2430-i2c";
};
......
arch/arm/boot/dts/omap3-n900.dts
View file @ 955d8f3e
......@@ -482,6 +482,11 @@ &vintdig {
regulator-always-on;
};
/* First two dma channels are reserved on secure omap3 */
&sdma {
dma-channel-mask = <0xfffffffc>;
};
&twl {
twl_audio: audio {
compatible = "ti,twl4030-audio";
......
arch/arm/boot/dts/omap3.dtsi
View file @ 955d8f3e
......@@ -206,17 +206,41 @@ intc: interrupt-controller@48200000 {
reg = <0x48200000 0x1000>;
};
sdma: dma-controller@48056000 {
compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
reg = <0x48056000 0x1000>;
interrupts = <12>,
<13>,
<14>,
<15>;
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <96>;
ti,hwmods = "dma";
target-module@48056000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x48056000 0x4>,
<0x4805602c 0x4>,
<0x48056028 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
clocks = <&core_l3_ick>;
clock-names = "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48056000 0x1000>;
sdma: dma-controller@0 {
compatible = "ti,omap3430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <12>,
<13>,
<14>,
<15>;
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <96>;
};
};
gpio1: gpio@48310000 {
......
arch/arm/boot/dts/omap36xx.dtsi
View file @ 955d8f3e
......@@ -223,6 +223,10 @@ thermal_zones: thermal-zones {
};
};
&sdma {
compatible = "ti,omap3630-sdma", "ti,omap-sdma";
};
/* OMAP3630 needs dss_96m_fck for VENC */
&venc {
clocks = <&dss_tv_fck>, <&dss_96m_fck>;
......
arch/arm/boot/dts/omap4-l4-abe.dtsi
View file @ 955d8f3e
......@@ -219,7 +219,6 @@ target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "dmic";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
......@@ -279,7 +278,6 @@ wdt3: wdt@0 {
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcpdm";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
......@@ -314,7 +312,6 @@ mcpdm: mcpdm@0 {
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
......@@ -345,7 +342,6 @@ timer5: timer@0 {
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
......@@ -376,7 +372,6 @@ timer6: timer@0 {
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
......@@ -407,7 +402,6 @@ timer7: timer@0 {
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
......@@ -466,7 +460,6 @@ target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "aess";
reg = <0xf1000 0x4>,
<0xf1010 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/omap4-l4.dtsi
View file @ 955d8f3e
......@@ -136,7 +136,6 @@ cm2_clockdomains: clockdomains {
target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
......@@ -160,7 +159,7 @@ SYSC_OMAP2_SOFTRESET |
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
compatible = "ti,omap4430-sdma";
compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
......@@ -174,7 +173,6 @@ sdma: dma-controller@0 {
target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "hsi";
reg = <0x58000 0x4>,
<0x58010 0x4>,
<0x58014 0x4>;
......@@ -321,7 +319,6 @@ usbhsehci: ehci@c00 {
target-module@66000 { /* 0x4a066000, ap 25 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
......@@ -335,12 +332,18 @@ SYSC_OMAP2_SOFTRESET |
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_tesla 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
/* mmu_dsp cannot be moved before reset driver */
status = "disabled";
mmu_dsp: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
};
};
};
......@@ -420,7 +423,6 @@ usb_otg_hs: usb_otg_hs@0 {
target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "ocp2scp_usb_phy";
reg = <0x2d000 0x4>,
<0x2d010 0x4>,
<0x2d014 0x4>;
......@@ -499,7 +501,6 @@ target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0x59038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
......@@ -523,7 +524,6 @@ smartreflex_mpu: smartreflex@0 {
target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_iva";
reg = <0x5b038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
......@@ -547,7 +547,6 @@ smartreflex_iva: smartreflex@0 {
target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0x5d038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
......@@ -613,7 +612,6 @@ mbox_dsp: mbox_dsp {
target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0x76000 0x4>,
<0x76010 0x4>,
<0x76014 0x4>;
......@@ -721,7 +719,6 @@ target-module@8000 { /* 0x4a108000, ap 63 62.0 */
target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "fdif";
reg = <0xa000 0x4>,
<0xa010 0x4>;
reg-names = "rev", "sysc";
......@@ -1177,7 +1174,6 @@ timer1: timer@0 {
target-module@c000 { /* 0x4a31c000, ap 11 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "kbd";
reg = <0xc000 0x4>,
<0xc010 0x4>,
<0xc014 0x4>;
......@@ -1422,7 +1418,6 @@ uart3: serial@0 {
target-module@32000 { /* 0x48032000, ap 5 02.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>,
<0x32014 0x4>;
......@@ -1454,7 +1449,6 @@ timer2: timer@0 {
target-module@34000 { /* 0x48034000, ap 7 04.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
......@@ -1482,7 +1476,6 @@ timer3: timer@0 {
target-module@36000 { /* 0x48036000, ap 9 0e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
......@@ -1510,7 +1503,6 @@ timer4: timer@0 {
target-module@3e000 { /* 0x4803e000, ap 11 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
......@@ -1892,7 +1884,6 @@ i2c2: i2c@0 {
target-module@76000 { /* 0x48076000, ap 39 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "slimbus2";
reg = <0x76000 0x4>,
<0x76010 0x4>;
reg-names = "rev", "sysc";
......@@ -1913,7 +1904,6 @@ target-module@76000 { /* 0x48076000, ap 39 38.0 */
target-module@78000 { /* 0x48078000, ap 41 1a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x78000 0x4>,
<0x78010 0x4>,
<0x78014 0x4>;
......@@ -1942,7 +1932,6 @@ elm: elm@0 {
target-module@86000 { /* 0x48086000, ap 43 24.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>,
<0x86014 0x4>;
......@@ -1975,7 +1964,6 @@ timer10: timer@0 {
target-module@88000 { /* 0x48088000, ap 45 2e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
......@@ -2002,12 +1990,26 @@ timer11: timer@0 {
};
};
target-module@90000 { /* 0x48090000, ap 57 2a.0 */
compatible = "ti,sysc";
status = "disabled";
rng_target: target-module@90000 { /* 0x48090000, ap 57 2a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x91fe0 0x4>,
<0x91fe4 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_RNG_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x90000 0x2000>;
rng: rng@0 {
compatible = "ti,omap4-rng";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@96000 { /* 0x48096000, ap 37 26.0 */
......@@ -2171,6 +2173,35 @@ target-module@a4000 { /* 0x480a4000, ap 59 34.0 */
<0x00001000 0x000a5000 0x00001000>;
};
des_target: target-module@a5000 { /* 0x480a5000 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0xa5030 0x4>,
<0xa5034 0x4>,
<0xa5038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_DES3DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa5000 0x00001000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 117>, <&sdma 116>;
dma-names = "tx", "rx";
};
};
target-module@a8000 { /* 0x480a8000, ap 61 3e.0 */
compatible = "ti,sysc";
status = "disabled";
......
arch/arm/boot/dts/omap4.dtsi
View file @ 955d8f3e
......@@ -173,14 +173,6 @@ gpmc: gpmc@50000000 {
#gpio-cells = <2>;
};
mmu_dsp: mmu@4a066000 {
compatible = "ti,omap4-iommu";
reg = <0x4a066000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_dsp";
#iommu-cells = <0>;
};
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
......@@ -206,17 +198,37 @@ target-module@52000000 {
/* No child device binding, driver in staging */
};
mmu_ipu: mmu@55082000 {
compatible = "ti,omap4-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
<0x55082010 0x4>,
<0x55082014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
ranges = <0x0 0x55082000 0x100>;
#size-cells = <1>;
#address-cells = <1>;
mmu_ipu: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
target-module@4012c000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "slimbus1";
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
reg-names = "rev", "sysc";
......@@ -266,40 +278,90 @@ emif2: emif@4d000000 {
hw-caps-temp-alert;
};
aes1: aes@4b501000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes1";
reg = <0x4b501000 0xa0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 111>, <&sdma 110>;
dma-names = "tx", "rx";
};
aes2: aes@4b701000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes2";
reg = <0x4b701000 0xa0>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 114>, <&sdma 113>;
dma-names = "tx", "rx";
aes1_target: target-module@4b501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b501080 0x4>,
<0x4b501084 0x4>,
<0x4b501088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b501000 0x1000>;
aes1: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 111>, <&sdma 110>;
dma-names = "tx", "rx";
};
};
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x480a5000 0xa0>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 117>, <&sdma 116>;
dma-names = "tx", "rx";
aes2_target: target-module@4b701000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b701080 0x4>,
<0x4b701084 0x4>,
<0x4b701088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b701000 0x1000>;
aes2: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 114>, <&sdma 113>;
dma-names = "tx", "rx";
};
};
sham: sham@4b100000 {
compatible = "ti,omap4-sham";
ti,hwmods = "sham";
reg = <0x4b100000 0x300>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 119>;
dma-names = "rx";
sham_target: target-module@4b100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x4b100100 0x4>,
<0x4b100110 0x4>,
<0x4b100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x300>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 119>;
dma-names = "rx";
};
};
abb_mpu: regulator-abb-mpu {
......
arch/arm/boot/dts/omap44xx-clocks.dtsi
View file @ 955d8f3e
......@@ -1279,13 +1279,18 @@ l4_per_cm: l4_per_cm@1400 {
#size-cells = <1>;
ranges = <0 0x1400 0x200>;
l4_per_clkctrl: clk@20 {
compatible = "ti,clkctrl";
l4_per_clkctrl: clock@20 {
compatible = "ti,clkctrl-l4-per", "ti,clkctrl";
reg = <0x20 0x144>;
#clock-cells = <2>;
};
};
l4_secure_clkctrl: clock@1a0 {
compatible = "ti,clkctrl-l4-secure", "ti,clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
};
};
&prm {
......
arch/arm/boot/dts/omap5-l4-abe.dtsi
View file @ 955d8f3e
......@@ -203,7 +203,6 @@ target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "dmic";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
......@@ -244,7 +243,6 @@ target-module@30000 { /* 0x40130000, ap 14 0e.0 */
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "mcpdm";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
......@@ -279,7 +277,6 @@ mcpdm: mcpdm@0 {
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
......@@ -311,7 +308,6 @@ timer5: timer@0 {
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
......@@ -343,7 +339,6 @@ timer6: timer@0 {
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
......@@ -374,7 +369,6 @@ timer7: timer@0 {
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/omap5-l4.dtsi
View file @ 955d8f3e
......@@ -213,7 +213,6 @@ dwc3: dwc3@10000 {
target-module@56000 { /* 0x4a056000, ap 7 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
......@@ -237,7 +236,7 @@ SYSC_OMAP2_SOFTRESET |
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
compatible = "ti,omap4430-sdma";
compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
......@@ -349,7 +348,6 @@ usbhsehci: ehci@c00 {
target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmu_dsp";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
......@@ -364,12 +362,18 @@ SYSC_OMAP2_SOFTRESET |
/* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
/* mmu_dsp cannot be moved before reset driver */
status = "disabled";
mmu_dsp: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
};
};
target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
......@@ -430,7 +434,6 @@ segment@80000 { /* 0x4a080000 */
target-module@0 { /* 0x4a080000, ap 83 28.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "ocp2scp1";
reg = <0x0 0x4>,
<0x10 0x4>,
<0x14 0x4>;
......@@ -488,7 +491,6 @@ usb3_phy: usb3phy@4400 {
target-module@10000 { /* 0x4a090000, ap 89 36.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "ocp2scp3";
reg = <0x10000 0x4>,
<0x10010 0x4>,
<0x10014 0x4>;
......@@ -627,7 +629,6 @@ mbox_dsp: mbox_dsp {
target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0x76000 0x4>,
<0x76010 0x4>,
<0x76014 0x4>;
......@@ -1061,7 +1062,6 @@ uart3: serial@0 {
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
......@@ -1089,7 +1089,6 @@ timer2: timer@0 {
target-module@34000 { /* 0x48034000, ap 7 46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
......@@ -1117,7 +1116,6 @@ timer3: timer@0 {
target-module@36000 { /* 0x48036000, ap 9 4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
......@@ -1145,7 +1143,6 @@ timer4: timer@0 {
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
......@@ -1713,7 +1710,6 @@ i2c5: i2c@0 {
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>;
reg-names = "rev", "sysc";
......@@ -1742,7 +1738,6 @@ timer10: timer@0 {
target-module@88000 { /* 0x48088000, ap 43 66.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
......@@ -1769,12 +1764,26 @@ timer11: timer@0 {
};
};
target-module@90000 { /* 0x48090000, ap 55 1a.0 */
compatible = "ti,sysc";
status = "disabled";
rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x91fe0 0x4>,
<0x91fe4 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x90000 0x2000>;
rng: rng@0 {
compatible = "ti,omap4-rng";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@98000 { /* 0x48098000, ap 47 08.0 */
......@@ -2358,7 +2367,6 @@ timer1: timer@0 {
target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "kbd";
reg = <0xc000 0x4>,
<0xc010 0x4>;
reg-names = "rev", "sysc";
......
arch/arm/boot/dts/omap5.dtsi
View file @ 955d8f3e
......@@ -186,21 +186,33 @@ gpmc: gpmc@50000000 {
#gpio-cells = <2>;
};
mmu_dsp: mmu@4a066000 {
compatible = "ti,omap4-iommu";
reg = <0x4a066000 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_dsp";
#iommu-cells = <0>;
};
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
<0x55082010 0x4>,
<0x55082014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
ranges = <0x0 0x55082000 0x100>;
#size-cells = <1>;
#address-cells = <1>;
mmu_ipu: mmu@55082000 {
compatible = "ti,omap4-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
mmu_ipu: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
dmm@4e000000 {
......
arch/arm/boot/dts/omap54xx-clocks.dtsi
View file @ 955d8f3e
......@@ -1125,11 +1125,17 @@ l4per_cm: l4per_cm@1000 {
#size-cells = <1>;
ranges = <0 0x1000 0x200>;
l4per_clkctrl: clk@20 {
compatible = "ti,clkctrl";
l4per_clkctrl: clock@20 {
compatible = "ti,clkctrl-l4per", "ti,clkctrl";
reg = <0x20 0x15c>;
#clock-cells = <2>;
};
l4sec_clkctrl: clock@1a0 {
compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
reg = <0x1a0 0x3c>;
#clock-cells = <2>;
};
};
dss_cm: dss_cm@1400 {
......
arch/arm/configs/omap2plus_defconfig
View file @ 955d8f3e
......@@ -92,6 +92,7 @@ CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NETFILTER=y
CONFIG_PHONET=m
CONFIG_NET_SWITCHDEV=y
CONFIG_CAN=m
CONFIG_CAN_C_CAN=m
CONFIG_CAN_C_CAN_PLATFORM=m
......@@ -181,6 +182,7 @@ CONFIG_SMSC911X=y
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_TI_DAVINCI_EMAC=y
CONFIG_TI_CPSW=y
CONFIG_TI_CPSW_SWITCHDEV=y
CONFIG_TI_CPTS=y
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
......@@ -554,6 +556,6 @@ CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_SPLIT=y
CONFIG_DEBUG_INFO_DWARF4=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_SCHEDSTATS=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_TI_CPSW_SWITCHDEV=y
arch/arm/mach-omap2/common.h
View file @ 955d8f3e
......@@ -345,9 +345,12 @@ static inline int dra7xx_pciess_reset(struct omap_hwmod *oh)
}
#endif
struct omap_system_dma_plat_info;
void pdata_quirks_init(const struct of_device_id *);
void omap_auxdata_legacy_init(struct device *dev);
void omap_pcs_legacy_init(int irq, void (*rearm)(void));
extern struct omap_system_dma_plat_info dma_plat_info;
struct omap_sdrc_params;
extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
......
arch/arm/mach-omap2/dma.c
View file @ 955d8f3e
......@@ -30,10 +30,6 @@
#include <linux/omap-dma.h>
#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"
static enum omap_reg_offsets dma_common_ch_end;
static const struct omap_dma_reg reg_map[] = {
[REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
......@@ -81,42 +77,6 @@ static const struct omap_dma_reg reg_map[] = {
[CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
};
static void __iomem *dma_base;
static inline void dma_write(u32 val, int reg, int lch)
{
void __iomem *addr = dma_base;
addr += reg_map[reg].offset;
addr += reg_map[reg].stride * lch;
writel_relaxed(val, addr);
}
static inline u32 dma_read(int reg, int lch)
{
void __iomem *addr = dma_base;
addr += reg_map[reg].offset;
addr += reg_map[reg].stride * lch;
return readl_relaxed(addr);
}
static void omap2_clear_dma(int lch)
{
int i;
for (i = CSDP; i <= dma_common_ch_end; i += 1)
dma_write(0, i, lch);
}
static void omap2_show_dma_caps(void)
{
u8 revision = dma_read(REVISION, 0) & 0xff;
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
revision >> 4, revision & 0xf);
}
static unsigned configure_dma_errata(void)
{
unsigned errata = 0;
......@@ -211,82 +171,35 @@ static const struct dma_slave_map omap24xx_sdma_dt_map[] = {
{ "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
};
static struct omap_system_dma_plat_info dma_plat_info __initdata = {
.reg_map = reg_map,
.channel_stride = 0x60,
.show_dma_caps = omap2_show_dma_caps,
.clear_dma = omap2_clear_dma,
.dma_write = dma_write,
.dma_read = dma_read,
static struct omap_dma_dev_attr dma_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32,
.lch_count = 32,
};
static struct platform_device_info omap_dma_dev_info __initdata = {
.name = "omap-dma-engine",
.id = -1,
.dma_mask = DMA_BIT_MASK(32),
struct omap_system_dma_plat_info dma_plat_info = {
.reg_map = reg_map,
.channel_stride = 0x60,
.dma_attr = &dma_attr,
};
/* One time initializations */
static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
static int __init omap2_system_dma_init(void)
{
struct platform_device *pdev;
struct omap_system_dma_plat_info p;
struct omap_dma_dev_attr *d;
struct resource *mem;
char *name = "omap_dma_system";
p = dma_plat_info;
p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
p.errata = configure_dma_errata();
dma_plat_info.errata = configure_dma_errata();
if (soc_is_omap24xx()) {
/* DMA slave map for drivers not yet converted to DT */
p.slave_map = omap24xx_sdma_dt_map;
p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
dma_plat_info.slave_map = omap24xx_sdma_dt_map;
dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
}
pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
if (IS_ERR(pdev)) {
pr_err("%s: Can't build omap_device for %s:%s.\n",
__func__, name, oh->name);
return PTR_ERR(pdev);
}
omap_dma_dev_info.res = pdev->resource;
omap_dma_dev_info.num_res = pdev->num_resources;
if (!soc_is_omap242x())
dma_attr.dev_caps |= IS_RW_PRIORITY;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem) {
dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
return -EINVAL;
}
dma_base = ioremap(mem->start, resource_size(mem));
if (!dma_base) {
dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
return -ENOMEM;
}
d = oh->dev_attr;
if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
d->dev_caps |= HS_CHANNELS_RESERVED;
if (platform_get_irq_byname(pdev, "0") < 0)
d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
/* Check the capabilities register for descriptor loading feature */
if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
dma_common_ch_end = CCDN;
else
dma_common_ch_end = CCFN;
if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
return 0;
}
static int __init omap2_system_dma_init(void)
{
return omap_hwmod_for_each_by_class("dma",
omap2_system_dma_init_dev, NULL);
}
omap_arch_initcall(omap2_system_dma_init);
arch/arm/mach-omap2/omap_device.c
View file @ 955d8f3e
......@@ -373,176 +373,6 @@ void omap_device_delete(struct omap_device *od)
kfree(od);
}
/**
* omap_device_copy_resources - Add legacy IO and IRQ resources
* @oh: interconnect target module
* @pdev: platform device to copy resources to
*
* We still have legacy DMA and smartreflex needing resources.
* Let's populate what they need until we can eventually just
* remove this function. Note that there should be no need to
* call this from omap_device_build_from_dt(), nor should there
* be any need to call it for other devices.
*/
static int
omap_device_copy_resources(struct omap_hwmod *oh,
struct platform_device *pdev)
{
struct device_node *np, *child;
struct property *prop;
struct resource *res;
const char *name;
int error, irq = 0;
if (!oh || !oh->od || !oh->od->pdev)
return -EINVAL;
np = oh->od->pdev->dev.of_node;
if (!np) {
error = -ENODEV;
goto error;
}
res = kcalloc(2, sizeof(*res), GFP_KERNEL);
if (!res)
return -ENOMEM;
/* Do we have a dts range for the interconnect target module? */
error = omap_hwmod_parse_module_range(oh, np, res);
/* No ranges, rely on device reg entry */
if (error)
error = of_address_to_resource(np, 0, res);
if (error)
goto free;
/* SmartReflex needs first IO resource name to be "mpu" */
res[0].name = "mpu";
/*
* We may have a configured "ti,sysc" interconnect target with a
* dts child with the interrupt. If so use the first child's
* first interrupt for "ti-hwmods" legacy support.
*/
of_property_for_each_string(np, "compatible", prop, name)
if (!strncmp("ti,sysc-", name, 8))
break;
child = of_get_next_available_child(np, NULL);
if (name)
irq = irq_of_parse_and_map(child, 0);
if (!irq)
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
error = -EINVAL;
goto free;
}
/* Legacy DMA code needs interrupt name to be "0" */
res[1].start = irq;
res[1].end = irq;
res[1].flags = IORESOURCE_IRQ;
res[1].name = "0";
error = platform_device_add_resources(pdev, res, 2);
free:
kfree(res);
error:
WARN(error, "%s: %s device %s failed: %i\n",
__func__, oh->name, dev_name(&pdev->dev),
error);
return error;
}
/**
* omap_device_build - build and register an omap_device with one omap_hwmod
* @pdev_name: name of the platform_device driver to use
* @pdev_id: this platform_device's connection ID
* @oh: ptr to the single omap_hwmod that backs this omap_device
* @pdata: platform_data ptr to associate with the platform_device
* @pdata_len: amount of memory pointed to by @pdata
*
* Convenience function for building and registering a single
* omap_device record, which in turn builds and registers a
* platform_device record. See omap_device_build_ss() for more
* information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
* passes along the return value of omap_device_build_ss().
*/
struct platform_device __init *omap_device_build(const char *pdev_name,
int pdev_id,
struct omap_hwmod *oh,
void *pdata, int pdata_len)
{
int ret = -ENOMEM;
struct platform_device *pdev;
struct omap_device *od;
if (!oh || !pdev_name)
return ERR_PTR(-EINVAL);
if (!pdata && pdata_len > 0)
return ERR_PTR(-EINVAL);
if (strncmp(oh->name, "smartreflex", 11) &&
strncmp(oh->name, "dma", 3)) {
pr_warn("%s need to update %s to probe with dt\na",
__func__, pdev_name);
ret = -ENODEV;
goto odbs_exit;
}
pdev = platform_device_alloc(pdev_name, pdev_id);
if (!pdev) {
ret = -ENOMEM;
goto odbs_exit;
}
/* Set the dev_name early to allow dev_xxx in omap_device_alloc */
if (pdev->id != -1)
dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
else
dev_set_name(&pdev->dev, "%s", pdev->name);
/*
* Must be called before omap_device_alloc() as oh->od
* only contains the currently registered omap_device
* and will get overwritten by omap_device_alloc().
*/
ret = omap_device_copy_resources(oh, pdev);
if (ret)
goto odbs_exit1;
od = omap_device_alloc(pdev, &oh, 1);
if (IS_ERR(od)) {
ret = PTR_ERR(od);
goto odbs_exit1;
}
ret = platform_device_add_data(pdev, pdata, pdata_len);
if (ret)
goto odbs_exit2;
ret = omap_device_register(pdev);
if (ret)
goto odbs_exit2;
return pdev;
odbs_exit2:
omap_device_delete(od);
odbs_exit1:
platform_device_put(pdev);
odbs_exit:
pr_err("omap_device: %s: build failed (%d)\n", pdev_name, ret);
return ERR_PTR(ret);
}
#ifdef CONFIG_PM
static int _od_runtime_suspend(struct device *dev)
{
......
arch/arm/mach-omap2/omap_device.h
View file @ 955d8f3e
......@@ -68,10 +68,6 @@ int omap_device_idle(struct platform_device *pdev);
/* Core code interface */
struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
struct omap_hwmod *oh, void *pdata,
int pdata_len);
struct omap_device *omap_device_alloc(struct platform_device *pdev,
struct omap_hwmod **ohs, int oh_cnt);
void omap_device_delete(struct omap_device *od);
......
arch/arm/mach-omap2/omap_hwmod.c
View file @ 955d8f3e
......@@ -1852,23 +1852,6 @@ static int _omap4_get_context_lost(struct omap_hwmod *oh)
return oh->prcm.omap4.context_lost_counter;
}
/**
* _enable_preprogram - Pre-program an IP block during the _enable() process
* @oh: struct omap_hwmod *
*
* Some IP blocks (such as AESS) require some additional programming
* after enable before they can enter idle. If a function pointer to
* do so is present in the hwmod data, then call it and pass along the
* return value; otherwise, return 0.
*/
static int _enable_preprogram(struct omap_hwmod *oh)
{
if (!oh->class->enable_preprogram)
return 0;
return oh->class->enable_preprogram(oh);
}
/**
* _enable - enable an omap_hwmod
* @oh: struct omap_hwmod *
......@@ -1952,7 +1935,6 @@ static int _enable(struct omap_hwmod *oh)
_update_sysc_cache(oh);
_enable_sysc(oh);
}
r = _enable_preprogram(oh);
} else {
if (soc_ops.disable_module)
soc_ops.disable_module(oh);
......
arch/arm/mach-omap2/omap_hwmod.h
View file @ 955d8f3e
......@@ -501,7 +501,6 @@ struct omap_hwmod_omap4_prcm {
* @sysc: device SYSCONFIG/SYSSTATUS register data
* @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
* @reset: ptr to fn to be executed in place of the standard hwmod reset fn
* @enable_preprogram: ptr to fn to be executed during device enable
* @lock: ptr to fn to be executed to lock IP registers
* @unlock: ptr to fn to be executed to unlock IP registers
*
......@@ -526,7 +525,6 @@ struct omap_hwmod_class {
struct omap_hwmod_class_sysconfig *sysc;
int (*pre_shutdown)(struct omap_hwmod *oh);
int (*reset)(struct omap_hwmod *oh);
int (*enable_preprogram)(struct omap_hwmod *oh);
void (*lock)(struct omap_hwmod *oh);
void (*unlock)(struct omap_hwmod *oh);
};
......@@ -662,7 +660,6 @@ const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
*
*/
extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
void omap_hwmod_rtc_unlock(struct omap_hwmod *oh);
void omap_hwmod_rtc_lock(struct omap_hwmod *oh);
......
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View file @ 955d8f3e
......@@ -11,7 +11,6 @@
*/
#include <linux/platform_data/i2c-omap.h>
#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
......@@ -126,21 +125,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
.flags = HWMOD_16BIT_REG,
};
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32,
.lch_count = 32,
};
static struct omap_hwmod omap2420_dma_system_hwmod = {
.name = "dma",
.class = &omap2xxx_dma_hwmod_class,
.main_clk = "core_l3_ck",
.dev_attr = &dma_dev_attr,
.flags = HWMOD_NO_IDLEST,
};
/* mailbox */
static struct omap_hwmod omap2420_mailbox_hwmod = {
.name = "mailbox",
......@@ -328,22 +312,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
.master = &omap2420_dma_system_hwmod,
.slave = &omap2xxx_l3_main_hwmod,
.clk = "core_l3_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
.master = &omap2xxx_l4_core_hwmod,
.slave = &omap2420_dma_system_hwmod,
.clk = "sdma_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
.master = &omap2xxx_l4_core_hwmod,
......@@ -435,8 +403,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
&omap2420_l4_wkup__gpio2,
&omap2420_l4_wkup__gpio3,
&omap2420_l4_wkup__gpio4,
&omap2420_dma_system__l3,
&omap2420_l4_core__dma_system,
&omap2420_l4_core__mailbox,
&omap2420_l4_core__mcbsp1,
&omap2420_l4_core__mcbsp2,
......
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View file @ 955d8f3e
......@@ -12,7 +12,6 @@
#include <linux/platform_data/i2c-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
......@@ -121,21 +120,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.class = &omap2xxx_gpio_hwmod_class,
};
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
.lch_count = 32,
};
static struct omap_hwmod omap2430_dma_system_hwmod = {
.name = "dma",
.class = &omap2xxx_dma_hwmod_class,
.main_clk = "core_l3_ck",
.dev_attr = &dma_dev_attr,
.flags = HWMOD_NO_IDLEST,
};
/* mailbox */
static struct omap_hwmod omap2430_mailbox_hwmod = {
.name = "mailbox",
......@@ -508,22 +492,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
.master = &omap2430_dma_system_hwmod,
.slave = &omap2xxx_l3_main_hwmod,
.clk = "core_l3_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
.master = &omap2xxx_l4_core_hwmod,
.slave = &omap2430_dma_system_hwmod,
.clk = "sdma_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
.master = &omap2xxx_l4_core_hwmod,
......@@ -635,8 +603,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
&omap2430_l4_wkup__gpio3,
&omap2430_l4_wkup__gpio4,
&omap2430_l4_core__gpio5,
&omap2430_dma_system__l3,
&omap2430_l4_core__dma_system,
&omap2430_l4_core__mailbox,
&omap2430_l4_core__mcbsp1,
&omap2430_l4_core__mcbsp2,
......
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View file @ 955d8f3e
......@@ -7,7 +7,6 @@
*/
#include <linux/types.h>
#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
......@@ -95,23 +94,6 @@ struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
.sysc = &omap2xxx_gpio_sysc,
};
/* system dma */
static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2xxx_dma_sysc,
};
/*
* 'mailbox' class
* mailbox module allowing communication between the on-chip processors
......
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
View file @ 955d8f3e
......@@ -28,29 +28,13 @@ extern struct omap_hwmod_ocp_if am33xx_pruss__l3_main;
extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main;
extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx;
extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc;
extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan0;
extern struct omap_hwmod_ocp_if am33xx_l4_per__dcan1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__elm;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2;
extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer3;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer4;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer5;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer6;
extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer7;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tpcc;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc0;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc1;
extern struct omap_hwmod_ocp_if am33xx_l3_main__tptc2;
extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc;
extern struct omap_hwmod_ocp_if am33xx_l3_main__sha0;
extern struct omap_hwmod_ocp_if am33xx_l3_main__aes0;
extern struct omap_hwmod am33xx_l3_main_hwmod;
extern struct omap_hwmod am33xx_l3_s_hwmod;
......@@ -61,29 +45,13 @@ extern struct omap_hwmod am33xx_mpu_hwmod;
extern struct omap_hwmod am33xx_pruss_hwmod;
extern struct omap_hwmod am33xx_gfx_hwmod;
extern struct omap_hwmod am33xx_prcm_hwmod;
extern struct omap_hwmod am33xx_aes0_hwmod;
extern struct omap_hwmod am33xx_sha0_hwmod;
extern struct omap_hwmod am33xx_ocmcram_hwmod;
extern struct omap_hwmod am33xx_smartreflex0_hwmod;
extern struct omap_hwmod am33xx_smartreflex1_hwmod;
extern struct omap_hwmod am33xx_dcan0_hwmod;
extern struct omap_hwmod am33xx_dcan1_hwmod;
extern struct omap_hwmod am33xx_elm_hwmod;
extern struct omap_hwmod am33xx_epwmss0_hwmod;
extern struct omap_hwmod am33xx_epwmss1_hwmod;
extern struct omap_hwmod am33xx_epwmss2_hwmod;
extern struct omap_hwmod am33xx_gpmc_hwmod;
extern struct omap_hwmod am33xx_rtc_hwmod;
extern struct omap_hwmod am33xx_spi0_hwmod;
extern struct omap_hwmod am33xx_spi1_hwmod;
extern struct omap_hwmod am33xx_spinlock_hwmod;
extern struct omap_hwmod am33xx_timer1_hwmod;
extern struct omap_hwmod am33xx_timer2_hwmod;
extern struct omap_hwmod am33xx_timer3_hwmod;
extern struct omap_hwmod am33xx_timer4_hwmod;
extern struct omap_hwmod am33xx_timer5_hwmod;
extern struct omap_hwmod am33xx_timer6_hwmod;
extern struct omap_hwmod am33xx_timer7_hwmod;
extern struct omap_hwmod am33xx_tpcc_hwmod;
extern struct omap_hwmod am33xx_tptc0_hwmod;
extern struct omap_hwmod am33xx_tptc1_hwmod;
......@@ -94,7 +62,6 @@ extern struct omap_hwmod_class am33xx_l4_hwmod_class;
extern struct omap_hwmod_class am33xx_wkup_m3_hwmod_class;
extern struct omap_hwmod_class am33xx_control_hwmod_class;
extern struct omap_hwmod_class am33xx_timer_hwmod_class;
extern struct omap_hwmod_class am33xx_epwmss_hwmod_class;
extern struct omap_hwmod_class am33xx_ehrpwm_hwmod_class;
extern struct omap_hwmod_class am33xx_spi_hwmod_class;
......
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View file @ 955d8f3e
......@@ -106,50 +106,6 @@ struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
.user = OCP_USER_MPU,
};
/* l4 per/ls -> DCAN0 */
struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan0_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 per/ls -> DCAN1 */
struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_dcan1_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_elm_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_epwmss0_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_epwmss1_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_epwmss2_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l3s cfg -> gpmc */
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,
......@@ -158,30 +114,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.user = OCP_USER_MPU,
};
/* l4 ls -> spinlock */
struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spinlock_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 ls -> mcspi0 */
struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi0_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 ls -> mcspi1 */
struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_spi1_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 per -> timer2 */
struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
.master = &am33xx_l4_ls_hwmod,
......@@ -190,46 +122,6 @@ struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
.user = OCP_USER_MPU,
};
/* l4 per -> timer3 */
struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer3_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 per -> timer4 */
struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer4_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 per -> timer5 */
struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer5_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 per -> timer6 */
struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer6_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l4 per -> timer7 */
struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_timer7_hwmod,
.clk = "l4ls_gclk",
.user = OCP_USER_MPU,
};
/* l3 main -> tpcc */
struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
.master = &am33xx_l3_main_hwmod,
......@@ -268,19 +160,3 @@ struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
.slave = &am33xx_ocmcram_hwmod,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> sha0 HIB2 */
struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_sha0_hwmod,
.clk = "sha0_fck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l3 main -> AES0 HIB2 */
struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_aes0_hwmod,
.clk = "aes0_fck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View file @ 955d8f3e
......@@ -81,36 +81,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
};
/*
* 'adc/tsc' class
* TouchScreen Controller (Anolog-To-Digital Converter)
*/
static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
.rev_offs = 0x00,
.sysc_offs = 0x10,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
.name = "adc_tsc",
.sysc = &am33xx_adc_tsc_sysc,
};
static struct omap_hwmod am33xx_adc_tsc_hwmod = {
.name = "adc_tsc",
.class = &am33xx_adc_tsc_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.main_clk = "adc_tsc_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* Modules omap_hwmod structures
......@@ -226,34 +196,6 @@ static struct omap_hwmod am33xx_control_hwmod = {
},
};
/* lcdc */
static struct omap_hwmod_class_sysconfig lcdc_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x54,
.sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
.idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
.sysc_fields = &omap_hwmod_sysc_type2,
};
static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
.name = "lcdc",
.sysc = &lcdc_sysc,
};
static struct omap_hwmod am33xx_lcdc_hwmod = {
.name = "lcdc",
.class = &am33xx_lcdc_hwmod_class,
.clkdm_name = "lcdc_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.main_clk = "lcd_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/*
* Interfaces
......@@ -331,21 +273,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
.user = OCP_USER_MPU,
};
/* L4 WKUP -> ADC_TSC */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
.master = &am33xx_l4_wkup_hwmod,
.slave = &am33xx_adc_tsc_hwmod,
.clk = "dpll_core_m4_div2_ck",
.user = OCP_USER_MPU,
};
static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
.master = &am33xx_l3_main_hwmod,
.slave = &am33xx_lcdc_hwmod,
.clk = "dpll_core_m4_ck",
.user = OCP_USER_MPU,
};
/* l4 wkup -> timer1 */
static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
.master = &am33xx_l4_wkup_hwmod,
......@@ -375,32 +302,14 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
&am33xx_l4_wkup__smartreflex1,
&am33xx_l4_wkup__timer1,
&am33xx_l4_wkup__rtc,
&am33xx_l4_wkup__adc_tsc,
&am33xx_l4_hs__pruss,
&am33xx_l4_per__dcan0,
&am33xx_l4_per__dcan1,
&am33xx_l4_ls__timer2,
&am33xx_l4_ls__timer3,
&am33xx_l4_ls__timer4,
&am33xx_l4_ls__timer5,
&am33xx_l4_ls__timer6,
&am33xx_l4_ls__timer7,
&am33xx_l3_main__tpcc,
&am33xx_l4_ls__spinlock,
&am33xx_l4_ls__elm,
&am33xx_l4_ls__epwmss0,
&am33xx_l4_ls__epwmss1,
&am33xx_l4_ls__epwmss2,
&am33xx_l3_s__gpmc,
&am33xx_l3_main__lcdc,
&am33xx_l4_ls__mcspi0,
&am33xx_l4_ls__mcspi1,
&am33xx_l3_main__tptc0,
&am33xx_l3_main__tptc1,
&am33xx_l3_main__tptc2,
&am33xx_l3_main__ocmc,
&am33xx_l3_main__sha0,
&am33xx_l3_main__aes0,
NULL,
};
......
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View file @ 955d8f3e
......@@ -16,7 +16,6 @@
#include <linux/power/smartreflex.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/omap-dma.h>
#include "l3_3xxx.h"
#include "l4_3xxx.h"
......@@ -833,47 +832,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.class = &omap3xxx_gpio_hwmod_class,
};
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
.lch_count = 32,
};
static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap3xxx_dma_sysc,
};
/* dma_system */
static struct omap_hwmod omap3xxx_dma_system_hwmod = {
.name = "dma",
.class = &omap3xxx_dma_hwmod_class,
.main_clk = "core_l3_ick",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
},
},
.dev_attr = &dma_dev_attr,
.flags = HWMOD_NO_IDLEST,
};
/*
* 'mcbsp' class
* multi channel buffered serial port controller
......@@ -2233,23 +2191,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
.master = &omap3xxx_dma_system_hwmod,
.slave = &omap3xxx_l3_main_hwmod,
.clk = "core_l3_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dma_system_hwmod,
.clk = "core_l4_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> mcbsp1 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
.master = &omap3xxx_l4_core_hwmod,
......@@ -2628,8 +2569,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_per__gpio4,
&omap3xxx_l4_per__gpio5,
&omap3xxx_l4_per__gpio6,
&omap3xxx_dma_system__l3,
&omap3xxx_l4_core__dma_system,
&omap3xxx_l4_core__mcbsp1,
&omap3xxx_l4_per__mcbsp2,
&omap3xxx_l4_per__mcbsp3,
......
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
View file @ 955d8f3e
This diff is collapsed.
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ 955d8f3e
This diff is collapsed.
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View file @ 955d8f3e
This diff is collapsed.
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View file @ 955d8f3e
This diff is collapsed.
arch/arm/mach-omap2/omap_hwmod_common_data.h
View file @ 955d8f3e
......@@ -98,7 +98,6 @@ extern struct omap_hwmod_class omap2_hdq1w_class;
extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
extern struct omap_hwmod_class omap2xxx_mcspi_class;
......
arch/arm/mach-omap2/omap_hwmod_reset.c
View file @ 955d8f3e
......@@ -26,8 +26,6 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <sound/aess.h>
#include "omap_hwmod.h"
#include "common.h"
......@@ -40,28 +38,6 @@
#define OMAP_RTC_STATUS_BUSY BIT(0)
#define OMAP_RTC_MAX_READY_TIME 50
/**
* omap_hwmod_aess_preprogram - enable AESS internal autogating
* @oh: struct omap_hwmod *
*
* The AESS will not IdleAck to the PRCM until its internal autogating
* is enabled. Since internal autogating is disabled by default after
* AESS reset, we must enable autogating after the hwmod code resets
* the AESS. Returns 0.
*/
int omap_hwmod_aess_preprogram(struct omap_hwmod *oh)
{
void __iomem *va;
va = omap_hwmod_get_mpu_rt_va(oh);
if (!va)
return -EINVAL;
aess_enable_autogating(va);
return 0;
}
/**
* omap_rtc_wait_not_busy - Wait for the RTC BUSY flag
* @oh: struct omap_hwmod *
......
arch/arm/mach-omap2/pdata-quirks.c
View file @ 955d8f3e
......@@ -306,10 +306,14 @@ static void __init dra7x_evm_mmc_quirk(void)
static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk)
{
struct clk_hw *hw = __clk_get_hw(clk);
struct clockdomain *clkdm = NULL;
struct clk_hw_omap *hwclk;
hwclk = to_clk_hw_omap(__clk_get_hw(clk));
hwclk = to_clk_hw_omap(hw);
if (!omap2_clk_is_hw_omap(hw))
return NULL;
if (hwclk && hwclk->clkdm_name)
clkdm = clkdm_lookup(hwclk->clkdm_name);
......@@ -510,6 +514,7 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
/* Common auxdata */
OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
OF_DEV_AUXDATA("ti,omap-sdma", 0, NULL, &dma_plat_info),
{ /* sentinel */ },
};
......
arch/arm/mach-omap2/pm24xx.c
View file @ 955d8f3e
......@@ -83,8 +83,6 @@ static int omap2_enter_full_retention(void)
l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
cpu_cluster_pm_enter();
/* One last check for pending IRQs to avoid extra latency due
* to sleeping unnecessarily. */
if (omap_irq_pending())
......@@ -96,8 +94,6 @@ static int omap2_enter_full_retention(void)
OMAP_SDRC_REGADDR(SDRC_POWER));
no_sleep:
cpu_cluster_pm_exit();
clk_enable(osc_ck);
/* clear CORE wake-up events */
......@@ -162,25 +158,27 @@ static int omap2_can_sleep(void)
return 0;
if (__clk_is_enabled(osc_ck))
return 0;
if (omap_dma_running())
return 0;
return 1;
}
static void omap2_pm_idle(void)
{
if (!omap2_can_sleep()) {
if (omap_irq_pending())
return;
omap2_enter_mpu_retention();
return;
}
int error;
if (omap_irq_pending())
return;
error = cpu_cluster_pm_enter();
if (error || !omap2_can_sleep()) {
omap2_enter_mpu_retention();
goto out_cpu_cluster_pm;
}
omap2_enter_full_retention();
out_cpu_cluster_pm:
cpu_cluster_pm_exit();
}
static void __init prcm_setup_regs(void)
......
arch/arm/mach-omap2/pm34xx.c
View file @ 955d8f3e
......@@ -25,7 +25,6 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/omap-dma.h>
#include <linux/omap-gpmc.h>
#include <trace/events/power.h>
......@@ -85,7 +84,6 @@ static void omap3_core_save_context(void)
omap3_gpmc_save_context();
/* Save the system control module context, padconf already save above*/
omap3_control_save_context();
omap_dma_global_context_save();
}
static void omap3_core_restore_context(void)
......@@ -96,7 +94,6 @@ static void omap3_core_restore_context(void)
omap3_gpmc_restore_context();
/* Restore the interrupt controller context */
omap_intc_restore_context();
omap_dma_global_context_restore();
}
/*
......@@ -547,9 +544,7 @@ int __init omap3_pm_init(void)
local_irq_disable();
omap_dma_global_context_save();
omap3_save_secure_ram_context();
omap_dma_global_context_restore();
local_irq_enable();
}
......
arch/arm/plat-omap/dma.c
View file @ 955d8f3e
This diff is collapsed.
drivers/bus/ti-sysc.c
View file @ 955d8f3e
......@@ -343,6 +343,12 @@ static int sysc_get_clocks(struct sysc *ddata)
return -EINVAL;
}
/* Always add a slot for main clocks fck and ick even if unused */
if (!nr_fck)
ddata->nr_clocks++;
if (!nr_ick)
ddata->nr_clocks++;
ddata->clocks = devm_kcalloc(ddata->dev,
ddata->nr_clocks, sizeof(*ddata->clocks),
GFP_KERNEL);
......@@ -421,7 +427,7 @@ static int sysc_enable_opt_clocks(struct sysc *ddata)
struct clk *clock;
int i, error;
if (!ddata->clocks)
if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
return 0;
for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
......@@ -455,7 +461,7 @@ static void sysc_disable_opt_clocks(struct sysc *ddata)
struct clk *clock;
int i;
if (!ddata->clocks)
if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
return;
for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
......@@ -981,7 +987,8 @@ static int sysc_disable_module(struct device *dev)
return ret;
}
if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
best_mode = SYSC_IDLE_FORCE;
reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
......@@ -1583,6 +1590,10 @@ static int sysc_reset(struct sysc *ddata)
sysc_val |= sysc_mask;
sysc_write(ddata, sysc_offset, sysc_val);
if (ddata->cfg.srst_udelay)
usleep_range(ddata->cfg.srst_udelay,
ddata->cfg.srst_udelay * 2);
if (ddata->clk_enable_quirk)
ddata->clk_enable_quirk(ddata);
......
drivers/clk/ti/clk-44xx.c
View file @ 955d8f3e
......@@ -604,6 +604,18 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
{ 0 },
};
static const struct
omap_clkctrl_reg_data omap4_l4_secure_clkctrl_regs[] __initconst = {
{ OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
{ OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
{ 0 },
};
static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
{ 0 },
......@@ -691,6 +703,7 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
{ 0x4a009220, omap4_l3_gfx_clkctrl_regs },
{ 0x4a009320, omap4_l3_init_clkctrl_regs },
{ 0x4a009420, omap4_l4_per_clkctrl_regs },
{ 0x4a0095a0, omap4_l4_secure_clkctrl_regs },
{ 0x4a307820, omap4_l4_wkup_clkctrl_regs },
{ 0x4a307a20, omap4_emu_sys_clkctrl_regs },
{ 0 },
......
drivers/clk/ti/clk-54xx.c
View file @ 955d8f3e
......@@ -35,6 +35,20 @@ static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst =
{ 0 },
};
static const char * const omap5_aess_fclk_parents[] __initconst = {
"abe_clk",
NULL,
};
static const struct omap_clkctrl_div_data omap5_aess_fclk_data __initconst = {
.max_div = 2,
};
static const struct omap_clkctrl_bit_data omap5_aess_bit_data[] __initconst = {
{ 24, TI_CLK_DIVIDER, omap5_aess_fclk_parents, &omap5_aess_fclk_data },
{ 0 },
};
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
"abe_cm:clk:0018:26",
"pad_clks_ck",
......@@ -122,6 +136,7 @@ static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst =
static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
......@@ -286,6 +301,18 @@ static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst
{ 0 },
};
static const struct
omap_clkctrl_reg_data omap5_l4_secure_clkctrl_regs[] __initconst = {
{ OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "" },
{ OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "" },
{ OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "" },
{ OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "" },
{ OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
{ OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "" },
{ OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },
{ 0 },
};
static const struct omap_clkctrl_reg_data omap5_iva_clkctrl_regs[] __initconst = {
{ OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
{ OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
......@@ -508,6 +535,7 @@ const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
{ 0x4a008d20, omap5_l4cfg_clkctrl_regs },
{ 0x4a008e20, omap5_l3instr_clkctrl_regs },
{ 0x4a009020, omap5_l4per_clkctrl_regs },
{ 0x4a0091a0, omap5_l4_secure_clkctrl_regs },
{ 0x4a009220, omap5_iva_clkctrl_regs },
{ 0x4a009420, omap5_dss_clkctrl_regs },
{ 0x4a009520, omap5_gpu_clkctrl_regs },
......
drivers/clk/ti/clk-7xx.c
View file @ 955d8f3e
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drivers/clk/ti/clk.c
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drivers/clk/ti/clkctrl.c
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drivers/dma/ti/omap-dma.c
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include/dt-bindings/clock/dra7.h
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include/dt-bindings/clock/omap4.h
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include/dt-bindings/clock/omap5.h
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include/linux/omap-dma.h
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include/linux/platform_data/ti-sysc.h
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include/sound/aess.h deleted 100644 → 0
View file @ d1eef1c6
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