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Commit 9798df72 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
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staging: comedi: addi_apci_3501: define the timer i/o registers 

Create, and use, defines for the i/o registers used with the timer
subdevice.
Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 6ff35881
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Showing with 57 additions and 118 deletions
drivers/staging/comedi/drivers/addi-data/hwdrv_apci3501.c
View file @ 9798df72
/* Watchdog Related Defines */
#define APCI3501_WATCHDOG 0x20
#define APCI3501_TCW_SYNC_ENABLEDISABLE 0
#define APCI3501_TCW_RELOAD_VALUE 4
#define APCI3501_TCW_TIMEBASE 8
#define APCI3501_TCW_PROG 12
#define APCI3501_TCW_TRIG_STATUS 16
#define APCI3501_TCW_IRQ 20
#define APCI3501_TCW_WARN_TIMEVAL 24
#define APCI3501_TCW_WARN_TIMEBASE 28
#define ADDIDATA_TIMER 0
#define ADDIDATA_WATCHDOG 2
......@@ -52,69 +43,47 @@ static int i_APCI3501_ConfigTimerCounterWatchdog(struct comedi_device *dev,
devpriv->b_TimerSelectMode = ADDIDATA_WATCHDOG;
/* Disable the watchdog */
outl(0x0, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Wa */
outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
if (data[1] == 1) {
/* Enable TIMER int & DISABLE ALL THE OTHER int SOURCES */
outl(0x02,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
outl(0x02, dev->iobase + APCI3501_TIMER_CTRL_REG);
} else {
outl(0x0, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Timer interrupt */
/* disable Timer interrupt */
outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
/* Loading the Timebase value */
outl(data[2],
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_TIMEBASE);
outl(data[2], dev->iobase + APCI3501_TIMER_TIMEBASE_REG);
outl(data[3], dev->iobase + APCI3501_TIMER_RELOAD_REG);
/* Loading the Reload value */
outl(data[3],
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_RELOAD_VALUE);
/* Set the mode */
ul_Command1 = inl(dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG) | 0xFFF819E0UL; /* e2->e0 */
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
} /* end if(data[0]==ADDIDATA_WATCHDOG) */
/* Set the mode (e2->e0) */
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG) | 0xFFF819E0UL;
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
else if (data[0] == ADDIDATA_TIMER) {
/* First Stop The Timer */
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = ul_Command1 & 0xFFFFF9FEUL;
outl(ul_Command1, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* Stop The Timer */
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
devpriv->b_TimerSelectMode = ADDIDATA_TIMER;
if (data[1] == 1) {
/* Enable TIMER int & DISABLE ALL THE OTHER int SOURCES */
outl(0x02,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
outl(0x02, dev->iobase + APCI3501_TIMER_CTRL_REG);
} else {
outl(0x0, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* disable Timer interrupt */
/* disable Timer interrupt */
outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
/* Loading Timebase */
outl(data[2],
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_TIMEBASE);
/* Loading the Reload value */
outl(data[3],
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_RELOAD_VALUE);
outl(data[2], dev->iobase + APCI3501_TIMER_TIMEBASE_REG);
outl(data[3], dev->iobase + APCI3501_TIMER_RELOAD_REG);
/* printk ("\nTimer Address :: %x\n", (dev->iobase + APCI3501_WATCHDOG)); */
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
/* mode 2 */
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 =
(ul_Command1 & 0xFFF719E2UL) | 2UL << 13UL | 0x10UL;
outl(ul_Command1, dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG); /* mode 2 */
} /* end if(data[0]==ADDIDATA_TIMER) */
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
return insn->n;
}
......@@ -156,73 +125,48 @@ static int i_APCI3501_StartStopWriteTimerCounterWatchdog(struct comedi_device *d
if (devpriv->b_TimerSelectMode == ADDIDATA_WATCHDOG) {
if (data[1] == 1) {
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x1UL;
/* Enable the Watchdog */
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
else if (data[1] == 0) /* Stop The Watchdog */
{
/* Stop The Watchdog */
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = ul_Command1 & 0xFFFFF9FEUL;
outl(0x0,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG);
} else if (data[1] == 2) {
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x200UL;
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
} /* if(data[1]==2) */
} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_WATCHDOG) */
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
}
if (devpriv->b_TimerSelectMode == ADDIDATA_TIMER) {
if (data[1] == 1) {
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x1UL;
/* Enable the Timer */
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
} else if (data[1] == 0) {
/* Stop The Timer */
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = ul_Command1 & 0xFFFFF9FEUL;
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
else if (data[1] == 2) {
/* Trigger the Timer */
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = (ul_Command1 & 0xFFFFF9FFUL) | 0x200UL;
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_PROG);
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
}
}
} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_TIMER) */
i_Temp = inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_TRIG_STATUS) & 0x1;
i_Temp = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
return insn->n;
}
......@@ -258,18 +202,14 @@ static int i_APCI3501_ReadTimerCounterWatchdog(struct comedi_device *dev,
struct apci3501_private *devpriv = dev->private;
if (devpriv->b_TimerSelectMode == ADDIDATA_WATCHDOG) {
data[0] =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_TRIG_STATUS) & 0x1;
data[1] = inl(dev->iobase + APCI3501_WATCHDOG);
} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_WATCHDOG) */
data[0] = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
data[1] = inl(dev->iobase + APCI3501_TIMER_SYNC_REG);
}
else if (devpriv->b_TimerSelectMode == ADDIDATA_TIMER) {
data[0] =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_TRIG_STATUS) & 0x1;
data[1] = inl(dev->iobase + APCI3501_WATCHDOG);
} /* end if (devpriv->b_TimerSelectMode==ADDIDATA_TIMER) */
data[0] = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
data[1] = inl(dev->iobase + APCI3501_TIMER_SYNC_REG);
}
else if ((devpriv->b_TimerSelectMode != ADDIDATA_TIMER)
&& (devpriv->b_TimerSelectMode != ADDIDATA_WATCHDOG)) {
......
drivers/staging/comedi/drivers/addi_apci_3501.c
View file @ 9798df72
......@@ -44,6 +44,14 @@
#define APCI3501_AO_DATA_VAL(x) ((x) << 8)
#define APCI3501_AO_DATA_BIPOLAR (1 << 31)
#define APCI3501_AO_TRIG_SCS_REG 0x08
#define APCI3501_TIMER_SYNC_REG 0x20
#define APCI3501_TIMER_RELOAD_REG 0x24
#define APCI3501_TIMER_TIMEBASE_REG 0x28
#define APCI3501_TIMER_CTRL_REG 0x2c
#define APCI3501_TIMER_STATUS_REG 0x30
#define APCI3501_TIMER_IRQ_REG 0x34
#define APCI3501_TIMER_WARN_RELOAD_REG 0x38
#define APCI3501_TIMER_WARN_TIMEBASE_REG 0x3c
#define APCI3501_DO_REG 0x40
#define APCI3501_DI_REG 0x50
......@@ -268,17 +276,11 @@ static irqreturn_t apci3501_interrupt(int irq, void *d)
int i_temp;
/* Disable Interrupt */
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = (ul_Command1 & 0xFFFFF9FDul);
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
ui_Timer_AOWatchdog =
inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_IRQ) & 0x1;
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
ui_Timer_AOWatchdog = inl(dev->iobase + APCI3501_TIMER_IRQ_REG) & 0x1;
if ((!ui_Timer_AOWatchdog)) {
comedi_error(dev, "IRQ from unknown source");
return IRQ_NONE;
......@@ -286,13 +288,10 @@ static irqreturn_t apci3501_interrupt(int irq, void *d)
/* Enable Interrupt Send a signal to from kernel to user space */
send_sig(SIGIO, devpriv->tsk_Current, 0);
ul_Command1 =
inl(dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG);
ul_Command1 = ((ul_Command1 & 0xFFFFF9FDul) | 1 << 1);
outl(ul_Command1,
dev->iobase + APCI3501_WATCHDOG + APCI3501_TCW_PROG);
i_temp = inl(dev->iobase + APCI3501_WATCHDOG +
APCI3501_TCW_TRIG_STATUS) & 0x1;
outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG);
i_temp = inl(dev->iobase + APCI3501_TIMER_STATUS_REG) & 0x1;
return IRQ_HANDLED;
}
......
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