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Commit 979bb590 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "There is nothing exciting going on, no core changes, just a few
  drivers and cleanups.

  New drivers:

   - Cypress CY8C95x0 chip pin control support, along with an immediate
     cleanup

   - Mediatek MT8188 SoC pin control support

   - Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin
     control support

   - Qualcomm PM7250, PM8450

   - Rockchip RV1126 SoC pin control support

  Improvements:

   - Fix some missing pins in the Armada 37xx driver

   - Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP()
     macro

   - Fix some GPIO irq_chips to be immutable

   - Massive Qualcomm device tree binding cleanup, with more to come"

* tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits)
  MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement
  pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"
  pinctrl: Create subdirectory for StarFive drivers
  dt-bindings: pinctrl: st,stm32: Document interrupt-controller property
  dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property
  dt-bindings: pinctrl: st,stm32: Document gpio-line-names
  pinctrl: st: stop abusing of_get_named_gpio()
  pinctrl: wpcm450: Correct the fwnode_irq_get() return value check
  pinctrl: bcm: Remove unused struct bcm6328_pingroup
  pinctrl: qcom: restrict drivers per ARM/ARM64
  pinctrl: bcm: ns: Remove redundant dev_err call
  gpio: rockchip: request GPIO mux to pinctrl when setting direction
  pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback
  pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops
  pinctrl: cy8c95x0: Drop atomicity on operations on push_pull
  pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux()
  pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper
  pinctrl: stm32: Switch to use dev_err_probe() helper
  dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings
  pinctrl: qcom: spmi-gpio: Add compatible for PM7250B
  ...
parents 694b37a5 9d157c89
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Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
View file @ 979bb590
......@@ -63,6 +63,12 @@ examples:
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e6e2000 0x1000>;
pinctrl: pinctrl {
compatible = "aspeed,ast2400-pinctrl";
......
Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
View file @ 979bb590
......@@ -82,6 +82,10 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e6e2000 0x1000>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx>, <&lhc>;
......
Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
View file @ 979bb590
......@@ -96,6 +96,12 @@ examples:
syscon: scu@1e6e2000 {
compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0xf6c>;
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e6e2000 0x1000>;
pinctrl: pinctrl {
compatible = "aspeed,ast2600-pinctrl";
......
Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
View file @ 979bb590
......@@ -23,6 +23,7 @@ patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
function:
......
Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml 0 → 100644
View file @ 979bb590
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/cypress,cy8c95x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cypress CY8C95X0 I2C GPIO expander
maintainers:
- Patrick Rudolph <patrick.rudolph@9elements.com>
description: |
This supports the 20/40/60 pin Cypress CYC95x0 GPIO I2C expanders.
Pin function configuration is performed on a per-pin basis.
properties:
compatible:
enum:
- cypress,cy8c9520
- cypress,cy8c9540
- cypress,cy8c9560
reg:
maxItems: 1
gpio-controller: true
'#gpio-cells':
description:
The first cell is the GPIO number and the second cell specifies GPIO
flags, as defined in <dt-bindings/gpio/gpio.h>.
const: 2
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-line-names: true
gpio-ranges:
maxItems: 1
gpio-reserved-ranges:
maxItems: 1
vdd-supply:
description:
Optional power supply.
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: pincfg-node.yaml#
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: '^gp([0-7][0-7])$'
minItems: 1
maxItems: 60
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, pwm ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
drive-push-pull: true
drive-open-drain: true
drive-open-source: true
required:
- pins
- function
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pinctrl@20 {
compatible = "cypress,cy8c9520";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
vdd-supply = <&p3v3>;
gpio-reserved-ranges = <5 1>;
};
};
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml
View file @ 979bb590
......@@ -44,6 +44,7 @@ properties:
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
additionalProperties: false
description:
Child nodes can be specified to contain pin configuration information,
......
Documentation/devicetree/bindings/pinctrl/intel,pinctrl-thunderbay.yaml
View file @ 979bb590
......@@ -42,6 +42,7 @@ properties:
patternProperties:
'^gpio@[0-9a-f]*$':
type: object
additionalProperties: false
description:
Child nodes can be specified to contain pin configuration information,
......
Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml
View file @ 979bb590
......@@ -24,6 +24,7 @@ patternProperties:
'-pins$':
type: object
$ref: pinmux-node.yaml#
additionalProperties: false
properties:
marvell,function:
......
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
View file @ 979bb590
......@@ -76,6 +76,8 @@ required:
patternProperties:
'-[0-9]*$':
type: object
additionalProperties: false
patternProperties:
'-pins*$':
type: object
......
Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml
View file @ 979bb590
......@@ -117,6 +117,10 @@ patternProperties:
"i2s" "audio" 62, 63, 64, 65
"switch_int" "eth" 66
"mdc_mdio" "eth" 67
"wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83
"wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100
"wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
84, 85
$ref: "/schemas/pinctrl/pinmux-node.yaml"
properties:
......@@ -234,7 +238,9 @@ patternProperties:
then:
properties:
groups:
enum: [wf_2g, wf_5g, wf_dbdc]
items:
enum: [wf_2g, wf_5g, wf_dbdc]
maxItems: 3
'.*conf.*':
type: object
additionalProperties: false
......@@ -248,25 +254,27 @@ patternProperties:
An array of strings. Each string contains the name of a pin.
There is no PIN 41 to PIN 65 above on mt7686b, you can only use
those pins on mt7986a.
enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14,
GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS,
SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS,
SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP,
UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD,
UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS,
UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2,
EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6,
EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX,
PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
WF1_HB8]
items:
enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14,
GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS,
SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS,
SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP,
UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD,
UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS,
UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2,
EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6,
EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX,
PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
WF1_HB8]
maxItems: 101
bias-disable: true
......
Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml 0 → 100644
View file @ 979bb590
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT8188 Pin Controller
maintainers:
- Hui Liu <hui.liu@mediatek.com>
description: |
The MediaTek's MT8188 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8188-pinctrl
gpio-controller: true
'#gpio-cells':
description: |
Number of cells in GPIO specifier, should be two. The first cell
is the pin number, the second cell is used to specify optional
parameters which are defined in <dt-bindings/gpio/gpio.h>.
const: 2
gpio-ranges:
maxItems: 1
gpio-line-names: true
reg:
items:
- description: gpio registers base address
- description: rm group io configuration registers base address
- description: lt group io configuration registers base address
- description: lm group io configuration registers base address
- description: rt group io configuration registers base address
- description: eint registers base address
reg-names:
items:
- const: iocfg0
- const: iocfg_rm
- const: iocfg_lt
- const: iocfg_lm
- const: iocfg_rt
- const: eint
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
mediatek,rsel-resistance-in-si-unit:
type: boolean
description: |
We provide two methods to select the resistance for I2C when pull up or pull down.
The first is by RSEL definition value, another one is by resistance value(ohm).
This flag is used to identify if the method is resistance(si unit) value.
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
$ref: "/schemas/pinctrl/pincfg-node.yaml"
additionalProperties: false
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and
input schmitt.
properties:
pinmux:
description: |
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in dt-bindings/pinctrl/mediatek,<soc>-pinfunc.h
directly.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8188 pull down PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
description: mt8188 pull down RSEL type define value.
- enum: [75000, 5000]
description: mt8188 pull down RSEL type si unit value(ohm).
description: |
For pull down type is normal, it doesn't need add RSEL & R1R0 define
and resistance value.
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
define in mt8188.
For pull down type is RSEL, it can add RSEL define & resistance value(ohm)
to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
& "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
define in mt8188. It can also support resistance value(ohm) "75000" & "5000" in mt8188.
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8188 pull up PUPD/R0/R1 type define value.
- enum: [200, 201, 202, 203, 204, 205, 206, 207]
description: mt8188 pull up RSEL type define value.
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000]
description: mt8188 pull up RSEL type si unit value(ohm).
description: |
For pull up type is normal, it don't need add RSEL & R1R0 define
and resistance value.
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & "MTK_PUPD_SET_R1R0_11"
define in mt8188.
For pull up type is RSEL, it can add RSEL define & resistance value(ohm)
to set different resistance by identifying property "mediatek,rsel-resistance-in-si-unit".
It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001"
& "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & "MTK_PULL_SET_RSEL_100"
& "MTK_PULL_SET_RSEL_101" & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111"
define in mt8188. It can also support resistance value(ohm)
"1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188.
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8188-pinctrl";
reg = <0x10005000 0x1000>,
<0x11c00000 0x1000>,
<0x11e10000 0x1000>,
<0x11e20000 0x1000>,
<0x11ea0000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_rm",
"iocfg_lt", "iocfg_lm", "iocfg_rt",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 176>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
pio-pins {
pins {
pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>;
output-low;
};
};
spi0-pins {
pins-spi {
pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
<PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
<PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>;
drive-strength = <6>;
};
pins-spi-mi {
pinmux = <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
};
};
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO55__FUNC_B1_SCL0>,
<PINMUX_GPIO56__FUNC_B1_SDA0>;
bias-disable;
drive-strength-microamp = <1000>;
};
};
};
Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml
View file @ 979bb590
......@@ -30,6 +30,7 @@ patternProperties:
"^gpio@[0-7]$":
type: object
additionalProperties: false
description:
Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
......
Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml
View file @ 979bb590
......@@ -41,12 +41,12 @@ properties:
Gpio base register names.
items:
- const: iocfg0
- const: iocfg_bm
- const: iocfg_bl
- const: iocfg_br
- const: iocfg_lt
- const: iocfg_lm
- const: iocfg_lb
- const: iocfg_bl
- const: iocfg_rb
- const: iocfg_tl
- const: iocfg_rt
- const: eint
interrupt-controller: true
......@@ -235,9 +235,9 @@ examples:
<0x10002A00 0x0200>,
<0x10002c00 0x0200>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
"iocfg_br", "iocfg_lm", "iocfg_rb",
"iocfg_tl", "eint";
reg-names = "iocfg0", "iocfg_lt", "iocfg_lm",
"iocfg_lb", "iocfg_bl", "iocfg_rb",
"iocfg_rt", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 185>;
......
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
View file @ 979bb590
......@@ -24,6 +24,7 @@ properties:
- qcom,pm6150-gpio
- qcom,pm6150l-gpio
- qcom,pm6350-gpio
- qcom,pm7250b-gpio
- qcom,pm7325-gpio
- qcom,pm8005-gpio
- qcom,pm8008-gpio
......@@ -231,6 +232,7 @@ allOf:
enum:
- qcom,pm660l-gpio
- qcom,pm6150l-gpio
- qcom,pm7250b-gpio
- qcom,pm8038-gpio
- qcom,pm8150b-gpio
- qcom,pm8150l-gpio
......@@ -392,6 +394,7 @@ $defs:
- gpio1-gpio10 for pm6150
- gpio1-gpio12 for pm6150l
- gpio1-gpio9 for pm6350
- gpio1-gpio12 for pm7250b
- gpio1-gpio10 for pm7325
- gpio1-gpio4 for pm8005
- gpio1-gpio2 for pm8008
......@@ -407,6 +410,7 @@ $defs:
- gpio1-gpio10 for pm8350
- gpio1-gpio8 for pm8350b
- gpio1-gpio9 for pm8350c
- gpio1-gpio4 for pm8450
- gpio1-gpio38 for pm8917
- gpio1-gpio44 for pm8921
- gpio1-gpio36 for pm8941
......
Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml
View file @ 979bb590
......@@ -42,6 +42,9 @@ properties:
gpio-ranges:
maxItems: 1
gpio-line-names:
maxItems: 174
wakeup-parent: true
#PIN CONFIGURATION NODES
......@@ -51,7 +54,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "/schemas/pinctrl/pincfg-node.yaml"
properties:
pins:
......@@ -60,7 +62,7 @@ patternProperties:
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$"
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
sdc2_cmd, sdc2_data, ufs_reset ]
minItems: 1
......@@ -118,12 +120,21 @@ patternProperties:
required:
- pins
- function
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-2])$"
then:
required:
- function
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
required:
- compatible
......@@ -139,22 +150,22 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f000000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0xf000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
qup_uart5_default: qup-uart5-pins {
pins = "gpio46", "gpio47";
function = "qup13";
drive-strength = <2>;
bias-disable;
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f000000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0xf000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
qup_uart5_default: qup-uart5-pins {
pins = "gpio46", "gpio47";
function = "qup13";
drive-strength = <2>;
bias-disable;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml
View file @ 979bb590
......@@ -51,8 +51,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sc8180x-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sc8180x-tlmm-state"
additionalProperties: false
'$defs':
qcom-sc8180x-tlmm-state:
......@@ -60,7 +61,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -111,43 +111,52 @@ patternProperties:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$"
then:
required:
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@3100000 {
compatible = "qcom,sc8180x-tlmm";
reg = <0x03100000 0x300000>,
<0x03500000 0x700000>,
<0x03d00000 0x300000>;
reg-names = "west", "east", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 190>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio4";
function = "qup6";
bias-pull-up;
};
tx {
pins = "gpio5";
function = "qup6";
bias-disable;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@3100000 {
compatible = "qcom,sc8180x-tlmm";
reg = <0x03100000 0x300000>,
<0x03500000 0x700000>,
<0x03d00000 0x300000>;
reg-names = "west", "east", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 190>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx-pins {
pins = "gpio4";
function = "qup6";
bias-pull-up;
};
tx-pins {
pins = "gpio5";
function = "qup6";
bias-disable;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml 0 → 100644
View file @ 979bb590
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
Low Power Island (LPI) TLMM block
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
LPASS LPI IP on most Qualcomm SoCs
properties:
compatible:
const: qcom,sc8280xp-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-1]|1[0-8]])$"
function:
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data,
ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ]
description:
Specify the alternative function to be configured for the specified
pins.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
slew-rate:
enum: [0, 1, 2, 3]
default: 0
description: |
0: No adjustments
1: Higher Slew rate (faster edges)
2: Lower Slew rate (slower edges)
3: Reserved (No adjustments)
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6afe.h>
pinctrl@33c0000 {
compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
reg = <0x33c0000 0x20000>,
<0x3550000 0x10000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 18>;
};
Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml
View file @ 979bb590
......@@ -43,8 +43,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sc8280xp-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sc8280xp-tlmm-state"
additionalProperties: false
'$defs':
qcom-sc8280xp-tlmm-state:
......@@ -52,7 +53,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -112,40 +112,49 @@ patternProperties:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$"
then:
required:
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sc8280xp-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 230>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio4";
function = "qup14";
bias-pull-up;
};
tx {
pins = "gpio5";
function = "qup14";
bias-disable;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sc8280xp-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 230>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx-pins {
pins = "gpio4";
function = "qup14";
bias-pull-up;
};
tx-pins {
pins = "gpio5";
function = "qup14";
bias-disable;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml
View file @ 979bb590
......@@ -49,6 +49,8 @@ properties:
gpio-ranges:
maxItems: 1
gpio-reserved-ranges: true
wakeup-parent: true
#PIN CONFIGURATION NODES
......@@ -57,8 +59,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6115-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6115-tlmm-state"
additionalProperties: false
'$defs':
qcom-sm6115-tlmm-state:
......@@ -66,7 +69,6 @@ patternProperties:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -118,6 +120,16 @@ patternProperties:
required:
- pins
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
then:
required:
- function
additionalProperties: false
allOf:
......@@ -138,44 +150,44 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x500000 0x400000>,
<0x900000 0x400000>,
<0xd00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 114>;
sdc2_on_state: sdc2-on-state {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio88";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@500000 {
compatible = "qcom,sm6115-tlmm";
reg = <0x500000 0x400000>,
<0x900000 0x400000>,
<0xd00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 114>;
sdc2_on_state: sdc2-on-state {
clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd-pins {
pins = "gpio88";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml
View file @ 979bb590
......@@ -51,8 +51,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6125-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6125-tlmm-state"
additionalProperties: false
$defs:
qcom-sm6125-tlmm-state:
......@@ -60,7 +61,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -111,23 +111,52 @@ $defs:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
then:
required:
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@500000 {
compatible = "qcom,sm6125-tlmm";
reg = <0x00500000 0x400000>,
<0x00900000 0x400000>,
<0x00d00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 134>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@500000 {
compatible = "qcom,sm6125-tlmm";
reg = <0x00500000 0x400000>,
<0x00900000 0x400000>,
<0x00d00000 0x400000>;
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 134>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
sdc2-off-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,sm6350-pinctrl.yaml
View file @ 979bb590
......@@ -44,8 +44,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6350-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6350-tlmm-state"
additionalProperties: false
$defs:
qcom-sm6350-tlmm-state:
......@@ -53,7 +54,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -110,40 +110,49 @@ $defs:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$"
then:
required:
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sm6350-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio25";
function = "qup13_f2";
bias-disable;
};
tx {
pins = "gpio26";
function = "qup13_f2";
bias-disable;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sm6350-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx-pins {
pins = "gpio25";
function = "qup13_f2";
bias-disable;
};
tx-pins {
pins = "gpio26";
function = "qup13_f2";
bias-disable;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml
View file @ 979bb590
......@@ -44,8 +44,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm6375-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm6375-tlmm-state"
additionalProperties: false
$defs:
qcom-sm6375-tlmm-state:
......@@ -53,7 +54,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -119,40 +119,49 @@ $defs:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
then:
required:
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@500000 {
compatible = "qcom,sm6375-tlmm";
reg = <0x00500000 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio18";
function = "qup13_f2";
bias-pull-up;
};
tx {
pins = "gpio19";
function = "qup13_f2";
bias-disable;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@500000 {
compatible = "qcom,sm6375-tlmm";
reg = <0x00500000 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx-pins {
pins = "gpio18";
function = "qup13_f2";
bias-pull-up;
};
tx-pins {
pins = "gpio19";
function = "qup13_f2";
bias-disable;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
View file @ 979bb590
......@@ -110,7 +110,16 @@ patternProperties:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
then:
required:
- function
additionalProperties: false
......@@ -132,18 +141,18 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@1f00000 {
compatible = "qcom,sm8250-pinctrl";
reg = <0x0f100000 0x300000>,
<0x0f500000 0x300000>,
<0x0f900000 0x300000>;
reg-names = "west", "south", "north";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 180>;
wakeup-parent = <&pdc>;
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@1f00000 {
compatible = "qcom,sm8250-pinctrl";
reg = <0x0f100000 0x300000>,
<0x0f500000 0x300000>,
<0x0f900000 0x300000>;
reg-names = "west", "south", "north";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 180>;
wakeup-parent = <&pdc>;
};
Documentation/devicetree/bindings/pinctrl/qcom,sm8350-pinctrl.yaml
View file @ 979bb590
......@@ -44,8 +44,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm8350-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm8350-tlmm-state"
additionalProperties: false
$defs:
qcom-sm8350-tlmm-state:
......@@ -53,7 +54,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -107,40 +107,49 @@ $defs:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
then:
required:
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sm8350-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 203>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio18";
function = "qup3";
bias-pull-up;
};
tx {
pins = "gpio19";
function = "qup3";
bias-disable;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sm8350-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 203>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx-pins {
pins = "gpio18";
function = "qup3";
bias-pull-up;
};
tx-pins {
pins = "gpio19";
function = "qup3";
bias-disable;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml 0 → 100644
View file @ 979bb590
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
Low Power Island (LPI) TLMM block
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
This binding describes the Top Level Mode Multiplexer block found in the
LPASS LPI IP on most Qualcomm SoCs
properties:
compatible:
const: qcom,sm8450-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
gpio-controller: true
'#gpio-cells':
description: Specifying the pin number and flags, as defined in
include/dt-bindings/gpio/gpio.h
const: 2
gpio-ranges:
maxItems: 1
#PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-2][0-9]])$"
function:
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data,
slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data,
ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d,
ext_mclk1_e ]
description:
Specify the alternative function to be configured for the specified
pins.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
default: 2
description:
Selects the drive strength for the specified pins, in mA.
slew-rate:
enum: [0, 1, 2, 3]
default: 0
description: |
0: No adjustments
1: Higher Slew rate (faster edges)
2: Lower Slew rate (slower edges)
3: Reserved (No adjustments)
bias-pull-down: true
bias-pull-up: true
bias-disable: true
output-high: true
output-low: true
required:
- pins
- function
additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6afe.h>
pinctrl@3440000 {
compatible = "qcom,sm8450-lpass-lpi-pinctrl";
reg = <0x3440000 0x20000>,
<0x34d0000 0x10000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "audio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 23>;
};
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-pinctrl.yaml
View file @ 979bb590
......@@ -27,7 +27,14 @@ properties:
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
gpio-reserved-ranges: true
gpio-reserved-ranges:
minItems: 1
maxItems: 105
gpio-line-names:
maxItems: 209
'#gpio-cells': true
gpio-ranges: true
wakeup-parent: true
......@@ -43,8 +50,9 @@ patternProperties:
oneOf:
- $ref: "#/$defs/qcom-sm8450-tlmm-state"
- patternProperties:
".*":
"-pins$":
$ref: "#/$defs/qcom-sm8450-tlmm-state"
additionalProperties: false
$defs:
qcom-sm8450-tlmm-state:
......@@ -52,7 +60,6 @@ $defs:
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
properties:
pins:
......@@ -104,40 +111,49 @@ $defs:
required:
- pins
- function
allOf:
- $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
- if:
properties:
pins:
pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
then:
required:
- function
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sm8450-tlmm";
reg = <0x0f100000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 211>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-wo-subnode-state {
pins = "gpio1";
function = "gpio";
};
uart-w-subnodes-state {
rx {
pins = "gpio26";
function = "qup7";
bias-pull-up;
};
tx {
pins = "gpio27";
function = "qup7";
bias-disable;
};
};
#include <dt-bindings/interrupt-controller/arm-gic.h>
pinctrl@f100000 {
compatible = "qcom,sm8450-tlmm";
reg = <0x0f100000 0x300000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 211>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
uart-w-state {
rx-pins {
pins = "gpio26";
function = "qup7";
bias-pull-up;
};
tx-pins {
pins = "gpio27";
function = "qup7";
bias-disable;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml
View file @ 979bb590
......@@ -41,6 +41,7 @@ required:
patternProperties:
"^gpio-[0-9]*$":
type: object
additionalProperties: false
description:
Each port of the r7s72100 pin controller hardware is itself a GPIO
......
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
View file @ 979bb590
......@@ -23,7 +23,7 @@ properties:
oneOf:
- items:
- enum:
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
- items:
......
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
View file @ 979bb590
......@@ -47,6 +47,7 @@ properties:
- rockchip,rk3568-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
- rockchip,rv1126-pinctrl
rockchip,grf:
$ref: "/schemas/types.yaml#/definitions/phandle"
......
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml
View file @ 979bb590
......@@ -20,7 +20,6 @@ description: |
The values used for config properties should be derived from the hardware
manual and these values are programmed as-is into the pin pull up/down and
driver strength register of the pin-controller.
See also include/dt-bindings/pinctrl/samsung.h with useful constants.
See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
additional information and example.
......
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
View file @ 979bb590
......@@ -15,9 +15,6 @@ description: |
This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
controller.
Pin group settings (like drive strength, pull up/down) are available as
macros in include/dt-bindings/pinctrl/samsung.h.
All the pin controller nodes should be represented in the aliases node using
the following format 'pinctrl{n}' where n is a unique number for the alias.
......@@ -97,6 +94,9 @@ patternProperties:
additionalProperties: false
"^(initial|sleep)-state$":
type: object
additionalProperties: false
patternProperties:
"^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$":
$ref: samsung,pinctrl-pins-cfg.yaml
......@@ -138,8 +138,6 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@7f008000 {
compatible = "samsung,s3c64xx-pinctrl";
reg = <0x7f008000 0x1000>;
......@@ -166,8 +164,8 @@ examples:
uart0-data-pins {
samsung,pins = "gpa-0", "gpa-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
};
// ...
......@@ -175,7 +173,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
......@@ -197,9 +194,9 @@ examples:
uart0-data-pins {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
// ...
......@@ -207,14 +204,14 @@ examples:
sleep0: sleep-state {
gpa0-0-pin {
samsung,pins = "gpa0-0";
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-con-pdn = <2>;
samsung,pin-pud-pdn = <0>;
};
gpa0-1-pin {
samsung,pins = "gpa0-1";
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>;
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-con-pdn = <0>;
samsung,pin-pud-pdn = <0>;
};
// ...
......@@ -223,7 +220,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
......@@ -272,26 +268,26 @@ examples:
sd0-clk-pins {
samsung,pins = "gpk0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd4-bus-width8-pins {
part-1-pins {
samsung,pins = "gpk0-3", "gpk0-4",
"gpk0-5", "gpk0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
part-2-pins {
samsung,pins = "gpk1-3", "gpk1-4",
"gpk1-5", "gpk1-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
};
......@@ -299,16 +295,15 @@ examples:
otg-gp-pins {
samsung,pins = "gpx3-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
samsung,pin-function = <1>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
samsung,pin-val = <0>;
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@10580000 {
compatible = "samsung,exynos5433-pinctrl";
......@@ -352,9 +347,9 @@ examples:
initial_alive: initial-state {
gpa0-0-pin {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
samsung,pin-function = <0>;
samsung,pin-pud = <1>;
samsung,pin-drv = <0>;
};
// ...
......@@ -363,7 +358,6 @@ examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@114b0000 {
compatible = "samsung,exynos5433-pinctrl";
......@@ -384,9 +378,9 @@ examples:
i2s0-bus-pins {
samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
"gpz0-4", "gpz0-5", "gpz0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
// ...
......
Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
View file @ 979bb590
......@@ -64,6 +64,9 @@ patternProperties:
gpio-controller: true
'#gpio-cells':
const: 2
interrupt-controller: true
'#interrupt-cells':
const: 2
reg:
maxItems: 1
......@@ -71,6 +74,7 @@ patternProperties:
maxItems: 1
resets:
maxItems: 1
gpio-line-names: true
gpio-ranges:
minItems: 1
maxItems: 16
......@@ -106,6 +110,12 @@ patternProperties:
minimum: 0
maximum: 11
patternProperties:
"^(.+-hog(-[0-9]+)?)$":
type: object
required:
- gpio-hog
required:
- gpio-controller
- '#gpio-cells'
......@@ -115,9 +125,12 @@ patternProperties:
'-[0-9]*$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl group available on the machine. Each subnode will list the
......
Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
View file @ 979bb590
......@@ -165,7 +165,7 @@ examples:
- |
#include <dt-bindings/clock/starfive-jh7100.h>
#include <dt-bindings/reset/starfive-jh7100.h>
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
soc {
#address-cells = <2>;
......
Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
View file @ 979bb590
......@@ -36,6 +36,7 @@ patternProperties:
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength.
$ref: "pinmux-node.yaml"
additionalProperties: false
properties:
function:
......
MAINTAINERS
View file @ 979bb590
......@@ -5665,6 +5665,12 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
T: git git://linuxtv.org/anttip/media_tree.git
F: drivers/media/common/cypress_firmware*
CYPRESS CY8C95X0 PINCTRL DRIVER
M: Patrick Rudolph <patrick.rudolph@9elements.com>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/pinctrl/pinctrl-cy8c95x0.c
CYPRESS CY8CTMA140 TOUCHSCREEN DRIVER
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-input@vger.kernel.org
......@@ -19606,8 +19612,8 @@ M: Emil Renner Berthing <kernel@esmil.dk>
L: linux-gpio@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
F: drivers/pinctrl/pinctrl-starfive.c
F: include/dt-bindings/pinctrl/pinctrl-starfive.h
F: drivers/pinctrl/starfive/
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
STARFIVE JH7100 RESET CONTROLLER DRIVER
M: Emil Renner Berthing <kernel@esmil.dk>
......
arch/arm/mach-at91/pm.c
View file @ 979bb590
......@@ -19,8 +19,6 @@
#include <linux/clk/at91_pmc.h>
#include <linux/platform_data/atmel.h>
#include <soc/at91/pm.h>
#include <asm/cacheflush.h>
#include <asm/fncpy.h>
#include <asm/system_misc.h>
......@@ -656,16 +654,6 @@ static int at91_pm_enter(suspend_state_t state)
if (ret)
return ret;
#ifdef CONFIG_PINCTRL_AT91
/*
* FIXME: this is needed to communicate between the pinctrl driver and
* the PM implementation in the machine. Possibly part of the PM
* implementation should be moved down into the pinctrl driver and get
* called as part of the generic suspend/resume path.
*/
at91_pinctrl_gpio_suspend();
#endif
switch (state) {
case PM_SUSPEND_MEM:
case PM_SUSPEND_STANDBY:
......@@ -690,9 +678,6 @@ static int at91_pm_enter(suspend_state_t state)
}
error:
#ifdef CONFIG_PINCTRL_AT91
at91_pinctrl_gpio_resume();
#endif
at91_pm_config_quirks(false);
return 0;
}
......
arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts
View file @ 979bb590
......@@ -8,7 +8,7 @@
#include "jh7100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
/ {
model = "BeagleV Starlight Beta";
......
drivers/gpio/gpio-rockchip.c
View file @ 979bb590
......@@ -19,6 +19,7 @@
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regmap.h>
......@@ -156,6 +157,12 @@ static int rockchip_gpio_set_direction(struct gpio_chip *chip,
unsigned long flags;
u32 data = input ? 0 : 1;
if (input)
pinctrl_gpio_direction_input(bank->pin_base + offset);
else
pinctrl_gpio_direction_output(bank->pin_base + offset);
raw_spin_lock_irqsave(&bank->slock, flags);
rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
raw_spin_unlock_irqrestore(&bank->slock, flags);
......
drivers/pinctrl/Kconfig
View file @ 979bb590
......@@ -135,6 +135,20 @@ config PINCTRL_BM1880
help
Pinctrl driver for Bitmain BM1880 SoC.
config PINCTRL_CY8C95X0
tristate "Cypress CY8C95X0 I2C pinctrl and GPIO driver"
depends on I2C
select GPIOLIB
select GPIOLIB_IRQCHIP
select PINMUX
select PINCONF
select GENERIC_PINCONF
select REGMAP_I2C
help
Support for 20/40/60 pin Cypress Cy8C95x0 pinctrl/gpio I2C expander.
This driver can also be built as a module. If so, the module will be
called pinctrl-cy8c95x0.
config PINCTRL_DA850_PUPD
tristate "TI DA850/OMAP-L138/AM18XX pull-up and pull-down groups"
depends on OF && (ARCH_DAVINCI_DA850 || COMPILE_TEST)
......@@ -324,6 +338,11 @@ config PINCTRL_OCELOT
select GENERIC_PINMUX_FUNCTIONS
select OF_GPIO
select REGMAP_MMIO
help
Support for the internal GPIO interfaces on Microsemi Ocelot and
Jaguar2 SoCs.
If conpiled as a module, the module name will be pinctrl-ocelot.
config PINCTRL_OXNAS
bool
......@@ -415,23 +434,6 @@ config PINCTRL_ST
select PINCONF
select GPIOLIB_IRQCHIP
config PINCTRL_STARFIVE
tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
depends on SOC_STARFIVE || COMPILE_TEST
depends on OF
default SOC_STARFIVE
select GENERIC_PINCTRL_GROUPS
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
select GPIOLIB
select GPIOLIB_IRQCHIP
select OF_GPIO
help
Say yes here to support pin control on the StarFive JH7100 SoC.
This also provides an interface to the GPIO pins not used by other
peripherals supporting inputs, outputs, configuring pull-up/pull-down
and interrupts on input changes.
config PINCTRL_STMFX
tristate "STMicroelectronics STMFX GPIO expander pinctrl driver"
depends on I2C
......@@ -529,6 +531,7 @@ source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/starfive/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunplus/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
......
drivers/pinctrl/Makefile
View file @ 979bb590
......@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
......@@ -43,7 +44,6 @@ obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
......@@ -70,6 +70,7 @@ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_SOC_STARFIVE) += starfive/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
obj-y += sunplus/
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
......
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View file @ 979bb590
......@@ -92,19 +92,10 @@ static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr)
{
int ret;
pr_debug("Disabling signal %s for %s\n", expr->signal,
expr->function);
ret = aspeed_sig_expr_eval(ctx, expr, true);
if (ret < 0)
return ret;
if (ret)
return aspeed_sig_expr_set(ctx, expr, false);
return 0;
return aspeed_sig_expr_set(ctx, expr, false);
}
/**
......
drivers/pinctrl/bcm/pinctrl-bcm6318.c
View file @ 979bb590
......@@ -27,12 +27,6 @@
#define BCM6318_PAD_REG 0x54
#define BCM6328_PAD_MASK GENMASK(3, 0)
struct bcm6318_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6318_function {
const char *name;
const char * const *groups;
......@@ -146,64 +140,57 @@ static unsigned gpio47_pins[] = { 47 };
static unsigned gpio48_pins[] = { 48 };
static unsigned gpio49_pins[] = { 49 };
#define BCM6318_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6318_pingroup bcm6318_groups[] = {
BCM6318_GROUP(gpio0),
BCM6318_GROUP(gpio1),
BCM6318_GROUP(gpio2),
BCM6318_GROUP(gpio3),
BCM6318_GROUP(gpio4),
BCM6318_GROUP(gpio5),
BCM6318_GROUP(gpio6),
BCM6318_GROUP(gpio7),
BCM6318_GROUP(gpio8),
BCM6318_GROUP(gpio9),
BCM6318_GROUP(gpio10),
BCM6318_GROUP(gpio11),
BCM6318_GROUP(gpio12),
BCM6318_GROUP(gpio13),
BCM6318_GROUP(gpio14),
BCM6318_GROUP(gpio15),
BCM6318_GROUP(gpio16),
BCM6318_GROUP(gpio17),
BCM6318_GROUP(gpio18),
BCM6318_GROUP(gpio19),
BCM6318_GROUP(gpio20),
BCM6318_GROUP(gpio21),
BCM6318_GROUP(gpio22),
BCM6318_GROUP(gpio23),
BCM6318_GROUP(gpio24),
BCM6318_GROUP(gpio25),
BCM6318_GROUP(gpio26),
BCM6318_GROUP(gpio27),
BCM6318_GROUP(gpio28),
BCM6318_GROUP(gpio29),
BCM6318_GROUP(gpio30),
BCM6318_GROUP(gpio31),
BCM6318_GROUP(gpio32),
BCM6318_GROUP(gpio33),
BCM6318_GROUP(gpio34),
BCM6318_GROUP(gpio35),
BCM6318_GROUP(gpio36),
BCM6318_GROUP(gpio37),
BCM6318_GROUP(gpio38),
BCM6318_GROUP(gpio39),
BCM6318_GROUP(gpio40),
BCM6318_GROUP(gpio41),
BCM6318_GROUP(gpio42),
BCM6318_GROUP(gpio43),
BCM6318_GROUP(gpio44),
BCM6318_GROUP(gpio45),
BCM6318_GROUP(gpio46),
BCM6318_GROUP(gpio47),
BCM6318_GROUP(gpio48),
BCM6318_GROUP(gpio49),
static struct pingroup bcm6318_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(gpio48),
BCM_PIN_GROUP(gpio49),
};
/* GPIO_MODE */
......@@ -368,10 +355,10 @@ static const char *bcm6318_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6318_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6318_groups[group].pins;
*num_pins = bcm6318_groups[group].num_pins;
*npins = bcm6318_groups[group].npins;
return 0;
}
......@@ -424,7 +411,7 @@ static int bcm6318_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6318_pingroup *pg = &bcm6318_groups[group];
const struct pingroup *pg = &bcm6318_groups[group];
const struct bcm6318_function *f = &bcm6318_funcs[selector];
bcm6318_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);
......
drivers/pinctrl/bcm/pinctrl-bcm63268.c
View file @ 979bb590
......@@ -40,12 +40,6 @@ enum bcm63268_pinctrl_reg {
BCM63268_BASEMODE,
};
struct bcm63268_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm63268_function {
const char *name;
const char * const *groups;
......@@ -185,74 +179,67 @@ static unsigned vdsl_phy1_grp_pins[] = { 12, 13 };
static unsigned vdsl_phy2_grp_pins[] = { 24, 25 };
static unsigned vdsl_phy3_grp_pins[] = { 26, 27 };
#define BCM63268_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm63268_pingroup bcm63268_groups[] = {
BCM63268_GROUP(gpio0),
BCM63268_GROUP(gpio1),
BCM63268_GROUP(gpio2),
BCM63268_GROUP(gpio3),
BCM63268_GROUP(gpio4),
BCM63268_GROUP(gpio5),
BCM63268_GROUP(gpio6),
BCM63268_GROUP(gpio7),
BCM63268_GROUP(gpio8),
BCM63268_GROUP(gpio9),
BCM63268_GROUP(gpio10),
BCM63268_GROUP(gpio11),
BCM63268_GROUP(gpio12),
BCM63268_GROUP(gpio13),
BCM63268_GROUP(gpio14),
BCM63268_GROUP(gpio15),
BCM63268_GROUP(gpio16),
BCM63268_GROUP(gpio17),
BCM63268_GROUP(gpio18),
BCM63268_GROUP(gpio19),
BCM63268_GROUP(gpio20),
BCM63268_GROUP(gpio21),
BCM63268_GROUP(gpio22),
BCM63268_GROUP(gpio23),
BCM63268_GROUP(gpio24),
BCM63268_GROUP(gpio25),
BCM63268_GROUP(gpio26),
BCM63268_GROUP(gpio27),
BCM63268_GROUP(gpio28),
BCM63268_GROUP(gpio29),
BCM63268_GROUP(gpio30),
BCM63268_GROUP(gpio31),
BCM63268_GROUP(gpio32),
BCM63268_GROUP(gpio33),
BCM63268_GROUP(gpio34),
BCM63268_GROUP(gpio35),
BCM63268_GROUP(gpio36),
BCM63268_GROUP(gpio37),
BCM63268_GROUP(gpio38),
BCM63268_GROUP(gpio39),
BCM63268_GROUP(gpio40),
BCM63268_GROUP(gpio41),
BCM63268_GROUP(gpio42),
BCM63268_GROUP(gpio43),
BCM63268_GROUP(gpio44),
BCM63268_GROUP(gpio45),
BCM63268_GROUP(gpio46),
BCM63268_GROUP(gpio47),
BCM63268_GROUP(gpio48),
BCM63268_GROUP(gpio49),
BCM63268_GROUP(gpio50),
BCM63268_GROUP(gpio51),
static struct pingroup bcm63268_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(gpio48),
BCM_PIN_GROUP(gpio49),
BCM_PIN_GROUP(gpio50),
BCM_PIN_GROUP(gpio51),
/* multi pin groups */
BCM63268_GROUP(nand_grp),
BCM63268_GROUP(dectpd_grp),
BCM63268_GROUP(vdsl_phy0_grp),
BCM63268_GROUP(vdsl_phy1_grp),
BCM63268_GROUP(vdsl_phy2_grp),
BCM63268_GROUP(vdsl_phy3_grp),
BCM_PIN_GROUP(nand_grp),
BCM_PIN_GROUP(dectpd_grp),
BCM_PIN_GROUP(vdsl_phy0_grp),
BCM_PIN_GROUP(vdsl_phy1_grp),
BCM_PIN_GROUP(vdsl_phy2_grp),
BCM_PIN_GROUP(vdsl_phy3_grp),
};
static const char * const led_groups[] = {
......@@ -487,10 +474,10 @@ static const char *bcm63268_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm63268_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group,
const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm63268_groups[group].pins;
*num_pins = bcm63268_groups[group].num_pins;
*npins = bcm63268_groups[group].npins;
return 0;
}
......@@ -545,13 +532,13 @@ static int bcm63268_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm63268_pingroup *pg = &bcm63268_groups[group];
const struct pingroup *pg = &bcm63268_groups[group];
const struct bcm63268_function *f = &bcm63268_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->num_pins; i++)
for (i = 0; i < pg->npins; i++)
bcm63268_set_gpio(pc, pg->pins[i]);
switch (f->reg) {
......
drivers/pinctrl/bcm/pinctrl-bcm6328.c
View file @ 979bb590
......@@ -26,12 +26,6 @@
#define BCM6328_MUX_OTHER_REG 0x24
#define BCM6328_MUX_MASK GENMASK(1, 0)
struct bcm6328_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6328_function {
const char *name;
const char * const *groups;
......@@ -125,49 +119,42 @@ static unsigned gpio31_pins[] = { 31 };
static unsigned hsspi_cs1_pins[] = { 36 };
static unsigned usb_port1_pins[] = { 38 };
#define BCM6328_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6328_pingroup bcm6328_groups[] = {
BCM6328_GROUP(gpio0),
BCM6328_GROUP(gpio1),
BCM6328_GROUP(gpio2),
BCM6328_GROUP(gpio3),
BCM6328_GROUP(gpio4),
BCM6328_GROUP(gpio5),
BCM6328_GROUP(gpio6),
BCM6328_GROUP(gpio7),
BCM6328_GROUP(gpio8),
BCM6328_GROUP(gpio9),
BCM6328_GROUP(gpio10),
BCM6328_GROUP(gpio11),
BCM6328_GROUP(gpio12),
BCM6328_GROUP(gpio13),
BCM6328_GROUP(gpio14),
BCM6328_GROUP(gpio15),
BCM6328_GROUP(gpio16),
BCM6328_GROUP(gpio17),
BCM6328_GROUP(gpio18),
BCM6328_GROUP(gpio19),
BCM6328_GROUP(gpio20),
BCM6328_GROUP(gpio21),
BCM6328_GROUP(gpio22),
BCM6328_GROUP(gpio23),
BCM6328_GROUP(gpio24),
BCM6328_GROUP(gpio25),
BCM6328_GROUP(gpio26),
BCM6328_GROUP(gpio27),
BCM6328_GROUP(gpio28),
BCM6328_GROUP(gpio29),
BCM6328_GROUP(gpio30),
BCM6328_GROUP(gpio31),
BCM6328_GROUP(hsspi_cs1),
BCM6328_GROUP(usb_port1),
static struct pingroup bcm6328_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(hsspi_cs1),
BCM_PIN_GROUP(usb_port1),
};
/* GPIO_MODE */
......@@ -292,10 +279,10 @@ static const char *bcm6328_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6328_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6328_groups[group].pins;
*num_pins = bcm6328_groups[group].num_pins;
*npins = bcm6328_groups[group].npins;
return 0;
}
......@@ -338,7 +325,7 @@ static int bcm6328_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6328_pingroup *pg = &bcm6328_groups[group];
const struct pingroup *pg = &bcm6328_groups[group];
const struct bcm6328_function *f = &bcm6328_funcs[selector];
bcm6328_rmw_mux(pc, pg->pins[0], f->mode_val, f->mux_val);
......
drivers/pinctrl/bcm/pinctrl-bcm6358.c
View file @ 979bb590
......@@ -35,9 +35,7 @@
#define BCM6358_MODE_MUX_SYS_IRQ BIT(15)
struct bcm6358_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
struct pingroup grp;
const uint16_t mode_val;
......@@ -131,9 +129,7 @@ static unsigned sys_irq_grp_pins[] = { 5 };
#define BCM6358_GPIO_MUX_GROUP(n, bit, dir) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
.grp = BCM_PIN_GROUP(n), \
.mode_val = BCM6358_MODE_MUX_##bit, \
.direction = dir, \
}
......@@ -219,15 +215,15 @@ static int bcm6358_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
static const char *bcm6358_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned group)
{
return bcm6358_groups[group].name;
return bcm6358_groups[group].grp.name;
}
static int bcm6358_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6358_groups[group].pins;
*num_pins = bcm6358_groups[group].num_pins;
*pins = bcm6358_groups[group].grp.pins;
*npins = bcm6358_groups[group].grp.npins;
return 0;
}
......@@ -264,12 +260,12 @@ static int bcm6358_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int mask = val;
unsigned pin;
for (pin = 0; pin < pg->num_pins; pin++)
for (pin = 0; pin < pg->grp.npins; pin++)
mask |= (unsigned long)bcm6358_pins[pin].drv_data;
regmap_field_update_bits(priv->overlays, mask, val);
for (pin = 0; pin < pg->num_pins; pin++) {
for (pin = 0; pin < pg->grp.npins; pin++) {
struct pinctrl_gpio_range *range;
unsigned int hw_gpio = bcm6358_pins[pin].number;
......
drivers/pinctrl/bcm/pinctrl-bcm6362.c
View file @ 979bb590
......@@ -35,12 +35,6 @@ enum bcm6362_pinctrl_reg {
BCM6362_BASEMODE,
};
struct bcm6362_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6362_function {
const char *name;
const char * const *groups;
......@@ -162,63 +156,56 @@ static unsigned nand_grp_pins[] = {
18, 19, 20, 21, 22, 23, 27,
};
#define BCM6362_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6362_pingroup bcm6362_groups[] = {
BCM6362_GROUP(gpio0),
BCM6362_GROUP(gpio1),
BCM6362_GROUP(gpio2),
BCM6362_GROUP(gpio3),
BCM6362_GROUP(gpio4),
BCM6362_GROUP(gpio5),
BCM6362_GROUP(gpio6),
BCM6362_GROUP(gpio7),
BCM6362_GROUP(gpio8),
BCM6362_GROUP(gpio9),
BCM6362_GROUP(gpio10),
BCM6362_GROUP(gpio11),
BCM6362_GROUP(gpio12),
BCM6362_GROUP(gpio13),
BCM6362_GROUP(gpio14),
BCM6362_GROUP(gpio15),
BCM6362_GROUP(gpio16),
BCM6362_GROUP(gpio17),
BCM6362_GROUP(gpio18),
BCM6362_GROUP(gpio19),
BCM6362_GROUP(gpio20),
BCM6362_GROUP(gpio21),
BCM6362_GROUP(gpio22),
BCM6362_GROUP(gpio23),
BCM6362_GROUP(gpio24),
BCM6362_GROUP(gpio25),
BCM6362_GROUP(gpio26),
BCM6362_GROUP(gpio27),
BCM6362_GROUP(gpio28),
BCM6362_GROUP(gpio29),
BCM6362_GROUP(gpio30),
BCM6362_GROUP(gpio31),
BCM6362_GROUP(gpio32),
BCM6362_GROUP(gpio33),
BCM6362_GROUP(gpio34),
BCM6362_GROUP(gpio35),
BCM6362_GROUP(gpio36),
BCM6362_GROUP(gpio37),
BCM6362_GROUP(gpio38),
BCM6362_GROUP(gpio39),
BCM6362_GROUP(gpio40),
BCM6362_GROUP(gpio41),
BCM6362_GROUP(gpio42),
BCM6362_GROUP(gpio43),
BCM6362_GROUP(gpio44),
BCM6362_GROUP(gpio45),
BCM6362_GROUP(gpio46),
BCM6362_GROUP(gpio47),
BCM6362_GROUP(nand_grp),
static struct pingroup bcm6362_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(gpio32),
BCM_PIN_GROUP(gpio33),
BCM_PIN_GROUP(gpio34),
BCM_PIN_GROUP(gpio35),
BCM_PIN_GROUP(gpio36),
BCM_PIN_GROUP(gpio37),
BCM_PIN_GROUP(gpio38),
BCM_PIN_GROUP(gpio39),
BCM_PIN_GROUP(gpio40),
BCM_PIN_GROUP(gpio41),
BCM_PIN_GROUP(gpio42),
BCM_PIN_GROUP(gpio43),
BCM_PIN_GROUP(gpio44),
BCM_PIN_GROUP(gpio45),
BCM_PIN_GROUP(gpio46),
BCM_PIN_GROUP(gpio47),
BCM_PIN_GROUP(nand_grp),
};
static const char * const led_groups[] = {
......@@ -463,10 +450,10 @@ static const char *bcm6362_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6362_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6362_groups[group].pins;
*num_pins = bcm6362_groups[group].num_pins;
*npins = bcm6362_groups[group].npins;
return 0;
}
......@@ -519,13 +506,13 @@ static int bcm6362_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned selector, unsigned group)
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
const struct bcm6362_pingroup *pg = &bcm6362_groups[group];
const struct pingroup *pg = &bcm6362_groups[group];
const struct bcm6362_function *f = &bcm6362_funcs[selector];
unsigned i;
unsigned int reg;
unsigned int val, mask;
for (i = 0; i < pg->num_pins; i++)
for (i = 0; i < pg->npins; i++)
bcm6362_set_gpio(pc, pg->pins[i]);
switch (f->reg) {
......
drivers/pinctrl/bcm/pinctrl-bcm6368.c
View file @ 979bb590
......@@ -26,12 +26,6 @@
#define BCM6368_BASEMODE_GPIO 0x0
#define BCM6368_BASEMODE_UART1 0x1
struct bcm6368_pingroup {
const char *name;
const unsigned * const pins;
const unsigned num_pins;
};
struct bcm6368_function {
const char *name;
const char * const *groups;
......@@ -127,47 +121,40 @@ static unsigned gpio30_pins[] = { 30 };
static unsigned gpio31_pins[] = { 31 };
static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
#define BCM6368_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.num_pins = ARRAY_SIZE(n##_pins), \
}
static struct bcm6368_pingroup bcm6368_groups[] = {
BCM6368_GROUP(gpio0),
BCM6368_GROUP(gpio1),
BCM6368_GROUP(gpio2),
BCM6368_GROUP(gpio3),
BCM6368_GROUP(gpio4),
BCM6368_GROUP(gpio5),
BCM6368_GROUP(gpio6),
BCM6368_GROUP(gpio7),
BCM6368_GROUP(gpio8),
BCM6368_GROUP(gpio9),
BCM6368_GROUP(gpio10),
BCM6368_GROUP(gpio11),
BCM6368_GROUP(gpio12),
BCM6368_GROUP(gpio13),
BCM6368_GROUP(gpio14),
BCM6368_GROUP(gpio15),
BCM6368_GROUP(gpio16),
BCM6368_GROUP(gpio17),
BCM6368_GROUP(gpio18),
BCM6368_GROUP(gpio19),
BCM6368_GROUP(gpio20),
BCM6368_GROUP(gpio21),
BCM6368_GROUP(gpio22),
BCM6368_GROUP(gpio23),
BCM6368_GROUP(gpio24),
BCM6368_GROUP(gpio25),
BCM6368_GROUP(gpio26),
BCM6368_GROUP(gpio27),
BCM6368_GROUP(gpio28),
BCM6368_GROUP(gpio29),
BCM6368_GROUP(gpio30),
BCM6368_GROUP(gpio31),
BCM6368_GROUP(uart1_grp),
static struct pingroup bcm6368_groups[] = {
BCM_PIN_GROUP(gpio0),
BCM_PIN_GROUP(gpio1),
BCM_PIN_GROUP(gpio2),
BCM_PIN_GROUP(gpio3),
BCM_PIN_GROUP(gpio4),
BCM_PIN_GROUP(gpio5),
BCM_PIN_GROUP(gpio6),
BCM_PIN_GROUP(gpio7),
BCM_PIN_GROUP(gpio8),
BCM_PIN_GROUP(gpio9),
BCM_PIN_GROUP(gpio10),
BCM_PIN_GROUP(gpio11),
BCM_PIN_GROUP(gpio12),
BCM_PIN_GROUP(gpio13),
BCM_PIN_GROUP(gpio14),
BCM_PIN_GROUP(gpio15),
BCM_PIN_GROUP(gpio16),
BCM_PIN_GROUP(gpio17),
BCM_PIN_GROUP(gpio18),
BCM_PIN_GROUP(gpio19),
BCM_PIN_GROUP(gpio20),
BCM_PIN_GROUP(gpio21),
BCM_PIN_GROUP(gpio22),
BCM_PIN_GROUP(gpio23),
BCM_PIN_GROUP(gpio24),
BCM_PIN_GROUP(gpio25),
BCM_PIN_GROUP(gpio26),
BCM_PIN_GROUP(gpio27),
BCM_PIN_GROUP(gpio28),
BCM_PIN_GROUP(gpio29),
BCM_PIN_GROUP(gpio30),
BCM_PIN_GROUP(gpio31),
BCM_PIN_GROUP(uart1_grp),
};
static const char * const analog_afe_0_groups[] = {
......@@ -358,10 +345,10 @@ static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned group, const unsigned **pins,
unsigned *num_pins)
unsigned *npins)
{
*pins = bcm6368_groups[group].pins;
*num_pins = bcm6368_groups[group].num_pins;
*npins = bcm6368_groups[group].npins;
return 0;
}
......@@ -393,14 +380,14 @@ static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
{
struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
struct bcm6368_priv *priv = pc->driver_data;
const struct bcm6368_pingroup *pg = &bcm6368_groups[group];
const struct pingroup *pg = &bcm6368_groups[group];
const struct bcm6368_function *fun = &bcm6368_funcs[selector];
int i, pin;
if (fun->basemode) {
unsigned int mask = 0;
for (i = 0; i < pg->num_pins; i++) {
for (i = 0; i < pg->npins; i++) {
pin = pg->pins[i];
if (pin < BCM63XX_BANK_GPIOS)
mask |= BIT(pin);
......@@ -419,7 +406,7 @@ static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
BIT(pin));
}
for (pin = 0; pin < pg->num_pins; pin++) {
for (pin = 0; pin < pg->npins; pin++) {
struct pinctrl_gpio_range *range;
int hw_gpio = bcm6368_pins[pin].number;
......
drivers/pinctrl/bcm/pinctrl-bcm63xx.h
View file @ 979bb590
......@@ -21,6 +21,8 @@ struct bcm63xx_pinctrl_soc {
unsigned int ngpios;
};
#define BCM_PIN_GROUP(n) PINCTRL_PINGROUP(#n, n##_pins, ARRAY_SIZE(n##_pins))
struct bcm63xx_pinctrl {
struct device *dev;
struct regmap *regs;
......
drivers/pinctrl/bcm/pinctrl-ns.c
View file @ 979bb590
......@@ -233,10 +233,8 @@ static int ns_pinctrl_probe(struct platform_device *pdev)
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"cru_gpio_control");
ns_pinctrl->base = devm_ioremap_resource(dev, res);
if (IS_ERR(ns_pinctrl->base)) {
dev_err(dev, "Failed to map pinctrl regs\n");
if (IS_ERR(ns_pinctrl->base))
return PTR_ERR(ns_pinctrl->base);
}
memcpy(pctldesc, &ns_pinctrl_desc, sizeof(*pctldesc));
......
drivers/pinctrl/berlin/berlin.c
View file @ 979bb590
......@@ -209,7 +209,7 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev)
for (i = 0; i < pctrl->desc->ngroups; i++) {
desc_group = pctrl->desc->groups + i;
/* compute the maxiumum number of functions a group can have */
/* compute the maximum number of functions a group can have */
max_functions += 1 << (desc_group->bit_width + 1);
}
......
drivers/pinctrl/freescale/Kconfig
View file @ 979bb590
......@@ -119,28 +119,32 @@ config PINCTRL_IMX7ULP
config PINCTRL_IMX8MM
tristate "IMX8MM pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mm pinctrl driver
config PINCTRL_IMX8MN
tristate "IMX8MN pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mn pinctrl driver
config PINCTRL_IMX8MP
tristate "IMX8MP pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mp pinctrl driver
config PINCTRL_IMX8MQ
tristate "IMX8MQ pinctrl driver"
depends on ARCH_MXC
depends on OF
depends on SOC_IMX8M
select PINCTRL_IMX
help
Say Y here to enable the imx8mq pinctrl driver
......
drivers/pinctrl/mediatek/Kconfig
View file @ 979bb590
......@@ -162,6 +162,18 @@ config PINCTRL_MT8186
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
config PINCTRL_MT8188
bool "MediaTek MT8188 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_PARIS
help
Say yes here to support pin controller and gpio driver
on MediaTek MT8188 SoC.
In MTK platform, we support virtual gpio and use it to
map specific eint which doesn't have real gpio pin.
config PINCTRL_MT8192
bool "Mediatek MT8192 pin control"
depends on OF
......
drivers/pinctrl/mediatek/Makefile
View file @ 979bb590
......@@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
......
drivers/pinctrl/mediatek/pinctrl-mt8188.c 0 → 100644
View file @ 979bb590
This diff is collapsed.
drivers/pinctrl/mediatek/pinctrl-mtk-mt8188.h 0 → 100644
View file @ 979bb590
This diff is collapsed.
drivers/pinctrl/meson/pinctrl-meson.c
View file @ 979bb590
......@@ -608,6 +608,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc)
pc->chip.label = pc->data->name;
pc->chip.parent = pc->dev;
pc->chip.fwnode = pc->fwnode;
pc->chip.request = gpiochip_generic_request;
pc->chip.free = gpiochip_generic_free;
pc->chip.set_config = gpiochip_generic_config;
......@@ -619,8 +620,6 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc)
pc->chip.base = -1;
pc->chip.ngpio = pc->data->num_pins;
pc->chip.can_sleep = false;
pc->chip.of_node = pc->of_node;
pc->chip.of_gpio_n_cells = 2;
ret = gpiochip_add_data(&pc->chip, pc);
if (ret) {
......@@ -678,8 +677,8 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc)
return -EINVAL;
}
gpio_np = to_of_node(gpiochip_node_get_first(pc->dev));
pc->of_node = gpio_np;
pc->fwnode = gpiochip_node_get_first(pc->dev);
gpio_np = to_of_node(pc->fwnode);
pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
if (IS_ERR_OR_NULL(pc->reg_mux)) {
......
drivers/pinctrl/meson/pinctrl-meson.h
View file @ 979bb590
......@@ -12,6 +12,8 @@
#include <linux/types.h>
#include <linux/module.h>
struct fwnode_handle;
struct meson_pinctrl;
/**
......@@ -131,7 +133,7 @@ struct meson_pinctrl {
struct regmap *reg_gpio;
struct regmap *reg_ds;
struct gpio_chip chip;
struct device_node *of_node;
struct fwnode_handle *fwnode;
};
#define FUNCTION(fn) \
......
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View file @ 979bb590
......@@ -112,14 +112,14 @@ struct armada_37xx_pinctrl {
struct armada_37xx_pm_state pm;
};
#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
#define PIN_GRP_GPIO_0(_name, _start, _nr) \
{ \
.name = _name, \
.start_pin = _start, \
.npins = _nr, \
.reg_mask = _mask, \
.val = {0, _mask}, \
.funcs = {_func1, _func2} \
.reg_mask = 0, \
.val = {0}, \
.funcs = {"gpio"} \
}
#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
......@@ -179,6 +179,7 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
"pwm", "led"),
PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
PIN_GRP_GPIO_0("gpio1_5", 5, 1),
PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
......@@ -195,15 +196,18 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
PIN_GRP_GPIO_0("gpio2_2", 2, 1),
PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"),
PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12),
"ptp", "mii"),
PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13),
"ptp", "mii"),
PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
"mii", "mii_err"),
};
......@@ -486,11 +490,15 @@ static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct armada_37xx_pin_group *group;
int grp = 0;
int ret;
dev_dbg(info->dev, "requesting gpio %d\n", offset);
while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) {
ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
if (ret)
return ret;
}
return 0;
}
......
drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
View file @ 979bb590
......@@ -303,23 +303,20 @@ static const unsigned usbhs_c_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20,
STN8815_PIN_C16, STN8815_PIN_A15,
STN8815_PIN_D17, STN8815_PIN_C17 };
#define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
static const struct nmk_pingroup nmk_stn8815_groups[] = {
STN8815_PIN_GROUP(u0txrx_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u0ctsrts_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u0modem_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(mmcsd_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(usbfs_b_1, NMK_GPIO_ALT_B),
STN8815_PIN_GROUP(usbhs_c_1, NMK_GPIO_ALT_C),
NMK_PIN_GROUP(u0txrx_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u0ctsrts_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u0modem_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(mmcsd_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
NMK_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(usbfs_b_1, NMK_GPIO_ALT_B),
NMK_PIN_GROUP(usbhs_c_1, NMK_GPIO_ALT_C),
};
/* We use this macro to define the groups applicable to a function */
......
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View file @ 979bb590
This diff is collapsed.
drivers/pinctrl/nomadik/pinctrl-nomadik.h
View file @ 979bb590
......@@ -5,7 +5,6 @@
/* Package definitions */
#define PINCTRL_NMK_STN8815 0
#define PINCTRL_NMK_DB8500 1
#define PINCTRL_NMK_DB8540 2
/* Alternate functions: function C is set in hw by setting both A and B */
#define NMK_GPIO_ALT_GPIO 0
......@@ -105,21 +104,21 @@ struct nmk_function {
/**
* struct nmk_pingroup - describes a Nomadik pin group
* @name: the name of this specific pin group
* @pins: an array of discrete physical pins used in this group, taken
* from the driver-local pin enumeration space
* @num_pins: the number of pins in this group array, i.e. the number of
* elements in .pins so we can iterate over that array
* @grp: Generic data of the pin group (name and pins)
* @altsetting: the altsetting to apply to all pins in this group to
* configure them to be used by a function
*/
struct nmk_pingroup {
const char *name;
const unsigned int *pins;
const unsigned npins;
struct pingroup grp;
int altsetting;
};
#define NMK_PIN_GROUP(a, b) \
{ \
.grp = PINCTRL_PINGROUP(#a, a##_pins, ARRAY_SIZE(a##_pins)), \
.altsetting = b, \
}
/**
* struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
* @pins: An array describing all pins the pin controller affects.
......@@ -173,17 +172,4 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
#endif
#ifdef CONFIG_PINCTRL_DB8540
void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
#else
static inline void
nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
{
}
#endif
#endif /* PINCTRL_PINCTRL_NOMADIK_H */
drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
View file @ 979bb590
......@@ -81,11 +81,11 @@ struct npcm7xx_gpio {
int irq;
struct irq_chip irq_chip;
u32 pinctrl_id;
int (*direction_input)(struct gpio_chip *chip, unsigned offset);
int (*direction_output)(struct gpio_chip *chip, unsigned offset,
int (*direction_input)(struct gpio_chip *chip, unsigned int offset);
int (*direction_output)(struct gpio_chip *chip, unsigned int offset,
int value);
int (*request)(struct gpio_chip *chip, unsigned offset);
void (*free)(struct gpio_chip *chip, unsigned offset);
int (*request)(struct gpio_chip *chip, unsigned int offset);
void (*free)(struct gpio_chip *chip, unsigned int offset);
};
struct npcm7xx_pinctrl {
......
drivers/pinctrl/nuvoton/pinctrl-wpcm450.c
View file @ 979bb590
......@@ -1081,10 +1081,13 @@ static int wpcm450_gpio_register(struct platform_device *pdev,
girq->num_parents = 0;
for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) {
int irq = fwnode_irq_get(child, i);
int irq;
irq = fwnode_irq_get(child, i);
if (irq < 0)
break;
if (!irq)
continue;
girq->parents[i] = irq;
girq->num_parents++;
......
drivers/pinctrl/pinctrl-amd.c
View file @ 979bb590
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drivers/pinctrl/pinctrl-at91.c
View file @ 979bb590
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drivers/pinctrl/pinctrl-cy8c95x0.c 0 → 100644
View file @ 979bb590
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drivers/pinctrl/pinctrl-ingenic.c
View file @ 979bb590
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drivers/pinctrl/pinctrl-mcp23s08.c
View file @ 979bb590
......@@ -549,9 +549,6 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
mcp->chip.get = mcp23s08_get;
mcp->chip.direction_output = mcp23s08_direction_output;
mcp->chip.set = mcp23s08_set;
#ifdef CONFIG_OF_GPIO
mcp->chip.of_gpio_n_cells = 2;
#endif
mcp->chip.base = base;
mcp->chip.can_sleep = true;
......
drivers/pinctrl/pinctrl-microchip-sgpio.c
View file @ 979bb590
......@@ -865,9 +865,10 @@ static int microchip_sgpio_register_bank(struct device *dev,
gc->can_sleep = !bank->is_input;
if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
int irq = fwnode_irq_get(fwnode, 0);
int irq;
if (irq) {
irq = fwnode_irq_get(fwnode, 0);
if (irq > 0) {
struct gpio_irq_chip *girq = &gc->irq;
gpio_irq_chip_set_chip(girq, &microchip_sgpio_irqchip);
......
drivers/pinctrl/pinctrl-ocelot.c
View file @ 979bb590
......@@ -2129,4 +2129,6 @@ static struct platform_driver ocelot_pinctrl_driver = {
.remove = ocelot_pinctrl_remove,
};
module_platform_driver(ocelot_pinctrl_driver);
MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver");
MODULE_LICENSE("Dual MIT/GPL");
drivers/pinctrl/pinctrl-pistachio.c
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drivers/pinctrl/pinctrl-rockchip.c
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drivers/pinctrl/pinctrl-rockchip.h
View file @ 979bb590
......@@ -186,6 +186,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1108,
RV1126,
RK2928,
RK3066B,
RK3128,
......
drivers/pinctrl/pinctrl-st.c
View file @ 979bb590
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drivers/pinctrl/qcom/Kconfig
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drivers/pinctrl/qcom/Makefile
View file @ 979bb590
......@@ -45,4 +45,6 @@ obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o
obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o
obj-$(CONFIG_PINCTRL_SM8450) += pinctrl-sm8450.o
obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o
obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c 0 → 100644
View file @ 979bb590
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drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c 0 → 100644
View file @ 979bb590
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drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View file @ 979bb590
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drivers/pinctrl/samsung/pinctrl-samsung.c
View file @ 979bb590
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drivers/pinctrl/starfive/Kconfig 0 → 100644
View file @ 979bb590
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drivers/pinctrl/starfive/Makefile 0 → 100644
View file @ 979bb590
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
drivers/pinctrl/stm32/pinctrl-stm32.c
View file @ 979bb590
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drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
View file @ 979bb590
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include/dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h 0 → 100644
View file @ 979bb590
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include/dt-bindings/pinctrl/samsung.h
View file @ 979bb590
This diff is collapsed.
include/soc/at91/pm.h deleted 100644 → 0
View file @ 694b37a5
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