[PATCH] sn: A little re-formatting

From: Pat Gefre <pfg@sgi.com>

A little re-formatting
Added pcibr_lock()

include/asm-ia64/sn/pci/pcibr_private.h

@@ -93,7 +93,7 @@ extern uint32_t pcibr_debug_mask;
  * set, then the overhead for this macro is just an extra 'if' check.
  */
 /* For high frequency events (ie. map allocation, direct translation,...) */
-#if 1 || DEBUG
+#if DEBUG
 #define PCIBR_DEBUG(args) PCIBR_DEBUG_ALWAYS(args)
 #else	/* DEBUG */
 #define PCIBR_DEBUG(args)
@@ -166,8 +166,8 @@ struct pcibr_intr_s {
 #define	bi_flags	bi_pi.pi_flags	/* PCIBR_INTR flags */
 #define	bi_dev		bi_pi.pi_dev	/* associated pci card */
 #define	bi_lines	bi_pi.pi_lines	/* which PCI interrupt line(s) */
-#define bi_func		bi_pi.pi_func	/* handler function (when connected) */
-#define bi_arg		bi_pi.pi_arg	/* handler parameter (when connected) */
+#define	bi_func		bi_pi.pi_func	/* handler function (when connected) */
+#define	bi_arg		bi_pi.pi_arg	/* handler parameter (when connected) */
 #define bi_mustruncpu	bi_pi.pi_mustruncpu /* Where we must run. */
 #define bi_irq		bi_pi.pi_irq	/* IRQ assigned. */
 #define bi_cpu		bi_pi.pi_cpu	/* cpu assigned. */
@@ -224,11 +224,11 @@ struct pcibr_info_s {
 #define	f_pops		f_c.c_pops	/* cached provider from c_master */
 #define	f_efunc		f_c.c_efunc	/* error handling function */
 #define	f_einfo		f_c.c_einfo	/* first parameter for efunc */
-#define f_window        f_c.c_window    /* state of BASE regs */
+#define	f_window	f_c.c_window	/* state of BASE regs */
 #define	f_rwindow	f_c.c_rwindow	/* expansion ROM BASE regs */
 #define	f_rbase		f_c.c_rbase	/* expansion ROM base */
 #define	f_rsize		f_c.c_rsize	/* expansion ROM size */
-#define f_piospace      f_c.c_piospace  /* additional I/O spaces allocated */
+#define	f_piospace	f_c.c_piospace	/* additional I/O spaces allocated */
 
     /* pcibr-specific connection state */
     int			    f_ibit[4];	/* Bridge bit for each INTx */
@@ -296,7 +296,8 @@ struct pcibr_intr_wrap_s {
 	((1 << XWIDGET_PART_REV_NUM_REV(pcibr_soft->bs_rev_num)) & pv)
 /*
  * Defines for individual WARs. Each is a bitmask of applicable
- * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B, etc.
+ * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
+ * (3 << 1) == (rev A or rev B), etc
  */
 #define PV854697 (~0)     /* PIC: write 64bit regs as 64bits. permanent */
 #define PV854827 (~0)     /* PIC: fake widget 0xf presence bit. permanent */
@@ -370,13 +371,15 @@ struct pcibr_soft_s {
     short		    bs_int_ate_size;	/* number of internal ates */
     short		    bs_bridge_type;	/* see defines above */
     short		    bs_bridge_mode;	/* see defines above */
-    int                     bs_rev_num;		/* revision number of Bridge */
+
+    int                     bs_rev_num;	/* revision number of Bridge */
 
     /* bs_dma_flags are the forced dma flags used on all DMAs. Used for
      * working around ASIC rev issues and protocol specific requirements
      */
     unsigned                bs_dma_flags;	/* forced DMA flags */
 
+    nasid_t		    bs_nasid;		/* nasid this bus is on */
     moduleid_t		    bs_moduleid;	/* io brick moduleid */
     short		    bs_bricktype;	/* io brick type */
 
@@ -520,9 +523,9 @@ struct pcibr_soft_s {
      *  time for the indexed slot/vchan number; array[slot][vchan]
      */
     int                     bs_rrb_fixed;
-    int                     bs_rrb_avail[2];
-    int                     bs_rrb_res[8];
-    int                     bs_rrb_res_dflt[8];
+    int			    bs_rrb_avail[2];
+    int			    bs_rrb_res[8];
+    int			    bs_rrb_res_dflt[8];
     int			    bs_rrb_valid[8][4];
     int			    bs_rrb_valid_dflt[8][4];
     struct {
@@ -535,6 +538,10 @@ struct pcibr_soft_s {
 	 * Bridge interrupt bit.
 	 */
 	struct pcibr_intr_wrap_s  bsi_pcibr_intr_wrap;
+	/* The bus and interrupt bit, used for pcibr_setpciint().
+	 * The pci busnum is bit3, int_bits bit2:0
+	 */
+	uint32_t		bsi_int_bit;
 
     } bs_intr[8];
 
@@ -562,9 +569,6 @@ struct pcibr_soft_s {
      */
     struct br_errintr_info {
 	int                     bserr_toutcnt;
-#ifdef LATER
-	toid_t                  bserr_toutid;	/* Timeout started by errintr */
-#endif	/* LATER */
 	iopaddr_t               bserr_addr;	/* Address where error occured */
 	uint64_t		bserr_intstat;	/* interrupts active at error dump */
     } bs_errinfo;
@@ -600,9 +604,9 @@ struct pcibr_soft_s {
 #define PCIBR_BUS_ADDR_IO_FREED        2  /* Reserved PROM I/O addr freed */
 
     struct bs_errintr_stat_s {
-	uint32_t              bs_errcount_total;
-	uint32_t              bs_lasterr_timestamp;
-	uint32_t              bs_lasterr_snapshot;
+	uint32_t		bs_errcount_total;
+	uint32_t		bs_lasterr_timestamp;
+	uint32_t		bs_lasterr_snapshot;
     } bs_errintr_stat[PCIBR_ISR_MAX_ERRS];
 
     /*
@@ -669,17 +673,17 @@ struct pciio_piospace_s {
     size_t                  count;	/* size of PIO space */
 };
 
-/* Use io spin locks. This ensures that all the PIO writes from a particular
- * CPU to a particular IO device are synched before the start of the next
- * set of PIO operations to the same device.
+/* 
+ * pcibr_soft structure locking macros
  */
-#ifdef PCI_LATER
-#define pcibr_lock(pcibr_soft)		io_splock(pcibr_soft->bs_lock)
-#define pcibr_unlock(pcibr_soft, s)	io_spunlock(pcibr_soft->bs_lock,s)
-#else
-#define pcibr_lock(pcibr_soft)		1
-#define pcibr_unlock(pcibr_soft, s)	
-#endif	/* PCI_LATER */
+inline static unsigned long
+pcibr_lock(pcibr_soft_t pcibr_soft)
+{
+        unsigned long flag;
+        spin_lock_irqsave(&pcibr_soft->bs_lock, flag);
+        return(flag);
+}
+#define pcibr_unlock(pcibr_soft, flag)  spin_unlock_irqrestore(&pcibr_soft->bs_lock, flag)
 
 #define PCIBR_VALID_SLOT(ps, s)     (s < PCIBR_NUM_SLOTS(ps))
 #define PCIBR_D64_BASE_UNSET    (0xFFFFFFFFFFFFFFFF)
@@ -690,14 +694,13 @@ struct pciio_piospace_s {
 #if PCIBR_SOFT_LIST
 typedef struct pcibr_list_s *pcibr_list_p;
 struct pcibr_list_s {
-	pcibr_list_p            bl_next;
-	pcibr_soft_t            bl_soft;
-	vertex_hdl_t          bl_vhdl;
+    pcibr_list_p            bl_next;
+    pcibr_soft_t            bl_soft;
+    vertex_hdl_t            bl_vhdl;
 };
 #endif /* PCIBR_SOFT_LIST */
 
-
-// Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot.
+/* Devices per widget: 2 buses, 2 slots per bus, 8 functions per slot. */
 #define DEV_PER_WIDGET (2*2*8)
 
 struct sn_flush_device_list {