Commit 9887d1c7 authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini

MIPS: KVM: Add kvm_asid_change trace event

Add a trace event for guest ASID changes, replacing the existing
kvm_debug call.
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: kvm@vger.kernel.org
Cc: linux-mips@linux-mips.org
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 1e09e86a
...@@ -1082,11 +1082,10 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause, ...@@ -1082,11 +1082,10 @@ enum emulation_result kvm_mips_emulate_CP0(u32 inst, u32 *opc, u32 cause,
if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) && if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
((kvm_read_c0_guest_entryhi(cop0) & ((kvm_read_c0_guest_entryhi(cop0) &
KVM_ENTRYHI_ASID) != nasid)) { KVM_ENTRYHI_ASID) != nasid)) {
kvm_debug("MTCz, change ASID from %#lx to %#lx\n", trace_kvm_asid_change(vcpu,
kvm_read_c0_guest_entryhi(cop0) kvm_read_c0_guest_entryhi(cop0)
& KVM_ENTRYHI_ASID, & KVM_ENTRYHI_ASID,
vcpu->arch.gprs[rt] nasid);
& KVM_ENTRYHI_ASID);
/* Blow away the shadow host TLBs */ /* Blow away the shadow host TLBs */
kvm_mips_flush_host_tlb(1); kvm_mips_flush_host_tlb(1);
......
...@@ -122,6 +122,28 @@ TRACE_EVENT(kvm_aux, ...@@ -122,6 +122,28 @@ TRACE_EVENT(kvm_aux,
__entry->pc) __entry->pc)
); );
TRACE_EVENT(kvm_asid_change,
TP_PROTO(struct kvm_vcpu *vcpu, unsigned int old_asid,
unsigned int new_asid),
TP_ARGS(vcpu, old_asid, new_asid),
TP_STRUCT__entry(
__field(unsigned long, pc)
__field(u8, old_asid)
__field(u8, new_asid)
),
TP_fast_assign(
__entry->pc = vcpu->arch.pc;
__entry->old_asid = old_asid;
__entry->new_asid = new_asid;
),
TP_printk("PC: 0x%08lx old: 0x%02x new: 0x%02x",
__entry->pc,
__entry->old_asid,
__entry->new_asid)
);
#endif /* _TRACE_KVM_H */ #endif /* _TRACE_KVM_H */
/* This part must be outside protection */ /* This part must be outside protection */
......
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