Commit 988bf4f0 authored by David S. Miller's avatar David S. Miller

Merge branch 'cxgb4'

Hariprasad Shenai says:

====================
Fixes T5 adapter init, due to incorrect FW version check

This patch series fixes, Chelsio T5 adapter initialization failure due to
incorrect firmware version check. This patch series modifies the firmware
flashing mechanism for T4/T5 adapter.

The patch series moves chip type from struct adapter to struct adapter_params.
It changes the references of chip type in cxgb4 and cxgb4vf drivers such that
build failure is avoided.

Patch 3/3 is dependent on patch 1/3
Patch 2/3 is also dependent on patch 1/3

We would like to request this patch series to get merged via David Miller's
'net' tree.

We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1b85ee09 16e47624
...@@ -49,13 +49,15 @@ ...@@ -49,13 +49,15 @@
#include <asm/io.h> #include <asm/io.h>
#include "cxgb4_uld.h" #include "cxgb4_uld.h"
#define FW_VERSION_MAJOR 1 #define T4FW_VERSION_MAJOR 0x01
#define FW_VERSION_MINOR 4 #define T4FW_VERSION_MINOR 0x06
#define FW_VERSION_MICRO 0 #define T4FW_VERSION_MICRO 0x18
#define T4FW_VERSION_BUILD 0x00
#define FW_VERSION_MAJOR_T5 0 #define T5FW_VERSION_MAJOR 0x01
#define FW_VERSION_MINOR_T5 0 #define T5FW_VERSION_MINOR 0x08
#define FW_VERSION_MICRO_T5 0 #define T5FW_VERSION_MICRO 0x1C
#define T5FW_VERSION_BUILD 0x00
#define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__) #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
...@@ -240,6 +242,26 @@ struct pci_params { ...@@ -240,6 +242,26 @@ struct pci_params {
unsigned char width; unsigned char width;
}; };
#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
#define CHELSIO_CHIP_FPGA 0x100
#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
#define CHELSIO_T4 0x4
#define CHELSIO_T5 0x5
enum chip_type {
T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
T4_FIRST_REV = T4_A1,
T4_LAST_REV = T4_A2,
T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
T5_FIRST_REV = T5_A0,
T5_LAST_REV = T5_A1,
};
struct adapter_params { struct adapter_params {
struct tp_params tp; struct tp_params tp;
struct vpd_params vpd; struct vpd_params vpd;
...@@ -259,7 +281,7 @@ struct adapter_params { ...@@ -259,7 +281,7 @@ struct adapter_params {
unsigned char nports; /* # of ethernet ports */ unsigned char nports; /* # of ethernet ports */
unsigned char portvec; unsigned char portvec;
unsigned char rev; /* chip revision */ enum chip_type chip; /* chip code */
unsigned char offload; unsigned char offload;
unsigned char bypass; unsigned char bypass;
...@@ -267,6 +289,23 @@ struct adapter_params { ...@@ -267,6 +289,23 @@ struct adapter_params {
unsigned int ofldq_wr_cred; unsigned int ofldq_wr_cred;
}; };
#include "t4fw_api.h"
#define FW_VERSION(chip) ( \
FW_HDR_FW_VER_MAJOR_GET(chip##FW_VERSION_MAJOR) | \
FW_HDR_FW_VER_MINOR_GET(chip##FW_VERSION_MINOR) | \
FW_HDR_FW_VER_MICRO_GET(chip##FW_VERSION_MICRO) | \
FW_HDR_FW_VER_BUILD_GET(chip##FW_VERSION_BUILD))
#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
struct fw_info {
u8 chip;
char *fs_name;
char *fw_mod_name;
struct fw_hdr fw_hdr;
};
struct trace_params { struct trace_params {
u32 data[TRACE_LEN / 4]; u32 data[TRACE_LEN / 4];
u32 mask[TRACE_LEN / 4]; u32 mask[TRACE_LEN / 4];
...@@ -512,25 +551,6 @@ struct sge { ...@@ -512,25 +551,6 @@ struct sge {
struct l2t_data; struct l2t_data;
#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
#define CHELSIO_CHIP_VERSION(code) ((code) >> 4)
#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
#define CHELSIO_T4 0x4
#define CHELSIO_T5 0x5
enum chip_type {
T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0),
T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
T4_FIRST_REV = T4_A1,
T4_LAST_REV = T4_A3,
T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
T5_FIRST_REV = T5_A1,
T5_LAST_REV = T5_A1,
};
#ifdef CONFIG_PCI_IOV #ifdef CONFIG_PCI_IOV
/* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
...@@ -715,12 +735,12 @@ enum { ...@@ -715,12 +735,12 @@ enum {
static inline int is_t5(enum chip_type chip) static inline int is_t5(enum chip_type chip)
{ {
return (chip >= T5_FIRST_REV && chip <= T5_LAST_REV); return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5;
} }
static inline int is_t4(enum chip_type chip) static inline int is_t4(enum chip_type chip)
{ {
return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV); return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
} }
static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr) static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
...@@ -900,7 +920,11 @@ int get_vpd_params(struct adapter *adapter, struct vpd_params *p); ...@@ -900,7 +920,11 @@ int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
unsigned int t4_flash_cfg_addr(struct adapter *adapter); unsigned int t4_flash_cfg_addr(struct adapter *adapter);
int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
int t4_check_fw_version(struct adapter *adapter); int t4_get_fw_version(struct adapter *adapter, u32 *vers);
int t4_get_tp_version(struct adapter *adapter, u32 *vers);
int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
const u8 *fw_data, unsigned int fw_size,
struct fw_hdr *card_fw, enum dev_state state, int *reset);
int t4_prep_adapter(struct adapter *adapter); int t4_prep_adapter(struct adapter *adapter);
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
void t4_fatal_err(struct adapter *adapter); void t4_fatal_err(struct adapter *adapter);
......
...@@ -509,7 +509,7 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q) ...@@ -509,7 +509,7 @@ static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
u32 val; u32 val;
if (q->pend_cred >= 8) { if (q->pend_cred >= 8) {
val = PIDX(q->pend_cred / 8); val = PIDX(q->pend_cred / 8);
if (!is_t4(adap->chip)) if (!is_t4(adap->params.chip))
val |= DBTYPE(1); val |= DBTYPE(1);
wmb(); wmb();
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) | t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), DBPRIO(1) |
...@@ -847,7 +847,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n) ...@@ -847,7 +847,7 @@ static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
wmb(); /* write descriptors before telling HW */ wmb(); /* write descriptors before telling HW */
spin_lock(&q->db_lock); spin_lock(&q->db_lock);
if (!q->db_disabled) { if (!q->db_disabled) {
if (is_t4(adap->chip)) { if (is_t4(adap->params.chip)) {
t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL), t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
QID(q->cntxt_id) | PIDX(n)); QID(q->cntxt_id) | PIDX(n));
} else { } else {
...@@ -1596,7 +1596,7 @@ static noinline int handle_trace_pkt(struct adapter *adap, ...@@ -1596,7 +1596,7 @@ static noinline int handle_trace_pkt(struct adapter *adap,
return 0; return 0;
} }
if (is_t4(adap->chip)) if (is_t4(adap->params.chip))
__skb_pull(skb, sizeof(struct cpl_trace_pkt)); __skb_pull(skb, sizeof(struct cpl_trace_pkt));
else else
__skb_pull(skb, sizeof(struct cpl_t5_trace_pkt)); __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt));
...@@ -1661,7 +1661,7 @@ int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp, ...@@ -1661,7 +1661,7 @@ int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
const struct cpl_rx_pkt *pkt; const struct cpl_rx_pkt *pkt;
struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq); struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
struct sge *s = &q->adap->sge; struct sge *s = &q->adap->sge;
int cpl_trace_pkt = is_t4(q->adap->chip) ? int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
CPL_TRACE_PKT : CPL_TRACE_PKT_T5; CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
if (unlikely(*(u8 *)rsp == cpl_trace_pkt)) if (unlikely(*(u8 *)rsp == cpl_trace_pkt))
...@@ -2182,7 +2182,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, ...@@ -2182,7 +2182,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id) static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
{ {
q->cntxt_id = id; q->cntxt_id = id;
if (!is_t4(adap->chip)) { if (!is_t4(adap->params.chip)) {
unsigned int s_qpp; unsigned int s_qpp;
unsigned short udb_density; unsigned short udb_density;
unsigned long qpshift; unsigned long qpshift;
...@@ -2641,7 +2641,7 @@ static int t4_sge_init_hard(struct adapter *adap) ...@@ -2641,7 +2641,7 @@ static int t4_sge_init_hard(struct adapter *adap)
* Set up to drop DOORBELL writes when the DOORBELL FIFO overflows * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
* and generate an interrupt when this occurs so we can recover. * and generate an interrupt when this occurs so we can recover.
*/ */
if (is_t4(adap->chip)) { if (is_t4(adap->params.chip)) {
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS, t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
V_HP_INT_THRESH(M_HP_INT_THRESH) | V_HP_INT_THRESH(M_HP_INT_THRESH) |
V_LP_INT_THRESH(M_LP_INT_THRESH), V_LP_INT_THRESH(M_LP_INT_THRESH),
......
This diff is collapsed.
...@@ -1092,6 +1092,11 @@ ...@@ -1092,6 +1092,11 @@
#define PL_REV 0x1943c #define PL_REV 0x1943c
#define S_REV 0
#define M_REV 0xfU
#define V_REV(x) ((x) << S_REV)
#define G_REV(x) (((x) >> S_REV) & M_REV)
#define LE_DB_CONFIG 0x19c04 #define LE_DB_CONFIG 0x19c04
#define HASHEN 0x00100000U #define HASHEN 0x00100000U
...@@ -1199,4 +1204,13 @@ ...@@ -1199,4 +1204,13 @@
#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
#define A_PL_VF_REV 0x4
#define A_PL_VF_WHOAMI 0x0
#define A_PL_VF_REVISION 0x8
#define S_CHIPID 4
#define M_CHIPID 0xfU
#define V_CHIPID(x) ((x) << S_CHIPID)
#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
#endif /* __T4_REGS_H */ #endif /* __T4_REGS_H */
...@@ -2157,7 +2157,7 @@ struct fw_debug_cmd { ...@@ -2157,7 +2157,7 @@ struct fw_debug_cmd {
struct fw_hdr { struct fw_hdr {
u8 ver; u8 ver;
u8 reserved1; u8 chip; /* terminator chip type */
__be16 len512; /* bin length in units of 512-bytes */ __be16 len512; /* bin length in units of 512-bytes */
__be32 fw_ver; /* firmware version */ __be32 fw_ver; /* firmware version */
__be32 tp_microcode_ver; __be32 tp_microcode_ver;
...@@ -2176,6 +2176,11 @@ struct fw_hdr { ...@@ -2176,6 +2176,11 @@ struct fw_hdr {
__be32 reserved6[23]; __be32 reserved6[23];
}; };
enum fw_hdr_chip {
FW_HDR_CHIP_T4,
FW_HDR_CHIP_T5
};
#define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff) #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
#define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff) #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
#define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff) #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
......
...@@ -344,7 +344,6 @@ struct adapter { ...@@ -344,7 +344,6 @@ struct adapter {
unsigned long registered_device_map; unsigned long registered_device_map;
unsigned long open_device_map; unsigned long open_device_map;
unsigned long flags; unsigned long flags;
enum chip_type chip;
struct adapter_params params; struct adapter_params params;
/* queue and interrupt resources */ /* queue and interrupt resources */
......
...@@ -1064,7 +1064,7 @@ static inline unsigned int mk_adap_vers(const struct adapter *adapter) ...@@ -1064,7 +1064,7 @@ static inline unsigned int mk_adap_vers(const struct adapter *adapter)
/* /*
* Chip version 4, revision 0x3f (cxgb4vf). * Chip version 4, revision 0x3f (cxgb4vf).
*/ */
return CHELSIO_CHIP_VERSION(adapter->chip) | (0x3f << 10); return CHELSIO_CHIP_VERSION(adapter->params.chip) | (0x3f << 10);
} }
/* /*
...@@ -1551,9 +1551,13 @@ static void cxgb4vf_get_regs(struct net_device *dev, ...@@ -1551,9 +1551,13 @@ static void cxgb4vf_get_regs(struct net_device *dev,
reg_block_dump(adapter, regbuf, reg_block_dump(adapter, regbuf,
T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_FIRST, T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_FIRST,
T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_LAST); T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_LAST);
/* T5 adds new registers in the PL Register map.
*/
reg_block_dump(adapter, regbuf, reg_block_dump(adapter, regbuf,
T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST, T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST,
T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_LAST); T4VF_PL_BASE_ADDR + (is_t4(adapter->params.chip)
? A_PL_VF_WHOAMI : A_PL_VF_REVISION));
reg_block_dump(adapter, regbuf, reg_block_dump(adapter, regbuf,
T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST, T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST,
T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST); T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST);
...@@ -2087,6 +2091,7 @@ static int adap_init0(struct adapter *adapter) ...@@ -2087,6 +2091,7 @@ static int adap_init0(struct adapter *adapter)
unsigned int ethqsets; unsigned int ethqsets;
int err; int err;
u32 param, val = 0; u32 param, val = 0;
unsigned int chipid;
/* /*
* Wait for the device to become ready before proceeding ... * Wait for the device to become ready before proceeding ...
...@@ -2114,12 +2119,14 @@ static int adap_init0(struct adapter *adapter) ...@@ -2114,12 +2119,14 @@ static int adap_init0(struct adapter *adapter)
return err; return err;
} }
adapter->params.chip = 0;
switch (adapter->pdev->device >> 12) { switch (adapter->pdev->device >> 12) {
case CHELSIO_T4: case CHELSIO_T4:
adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T4, 0); adapter->params.chip = CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
break; break;
case CHELSIO_T5: case CHELSIO_T5:
adapter->chip = CHELSIO_CHIP_CODE(CHELSIO_T5, 0); chipid = G_REV(t4_read_reg(adapter, A_PL_VF_REV));
adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
break; break;
} }
......
...@@ -537,7 +537,7 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl) ...@@ -537,7 +537,7 @@ static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
*/ */
if (fl->pend_cred >= FL_PER_EQ_UNIT) { if (fl->pend_cred >= FL_PER_EQ_UNIT) {
val = PIDX(fl->pend_cred / FL_PER_EQ_UNIT); val = PIDX(fl->pend_cred / FL_PER_EQ_UNIT);
if (!is_t4(adapter->chip)) if (!is_t4(adapter->params.chip))
val |= DBTYPE(1); val |= DBTYPE(1);
wmb(); wmb();
t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL, t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
......
...@@ -39,21 +39,28 @@ ...@@ -39,21 +39,28 @@
#include "../cxgb4/t4fw_api.h" #include "../cxgb4/t4fw_api.h"
#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
#define CHELSIO_CHIP_VERSION(code) ((code) >> 4) #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
/* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
*
* V = "4" for T4; "5" for T5, etc. or
* = "a" for T4 FPGA; "b" for T4 FPGA, etc.
* F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
* PP = adapter product designation
*/
#define CHELSIO_T4 0x4 #define CHELSIO_T4 0x4
#define CHELSIO_T5 0x5 #define CHELSIO_T5 0x5
enum chip_type { enum chip_type {
T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0), T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
T4_FIRST_REV = T4_A1, T4_FIRST_REV = T4_A1,
T4_LAST_REV = T4_A3, T4_LAST_REV = T4_A2,
T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
T5_FIRST_REV = T5_A1, T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
T5_FIRST_REV = T5_A0,
T5_LAST_REV = T5_A1, T5_LAST_REV = T5_A1,
}; };
...@@ -203,6 +210,7 @@ struct adapter_params { ...@@ -203,6 +210,7 @@ struct adapter_params {
struct vpd_params vpd; /* Vital Product Data */ struct vpd_params vpd; /* Vital Product Data */
struct rss_params rss; /* Receive Side Scaling */ struct rss_params rss; /* Receive Side Scaling */
struct vf_resources vfres; /* Virtual Function Resource limits */ struct vf_resources vfres; /* Virtual Function Resource limits */
enum chip_type chip; /* chip code */
u8 nports; /* # of Ethernet "ports" */ u8 nports; /* # of Ethernet "ports" */
}; };
...@@ -253,7 +261,7 @@ static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd, ...@@ -253,7 +261,7 @@ static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
static inline int is_t4(enum chip_type chip) static inline int is_t4(enum chip_type chip)
{ {
return (chip >= T4_FIRST_REV && chip <= T4_LAST_REV); return CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4;
} }
int t4vf_wait_dev_ready(struct adapter *); int t4vf_wait_dev_ready(struct adapter *);
......
...@@ -1027,7 +1027,7 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free, ...@@ -1027,7 +1027,7 @@ int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
unsigned nfilters = 0; unsigned nfilters = 0;
unsigned int rem = naddr; unsigned int rem = naddr;
struct fw_vi_mac_cmd cmd, rpl; struct fw_vi_mac_cmd cmd, rpl;
unsigned int max_naddr = is_t4(adapter->chip) ? unsigned int max_naddr = is_t4(adapter->params.chip) ?
NUM_MPS_CLS_SRAM_L_INSTANCES : NUM_MPS_CLS_SRAM_L_INSTANCES :
NUM_MPS_T5_CLS_SRAM_L_INSTANCES; NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
...@@ -1121,7 +1121,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid, ...@@ -1121,7 +1121,7 @@ int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
struct fw_vi_mac_exact *p = &cmd.u.exact[0]; struct fw_vi_mac_exact *p = &cmd.u.exact[0];
size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
u.exact[1]), 16); u.exact[1]), 16);
unsigned int max_naddr = is_t4(adapter->chip) ? unsigned int max_naddr = is_t4(adapter->params.chip) ?
NUM_MPS_CLS_SRAM_L_INSTANCES : NUM_MPS_CLS_SRAM_L_INSTANCES :
NUM_MPS_T5_CLS_SRAM_L_INSTANCES; NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
......
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