[PATCH] SCSI QLA not working on latest *-mm SN2 (qla_dbg fixes)
On Thu, 2004-09-16 at 14:09, Jesse Barnes wrote: > On Thursday, September 16, 2004 1:56 pm, Andrew Vasquez wrote: > > On Thu, 2004-09-16 at 13:05, Jesse Barnes wrote: > > > On Thursday, September 16, 2004 12:56 pm, Paul Jackson wrote: > > > > Andrew Vasquez has been looking at this, via private email with just > > > > me (no progress yet). Figured I update the larger list with this much > > > > ... > > > > > > It seems to be failing on one of the accesses to PCI_COMMAND in config > > > space in qla2x00_reset_chip(). I'm checking now to see if we're > > > accessing the card right after a reset but before the card has finished. > > > That would cause a master abort, the symptom I'm seeing at least. > > > > Interesting, the only changes in reset_chip() are for PCI posting > > issues. Relevant diff attached. > > Yeah, I think one of these is the culprit. Before I got your message, I fixed > some of them in my tree already (see attached) and things seem to work. > Hmm, seems we were a bit too over-aggressive in placement of the readw()s :( > WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); > + RD_REG_WORD(®->hccr); /* PCI Posting. */ > WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT); > + RD_REG_WORD(®->hccr); /* PCI Posting. */ > > /* Reset ISP chip. */ > WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); > + RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ > > In particular, are the above ok? If the chip is resetting, won't doing a read > cause a machine check (or at the very least, a device select timeout, which > will return all ones on friendlier platforms). > There are several more which deltas in qla_dbg.c which are suspect also. > WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); > + RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ > > Same here? > Andrew, please add Jesse's patch along with the patch I'm attaching to your tree. I'll be sure to add the ia64 machine back into our test ring. Signed-off-by:Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by:
James Bottomley <James.Bottomley@SteelEye.com>
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