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Commit 9b7b8154 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
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drm/amd/powerplay: added didt support for vega10 

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 209ee27e
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Showing with 1381 additions and 0 deletions
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
View file @ 9b7b8154
...@@ -146,6 +146,19 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) ...@@ -146,6 +146,19 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
data->registry_data.vr1hot_enabled = 1; data->registry_data.vr1hot_enabled = 1;
data->registry_data.regulator_hot_gpio_support = 1; data->registry_data.regulator_hot_gpio_support = 1;
data->registry_data.didt_support = 1;
if (data->registry_data.didt_support) {
data->registry_data.didt_mode = 6;
data->registry_data.sq_ramping_support = 1;
data->registry_data.db_ramping_support = 0;
data->registry_data.td_ramping_support = 0;
data->registry_data.tcp_ramping_support = 0;
data->registry_data.dbr_ramping_support = 0;
data->registry_data.edc_didt_support = 1;
data->registry_data.gc_didt_support = 0;
data->registry_data.psm_didt_support = 0;
}
data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT; data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
...@@ -222,6 +235,8 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) ...@@ -222,6 +235,8 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
/* assume disabled */ /* assume disabled */
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment); PHM_PlatformCaps_PowerContainment);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DiDtSupport);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SQRamping); PHM_PlatformCaps_SQRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
...@@ -230,6 +245,34 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) ...@@ -230,6 +245,34 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_TDRamping); PHM_PlatformCaps_TDRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TCPRamping); PHM_PlatformCaps_TCPRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DBRRamping);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DiDtEDCEnable);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_GCEDC);
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PSM);
if (data->registry_data.didt_support) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
if (data->registry_data.sq_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
if (data->registry_data.db_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
if (data->registry_data.td_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
if (data->registry_data.tcp_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
if (data->registry_data.dbr_ramping_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
if (data->registry_data.edc_didt_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
if (data->registry_data.gc_didt_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
if (data->registry_data.psm_didt_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
}
if (data->registry_data.power_containment_support) if (data->registry_data.power_containment_support)
phm_cap_set(hwmgr->platform_descriptor.platformCaps, phm_cap_set(hwmgr->platform_descriptor.platformCaps,
...@@ -322,6 +365,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) ...@@ -322,6 +365,7 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
FEATURE_FAN_CONTROL_BIT; FEATURE_FAN_CONTROL_BIT;
data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
if (!data->registry_data.prefetcher_dpm_key_disabled) if (!data->registry_data.prefetcher_dpm_key_disabled)
data->smu_features[GNLD_DPM_PREFETCHER].supported = true; data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
...@@ -391,6 +435,9 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) ...@@ -391,6 +435,9 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
if ((data->smu_version & 0xff000000) == 0x5000000) if ((data->smu_version & 0xff000000) == 0x5000000)
data->smu_features[GNLD_ACG].supported = true; data->smu_features[GNLD_ACG].supported = true;
if (data->registry_data.didt_support)
data->smu_features[GNLD_DIDT].supported = true;
} }
#ifdef PPLIB_VEGA10_EVV_SUPPORT #ifdef PPLIB_VEGA10_EVV_SUPPORT
...@@ -2907,6 +2954,11 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) ...@@ -2907,6 +2954,11 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE(!tmp_result,
"Failed to start DPM!", result = tmp_result); "Failed to start DPM!", result = tmp_result);
/* enable didt, do not abort if failed didt */
tmp_result = vega10_enable_didt_config(hwmgr);
PP_ASSERT(!tmp_result,
"Failed to enable didt config!");
tmp_result = vega10_enable_power_containment(hwmgr); tmp_result = vega10_enable_power_containment(hwmgr);
PP_ASSERT_WITH_CODE(!tmp_result, PP_ASSERT_WITH_CODE(!tmp_result,
"Failed to enable power containment!", "Failed to enable power containment!",
...@@ -4736,6 +4788,10 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) ...@@ -4736,6 +4788,10 @@ static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable power containment!", result = tmp_result); "Failed to disable power containment!", result = tmp_result);
tmp_result = vega10_disable_didt_config(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable didt config!", result = tmp_result);
tmp_result = vega10_avfs_enable(hwmgr, false); tmp_result = vega10_avfs_enable(hwmgr, false);
PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable AVFS!", result = tmp_result); "Failed to disable AVFS!", result = tmp_result);
......
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
View file @ 9b7b8154
...@@ -232,7 +232,9 @@ struct vega10_registry_data { ...@@ -232,7 +232,9 @@ struct vega10_registry_data {
uint8_t cac_support; uint8_t cac_support;
uint8_t clock_stretcher_support; uint8_t clock_stretcher_support;
uint8_t db_ramping_support; uint8_t db_ramping_support;
uint8_t didt_mode;
uint8_t didt_support; uint8_t didt_support;
uint8_t edc_didt_support;
uint8_t dynamic_state_patching_support; uint8_t dynamic_state_patching_support;
uint8_t enable_pkg_pwr_tracking_feature; uint8_t enable_pkg_pwr_tracking_feature;
uint8_t enable_tdc_limit_feature; uint8_t enable_tdc_limit_feature;
...@@ -265,6 +267,9 @@ struct vega10_registry_data { ...@@ -265,6 +267,9 @@ struct vega10_registry_data {
uint8_t tcp_ramping_support; uint8_t tcp_ramping_support;
uint8_t tdc_support; uint8_t tdc_support;
uint8_t td_ramping_support; uint8_t td_ramping_support;
uint8_t dbr_ramping_support;
uint8_t gc_didt_support;
uint8_t psm_didt_support;
uint8_t thermal_out_gpio_support; uint8_t thermal_out_gpio_support;
uint8_t thermal_support; uint8_t thermal_support;
uint8_t fw_ctf_enabled; uint8_t fw_ctf_enabled;
......
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h
View file @ 9b7b8154
...@@ -31,6 +31,12 @@ enum vega10_pt_config_reg_type { ...@@ -31,6 +31,12 @@ enum vega10_pt_config_reg_type {
VEGA10_CONFIGREG_MAX VEGA10_CONFIGREG_MAX
}; };
enum vega10_didt_config_reg_type {
VEGA10_CONFIGREG_DIDT = 0,
VEGA10_CONFIGREG_GCCAC,
VEGA10_CONFIGREG_SECAC
};
/* PowerContainment Features */ /* PowerContainment Features */
#define POWERCONTAINMENT_FEATURE_DTE 0x00000001 #define POWERCONTAINMENT_FEATURE_DTE 0x00000001
#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
...@@ -44,6 +50,13 @@ struct vega10_pt_config_reg { ...@@ -44,6 +50,13 @@ struct vega10_pt_config_reg {
enum vega10_pt_config_reg_type type; enum vega10_pt_config_reg_type type;
}; };
struct vega10_didt_config_reg {
uint32_t offset;
uint32_t mask;
uint32_t shift;
uint32_t value;
};
struct vega10_pt_defaults { struct vega10_pt_defaults {
uint8_t SviLoadLineEn; uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC; uint8_t SviLoadLineVddC;
...@@ -62,5 +75,8 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); ...@@ -62,5 +75,8 @@ int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
int vega10_power_control_set_level(struct pp_hwmgr *hwmgr); int vega10_power_control_set_level(struct pp_hwmgr *hwmgr);
int vega10_disable_power_containment(struct pp_hwmgr *hwmgr); int vega10_disable_power_containment(struct pp_hwmgr *hwmgr);
int vega10_enable_didt_config(struct pp_hwmgr *hwmgr);
int vega10_disable_didt_config(struct pp_hwmgr *hwmgr);
#endif /* _VEGA10_POWERTUNE_H_ */ #endif /* _VEGA10_POWERTUNE_H_ */
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
View file @ 9b7b8154
...@@ -164,9 +164,14 @@ enum phm_platform_caps { ...@@ -164,9 +164,14 @@ enum phm_platform_caps {
PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */ PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */
PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */ PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */
PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */ PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */
PHM_PlatformCaps_DiDtSupport, /* for dI/dT feature */
PHM_PlatformCaps_DBRamping, /* for dI/dT feature */ PHM_PlatformCaps_DBRamping, /* for dI/dT feature */
PHM_PlatformCaps_TDRamping, /* for dI/dT feature */ PHM_PlatformCaps_TDRamping, /* for dI/dT feature */
PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */ PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */
PHM_PlatformCaps_DBRRamping, /* for dI/dT feature */
PHM_PlatformCaps_DiDtEDCEnable, /* for dI/dT feature */
PHM_PlatformCaps_GCEDC, /* for dI/dT feature */
PHM_PlatformCaps_PSM, /* for dI/dT feature */
PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */ PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */
PHM_PlatformCaps_FPS, /* FPS support */ PHM_PlatformCaps_FPS, /* FPS support */
PHM_PlatformCaps_ACP, /* ACP support */ PHM_PlatformCaps_ACP, /* ACP support */
......
drivers/gpu/drm/amd/powerplay/inc/pp_debug.h
View file @ 9b7b8154
...@@ -42,6 +42,12 @@ ...@@ -42,6 +42,12 @@
} \ } \
} while (0) } while (0)
#define PP_ASSERT(cond, msg) \
do { \
if (!(cond)) { \
pr_warn("%s\n", msg); \
} \
} while (0)
#define PP_DBG_LOG(fmt, ...) \ #define PP_DBG_LOG(fmt, ...) \
do { \ do { \
......
drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
View file @ 9b7b8154
...@@ -41,6 +41,8 @@ inline static uint32_t soc15_get_register_offset( ...@@ -41,6 +41,8 @@ inline static uint32_t soc15_get_register_offset(
reg = MP1_BASE.instance[inst].segment[segment] + offset; reg = MP1_BASE.instance[inst].segment[segment] + offset;
else if (hw_id == DF_HWID) else if (hw_id == DF_HWID)
reg = DF_BASE.instance[inst].segment[segment] + offset; reg = DF_BASE.instance[inst].segment[segment] + offset;
else if (hw_id == GC_HWID)
reg = GC_BASE.instance[inst].segment[segment] + offset;
return reg; return reg;
} }
......
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