Commit 9bfa2544 authored by Claudiu Beznea's avatar Claudiu Beznea

ARM: dts: at91: sam9x60: fix the ddr clock for sam9x60

The 2nd DDR clock for sam9x60 DDR controller is peripheral clock with
id 49.

Fixes: 1e5f532c ("ARM: dts: at91: sam9x60: add device tree for soc and board")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221208115241.36312-1-claudiu.beznea@microchip.com
parent 1b929c02
...@@ -564,7 +564,7 @@ pmecc: ecc-engine@ffffe000 { ...@@ -564,7 +564,7 @@ pmecc: ecc-engine@ffffe000 {
mpddrc: mpddrc@ffffe800 { mpddrc: mpddrc@ffffe800 {
compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
reg = <0xffffe800 0x200>; reg = <0xffffe800 0x200>;
clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
clock-names = "ddrck", "mpddr"; clock-names = "ddrck", "mpddr";
}; };
......
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