drm/amd/powerplay: fix typos for clk map

It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

@@ -128,8 +128,8 @@ static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 	CLK_MAP(UCLK,		PPCLK_UCLK),
 	CLK_MAP(MCLK,		PPCLK_UCLK),
 	CLK_MAP(DCLK,		PPCLK_DCLK_0),
-	CLK_MAP(DCLK1,		PPCLK_DCLK_0),
-	CLK_MAP(VCLK,		PPCLK_VCLK_1),
+	CLK_MAP(DCLK1,		PPCLK_DCLK_1),
+	CLK_MAP(VCLK,		PPCLK_VCLK_0),
 	CLK_MAP(VCLK1,		PPCLK_VCLK_1),
 	CLK_MAP(DCEFCLK,	PPCLK_DCEFCLK),
 	CLK_MAP(DISPCLK,	PPCLK_DISPCLK),