clk: samsung: exynos7: add gate clock for DMA block

Add support for PDMA0 and PDMA1 gate clks.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

drivers/clk/samsung/clk-exynos7.c

@@ -722,6 +722,10 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
 	GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
 		"mout_aclk_fsys0_200_user",
 		ENABLE_ACLK_FSYS00, 19, 0, 0),
+	GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
+			ENABLE_ACLK_FSYS00, 3, 0, 0),
+	GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
+			ENABLE_ACLK_FSYS00, 4, 0, 0),
 
 	GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
 		ENABLE_ACLK_FSYS01, 29, 0, 0),

include/dt-bindings/clock/exynos7-clk.h

@@ -91,7 +91,9 @@
 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
 #define OSCCLK_PHY_CLKOUT_USB30_PHY		8
-#define FSYS0_NR_CLK			9
+#define ACLK_PDMA0			9
+#define ACLK_PDMA1			10
+#define FSYS0_NR_CLK			11
 
 /* FSYS1 */
 #define ACLK_MMC1			1