drm/amd/display: Update DCE for DCN35 support

[Why & How]
Update DCE files for DCN35 usage.
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dce/dce_abm.h

@@ -183,8 +183,7 @@
 	ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 
-#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
-	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+#define ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh) \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 			ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
@@ -214,9 +213,13 @@
 	ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 			ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 
-#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
+#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
+	ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
+	ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
 
+#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
 #define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
+#define ABM_MASK_SH_LIST_DCN35(mask_sh) ABM_MASK_SH_LIST_DCN10_COMMON(mask_sh)
 
 #define ABM_MASK_SH_LIST_DCN32(mask_sh) \
 	ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

@@ -681,6 +681,8 @@ struct dce_hwseq_registers {
 	uint32_t DMU_MEM_PWR_CNTL;
 	uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
 	uint32_t HPO_TOP_HW_CONTROL;
+	uint32_t DMU_CLK_CNTL;
+	uint32_t DCCG_GATE_DISABLE_CNTL5;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -1167,12 +1169,29 @@ struct dce_hwseq_registers {
 	type I2C_LIGHT_SLEEP_FORCE;\
 	type HPO_IO_EN;
 
+#define HWSEQ_DCN35_REG_FIELD_LIST(type) \
+	type DISPCLK_R_DMU_GATE_DIS;\
+	type DISPCLK_G_RBBMIF_GATE_DIS;\
+	type RBBMIF_FGCG_REP_DIS;\
+	type IHC_FGCG_REP_DIS;\
+	type DPREFCLK_ALLOW_DS_CLKSTOP;\
+	type DISPCLK_ALLOW_DS_CLKSTOP;\
+	type DPPCLK_ALLOW_DS_CLKSTOP;\
+	type DTBCLK_ALLOW_DS_CLKSTOP;\
+	type DCFCLK_ALLOW_DS_CLKSTOP;\
+	type DPIACLK_ALLOW_DS_CLKSTOP;\
+	type LONO_FGCG_REP_DIS;\
+	type LONO_DISPCLK_GATE_DISABLE;\
+	type LONO_SOCCLK_GATE_DISABLE;\
+	type LONO_DMCUBCLK_GATE_DISABLE;
+
 struct dce_hwseq_shift {
 	HWSEQ_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
+	HWSEQ_DCN35_REG_FIELD_LIST(uint8_t)
 };
 
 struct dce_hwseq_mask {
@@ -1181,6 +1200,7 @@ struct dce_hwseq_mask {
 	HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
 	HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
 	HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
+	HWSEQ_DCN35_REG_FIELD_LIST(uint32_t)
 };
 
 

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

@@ -308,6 +308,10 @@ static bool setup_engine(
 		     }
 	     }
 
+	if (dce_i2c_hw->masks->DC_I2C_DDC1_CLK_EN)
+		REG_UPDATE_N(SETUP, 1,
+			     FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_EN), 1);
+
 	/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
 	REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
 

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h

@@ -188,6 +188,7 @@ struct dce_i2c_shift {
 	uint8_t DC_I2C_REG_RW_CNTL_STATUS;
 	uint8_t I2C_LIGHT_SLEEP_FORCE;
 	uint8_t I2C_MEM_PWR_STATE;
+	uint8_t DC_I2C_DDC1_CLK_EN;
 };
 
 struct dce_i2c_mask {
@@ -232,6 +233,7 @@ struct dce_i2c_mask {
 	uint32_t DC_I2C_REG_RW_CNTL_STATUS;
 	uint32_t I2C_LIGHT_SLEEP_FORCE;
 	uint32_t I2C_MEM_PWR_STATE;
+	uint32_t DC_I2C_DDC1_CLK_EN;
 };
 
 #define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
@@ -243,6 +245,10 @@ struct dce_i2c_mask {
 	I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\
 	I2C_SF(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, mask_sh)
 
+#define I2C_COMMON_MASK_SH_LIST_DCN35(mask_sh)\
+	I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh),\
+	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_EN, mask_sh)
+
 struct dce_i2c_registers {
 	uint32_t SETUP;
 	uint32_t SPEED;