Skip to content

L
linux
Commit 9e0c42ea authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files
Options

Merge tag 'exynos-cleanup' of... 

Merge tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup3

Merge "Exynos cleanup for v3.15" from Kukjin Kim:

- reorganize code for
- add support reserve memory for mfc-v7
- consolidate exynos4 and exynos5 machine codes
- add generic compatible strings for exynos4 and exynos5
- update DT with generic compatible strings
- move clk related dt-binding header file in dt-bindings/clock

* tag 'exynos-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  dt-bindings: clock: Move exynos-audss-clk.h to dt-bindings/clock
  ARM: dts: Update Exynos DT files with generic compatible strings
  ARM: EXYNOS: Add generic compatible strings
  ARM: EXYNOS: Consolidate exynos4 and exynos5 machine files
  ARM: EXYNOS: Consolidate CPU init code
  ARM: SAMSUNG: Introduce generic Exynos4 and 5 helpers
  ARM: EXYNOS: Add support to reserve memory for MFC-v7
  ARM: SAMSUNG: Reorganize calls to reserve memory for MFC

Conflicts:
	arch/arm/mach-exynos/exynos.c

Signed-off-by; Arnd Bergmann <arnd@arndb.de>
parents 2c793fa3 602408e3
Hide whitespace changes
Inline Side-by-side
Showing with 166 additions and 303 deletions
arch/arm/boot/dts/exynos4210-origen.dts
View file @ 9e0c42ea
......@@ -19,7 +19,7 @@
/ {
model = "Insignal Origen evaluation board based on Exynos4210";
compatible = "insignal,origen", "samsung,exynos4210";
compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x10000000
......
arch/arm/boot/dts/exynos4210-smdkv310.dts
View file @ 9e0c42ea
......@@ -19,7 +19,7 @@
/ {
model = "Samsung smdkv310 evaluation board based on Exynos4210";
compatible = "samsung,smdkv310", "samsung,exynos4210";
compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x80000000>;
......
arch/arm/boot/dts/exynos4210-trats.dts
View file @ 9e0c42ea
......@@ -17,7 +17,7 @@
/ {
model = "Samsung Trats based on Exynos4210";
compatible = "samsung,trats", "samsung,exynos4210";
compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x10000000
......
arch/arm/boot/dts/exynos4210-universal_c210.dts
View file @ 9e0c42ea
......@@ -17,7 +17,7 @@
/ {
model = "Samsung Universal C210 based on Exynos4210 rev0";
compatible = "samsung,universal_c210", "samsung,exynos4210";
compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4";
memory {
reg = <0x40000000 0x10000000
......
arch/arm/boot/dts/exynos4210.dtsi
View file @ 9e0c42ea
......@@ -23,7 +23,7 @@
#include "exynos4210-pinctrl.dtsi"
/ {
compatible = "samsung,exynos4210";
compatible = "samsung,exynos4210", "samsung,exynos4";
aliases {
pinctrl0 = &pinctrl_0;
......
arch/arm/boot/dts/exynos4212.dtsi
View file @ 9e0c42ea
......@@ -20,7 +20,7 @@
#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4212";
compatible = "samsung,exynos4212", "samsung,exynos4";
combiner: interrupt-controller@10440000 {
samsung,combiner-nr = <18>;
......
arch/arm/boot/dts/exynos4412-odroidx.dts
View file @ 9e0c42ea
......@@ -16,7 +16,7 @@
/ {
model = "Hardkernel ODROID-X board based on Exynos4412";
compatible = "hardkernel,odroid-x", "samsung,exynos4412";
compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
......
arch/arm/boot/dts/exynos4412-origen.dts
View file @ 9e0c42ea
......@@ -17,7 +17,7 @@
/ {
model = "Insignal Origen evaluation board based on Exynos4412";
compatible = "insignal,origen4412", "samsung,exynos4412";
compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
......
arch/arm/boot/dts/exynos4412-smdk4412.dts
View file @ 9e0c42ea
......@@ -17,7 +17,7 @@
/ {
model = "Samsung SMDK evaluation board based on Exynos4412";
compatible = "samsung,smdk4412", "samsung,exynos4412";
compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
......
arch/arm/boot/dts/exynos4412-tiny4412.dts
View file @ 9e0c42ea
......@@ -16,7 +16,7 @@
/ {
model = "FriendlyARM TINY4412 board based on Exynos4412";
compatible = "friendlyarm,tiny4412", "samsung,exynos4412";
compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
memory {
reg = <0x40000000 0x40000000>;
......
arch/arm/boot/dts/exynos4412-trats2.dts
View file @ 9e0c42ea
......@@ -17,7 +17,7 @@
/ {
model = "Samsung Trats 2 based on Exynos4412";
compatible = "samsung,trats2", "samsung,exynos4412";
compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
aliases {
i2c8 = &i2c_ak8975;
......
arch/arm/boot/dts/exynos4412.dtsi
View file @ 9e0c42ea
......@@ -20,7 +20,7 @@
#include "exynos4x12.dtsi"
/ {
compatible = "samsung,exynos4412";
compatible = "samsung,exynos4412", "samsung,exynos4";
combiner: interrupt-controller@10440000 {
samsung,combiner-nr = <20>;
......
arch/arm/boot/dts/exynos5250-arndale.dts
View file @ 9e0c42ea
......@@ -15,7 +15,7 @@
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
compatible = "insignal,arndale", "samsung,exynos5250";
compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
memory {
reg = <0x40000000 0x80000000>;
......
arch/arm/boot/dts/exynos5250-smdk5250.dts
View file @ 9e0c42ea
......@@ -14,7 +14,7 @@
/ {
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
compatible = "samsung,smdk5250", "samsung,exynos5250";
compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
aliases {
};
......
arch/arm/boot/dts/exynos5250-snow.dts
View file @ 9e0c42ea
......@@ -14,7 +14,7 @@
/ {
model = "Google Snow";
compatible = "google,snow", "samsung,exynos5250";
compatible = "google,snow", "samsung,exynos5250", "samsung,exynos5";
aliases {
i2c104 = &i2c_104;
......
arch/arm/boot/dts/exynos5250.dtsi
View file @ 9e0c42ea
......@@ -21,10 +21,10 @@
#include "exynos5.dtsi"
#include "exynos5250-pinctrl.dtsi"
#include <dt-bindings/clk/exynos-audss-clk.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
/ {
compatible = "samsung,exynos5250";
compatible = "samsung,exynos5250", "samsung,exynos5";
aliases {
spi0 = &spi_0;
......
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View file @ 9e0c42ea
......@@ -16,7 +16,7 @@
/ {
model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
compatible = "insignal,arndale-octa", "samsung,exynos5420";
compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
memory {
reg = <0x20000000 0x80000000>;
......
arch/arm/boot/dts/exynos5420-smdk5420.dts
View file @ 9e0c42ea
......@@ -14,7 +14,7 @@
/ {
model = "Samsung SMDK5420 board based on EXYNOS5420";
compatible = "samsung,smdk5420", "samsung,exynos5420";
compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
memory {
reg = <0x20000000 0x80000000>;
......
arch/arm/boot/dts/exynos5420.dtsi
View file @ 9e0c42ea
......@@ -17,10 +17,10 @@
#include "exynos5.dtsi"
#include "exynos5420-pinctrl.dtsi"
#include <dt-bindings/clk/exynos-audss-clk.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
/ {
compatible = "samsung,exynos5420";
compatible = "samsung,exynos5420", "samsung,exynos5";
aliases {
mshc0 = &mmc_0;
......
arch/arm/boot/dts/exynos5440-sd5v1.dts
View file @ 9e0c42ea
......@@ -14,7 +14,7 @@
/ {
model = "SAMSUNG SD5v1 board based on EXYNOS5440";
compatible = "samsung,sd5v1", "samsung,exynos5440";
compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5";
chosen {
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
......
arch/arm/boot/dts/exynos5440-ssdk5440.dts
View file @ 9e0c42ea
......@@ -14,7 +14,7 @@
/ {
model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
compatible = "samsung,ssdk5440", "samsung,exynos5440";
compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5";
chosen {
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
......
arch/arm/boot/dts/exynos5440.dtsi
View file @ 9e0c42ea
......@@ -13,7 +13,7 @@
#include "skeleton.dtsi"
/ {
compatible = "samsung,exynos5440";
compatible = "samsung,exynos5440", "samsung,exynos5";
interrupt-parent = <&gic>;
......
arch/arm/mach-exynos/Makefile
View file @ 9e0c42ea
......@@ -12,7 +12,7 @@ obj- :=
# Core
obj-$(CONFIG_ARCH_EXYNOS) += common.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos.o
obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
......@@ -29,8 +29,3 @@ obj-$(CONFIG_ARCH_EXYNOS) += firmware.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
# machine support
obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o
obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o
arch/arm/mach-exynos/common.h
View file @ 9e0c42ea
......@@ -19,8 +19,7 @@ void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
struct map_desc;
void exynos_init_io(void);
void exynos4_restart(enum reboot_mode mode, const char *cmd);
void exynos5_restart(enum reboot_mode mode, const char *cmd);
void exynos_restart(enum reboot_mode mode, const char *cmd);
void exynos_cpuidle_init(void);
void exynos_cpufreq_init(void);
void exynos_init_late(void);
......
arch/arm/mach-exynos/common.c → arch/arm/mach-exynos/exynos.c
View file @ 9e0c42ea
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* SAMSUNG EXYNOS Flattened Device Tree enabled machine
*
* Common Codes for EXYNOS
* Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/gpio.h>
#include <clocksource/samsung_pwm.h>
#include <linux/sched.h>
#include <linux/serial_core.h>
#include <linux/kernel.h>
#include <linux/serial_s3c.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <linux/of_irq.h>
#include <linux/pm_domain.h>
#include <linux/export.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <asm/proc-fns.h>
#include <asm/exception.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/cacheflush.h>
#include <asm/memory.h>
#include <plat/cpu.h>
#include <plat/pm.h>
#include "common.h"
#include "mfc.h"
#include "regs-pmu.h"
#define L2_AUX_VAL 0x7C470001
#define L2_AUX_MASK 0xC200ffff
static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
static void exynos4_map_io(void);
static void exynos5_map_io(void);
static int exynos_init(void);
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = EXYNOS4210_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init = exynos_init,
.name = name_exynos4210,
}, {
.idcode = EXYNOS4212_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init = exynos_init,
.name = name_exynos4212,
}, {
.idcode = EXYNOS4412_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init = exynos_init,
.name = name_exynos4412,
}, {
.idcode = EXYNOS5250_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
.init = exynos_init,
.name = name_exynos5250,
}, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
.init = exynos_init,
.name = name_exynos5420,
}, {
.idcode = EXYNOS5440_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.init = exynos_init,
.name = name_exynos5440,
},
};
/* Initial IO mappings */
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
......@@ -263,19 +198,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
},
};
void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
__raw_writel(0x1, S5P_SWRESET);
}
void exynos5_restart(enum reboot_mode mode, const char *cmd)
void exynos_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
u32 val;
void __iomem *addr;
val = 0x1;
addr = EXYNOS_SWRESET;
u32 val = 0x1;
void __iomem *addr = EXYNOS_SWRESET;
if (of_machine_is_compatible("samsung,exynos5440")) {
u32 status;
......@@ -346,6 +273,28 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
*
* register the standard cpu IO areas
*/
static void __init exynos_map_io(void)
{
if (soc_is_exynos4())
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
if (soc_is_exynos5())
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
if (soc_is_exynos4210()) {
if (samsung_rev() == EXYNOS4210_REV_0)
iotable_init(exynos4_iodesc0,
ARRAY_SIZE(exynos4_iodesc0));
else
iotable_init(exynos4_iodesc1,
ARRAY_SIZE(exynos4_iodesc1));
iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
}
if (soc_is_exynos4212() || soc_is_exynos4412())
iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
}
void __init exynos_init_io(void)
{
......@@ -356,30 +305,7 @@ void __init exynos_init_io(void)
/* detect cpu id and rev. */
s5p_init_cpu(S5P_VA_CHIPID);
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
}
static void __init exynos4_map_io(void)
{
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
else
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
if (soc_is_exynos4210())
iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
if (soc_is_exynos4212() || soc_is_exynos4412())
iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
}
static void __init exynos5_map_io(void)
{
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
exynos_map_io();
}
struct bus_type exynos_subsys = {
......@@ -387,10 +313,6 @@ struct bus_type exynos_subsys = {
.dev_name = "exynos-core",
};
static struct device exynos4_dev = {
.bus = &exynos_subsys,
};
static int __init exynos_core_init(void)
{
return subsys_system_register(&exynos_subsys, NULL);
......@@ -411,9 +333,77 @@ static int __init exynos4_l2x0_cache_init(void)
}
early_initcall(exynos4_l2x0_cache_init);
static int __init exynos_init(void)
static void __init exynos_dt_machine_init(void)
{
printk(KERN_INFO "EXYNOS: Initializing architecture\n");
struct device_node *i2c_np;
const char *i2c_compat = "samsung,s3c2440-i2c";
unsigned int tmp;
int id;
/*
* Exynos5's legacy i2c controller and new high speed i2c
* controller have muxed interrupt sources. By default the
* interrupts for 4-channel HS-I2C controller are enabled.
* If node for first four channels of legacy i2c controller
* are available then re-configure the interrupts via the
* system register.
*/
if (soc_is_exynos5()) {
for_each_compatible_node(i2c_np, NULL, i2c_compat) {
if (of_device_is_available(i2c_np)) {
id = of_alias_get_id(i2c_np, "i2c");
if (id < 4) {
tmp = readl(EXYNOS5_SYS_I2C_CFG);
writel(tmp & ~(0x1 << id),
EXYNOS5_SYS_I2C_CFG);
}
}
}
}
return device_register(&exynos4_dev);
exynos_cpuidle_init();
exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos_dt_compat[] __initconst = {
"samsung,exynos4",
"samsung,exynos4210",
"samsung,exynos4212",
"samsung,exynos4412",
"samsung,exynos5",
"samsung,exynos5250",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
};
static void __init exynos_reserve(void)
{
#ifdef CONFIG_S5P_DEV_MFC
int i;
char *mfc_mem[] = {
"samsung,mfc-v5",
"samsung,mfc-v6",
"samsung,mfc-v7",
};
for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
break;
#endif
}
DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
.init_machine = exynos_dt_machine_init,
.init_late = exynos_init_late,
.dt_compat = exynos_dt_compat,
.restart = exynos_restart,
.reserve = exynos_reserve,
MACHINE_END
arch/arm/mach-exynos/mach-exynos4-dt.c deleted 100644 → 0
View file @ 2c793fa3
/*
* Samsung's EXYNOS4 flattened device tree enabled machine
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2010-2011 Linaro Ltd.
* www.linaro.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
#include <asm/mach/arch.h>
#include <plat/mfc.h>
#include "common.h"
static void __init exynos4_dt_machine_init(void)
{
exynos_cpuidle_init();
exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos4_dt_compat[] __initdata = {
"samsung,exynos4210",
"samsung,exynos4212",
"samsung,exynos4412",
NULL
};
static void __init exynos4_reserve(void)
{
#ifdef CONFIG_S5P_DEV_MFC
struct s5p_mfc_dt_meminfo mfc_mem;
/* Reserve memory for MFC only if it's available */
mfc_mem.compatible = "samsung,mfc-v5";
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
mfc_mem.lsize);
#endif
}
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
.init_machine = exynos4_dt_machine_init,
.init_late = exynos_init_late,
.dt_compat = exynos4_dt_compat,
.restart = exynos4_restart,
.reserve = exynos4_reserve,
MACHINE_END
arch/arm/mach-exynos/mach-exynos5-dt.c deleted 100644 → 0
View file @ 2c793fa3
/*
* SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/of_platform.h>
#include <linux/of_fdt.h>
#include <linux/io.h>
#include <asm/mach/arch.h>
#include <plat/mfc.h>
#include "common.h"
#include "regs-pmu.h"
static void __init exynos5_dt_machine_init(void)
{
struct device_node *i2c_np;
const char *i2c_compat = "samsung,s3c2440-i2c";
unsigned int tmp;
/*
* Exynos5's legacy i2c controller and new high speed i2c
* controller have muxed interrupt sources. By default the
* interrupts for 4-channel HS-I2C controller are enabled.
* If node for first four channels of legacy i2c controller
* are available then re-configure the interrupts via the
* system register.
*/
for_each_compatible_node(i2c_np, NULL, i2c_compat) {
if (of_device_is_available(i2c_np)) {
if (of_alias_get_id(i2c_np, "i2c") < 4) {
tmp = readl(EXYNOS5_SYS_I2C_CFG);
writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")),
EXYNOS5_SYS_I2C_CFG);
}
}
}
exynos_cpuidle_init();
exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
};
static void __init exynos5_reserve(void)
{
#ifdef CONFIG_S5P_DEV_MFC
struct s5p_mfc_dt_meminfo mfc_mem;
/* Reserve memory for MFC only if it's available */
mfc_mem.compatible = "samsung,mfc-v6";
if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
mfc_mem.lsize);
#endif
}
DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
.dt_compat = exynos5_dt_compat,
.restart = exynos5_restart,
.reserve = exynos5_reserve,
MACHINE_END
arch/arm/mach-exynos/mfc.h 0 → 100644
View file @ 9e0c42ea
/*
* Copyright (C) 2013 Samsung Electronics Co.Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __MACH_EXYNOS_MFC_H
#define __MACH_EXYNOS_MFC_H __FILE__
int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
int depth, void *data);
#endif /* __MACH_EXYNOS_MFC_H */
arch/arm/mach-exynos/regs-pmu.h
View file @ 9e0c42ea
......@@ -26,7 +26,6 @@
#define S5P_USE_STANDBY_WFI0 (1 << 16)
#define S5P_USE_STANDBY_WFE0 (1 << 24)
#define S5P_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4)
......
arch/arm/plat-samsung/include/plat/cpu.h
View file @ 9e0c42ea
......@@ -166,6 +166,10 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
# define soc_is_exynos5440() 0
#endif
#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
soc_is_exynos4412())
#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
#ifndef KHZ
......
arch/arm/plat-samsung/include/plat/mfc.h
View file @ 9e0c42ea
......@@ -32,7 +32,4 @@ struct s5p_mfc_dt_meminfo {
void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
phys_addr_t lbase, unsigned int lsize);
int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
int depth, void *data);
#endif /* __PLAT_SAMSUNG_MFC_H */
arch/arm/plat-samsung/s5p-dev-mfc.c
View file @ 9e0c42ea
......@@ -122,32 +122,35 @@ device_initcall(s5p_mfc_memory_init);
#endif
#ifdef CONFIG_OF
int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
int depth, void *data)
{
__be32 *prop;
unsigned long len;
struct s5p_mfc_dt_meminfo *mfc_mem = data;
struct s5p_mfc_dt_meminfo mfc_mem;
if (!data)
return 0;
if (!of_flat_dt_is_compatible(node, mfc_mem->compatible))
if (!of_flat_dt_is_compatible(node, data))
return 0;
prop = of_get_flat_dt_prop(node, "samsung,mfc-l", &len);
if (!prop || (len != 2 * sizeof(unsigned long)))
return 0;
mfc_mem->loff = be32_to_cpu(prop[0]);
mfc_mem->lsize = be32_to_cpu(prop[1]);
mfc_mem.loff = be32_to_cpu(prop[0]);
mfc_mem.lsize = be32_to_cpu(prop[1]);
prop = of_get_flat_dt_prop(node, "samsung,mfc-r", &len);
if (!prop || (len != 2 * sizeof(unsigned long)))
return 0;
mfc_mem->roff = be32_to_cpu(prop[0]);
mfc_mem->rsize = be32_to_cpu(prop[1]);
mfc_mem.roff = be32_to_cpu(prop[0]);
mfc_mem.rsize = be32_to_cpu(prop[1]);
s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize,
mfc_mem.loff, mfc_mem.lsize);
return 1;
}
......
drivers/clk/samsung/clk-exynos-audss.c
View file @ 9e0c42ea
......@@ -17,7 +17,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/clk/exynos-audss-clk.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
enum exynos_audss_clk_type {
TYPE_EXYNOS4210,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7