clk: renesas: div6: Restore clock state during resume
On R-Car Gen3 systems, PSCI system suspend powers down the SoC, losing clock configuration. Register an (optional) notifier to restore the DIV6 clock state during system resume. As DIV6 clocks can be picky w.r.t. modifying multiple register fields at once, restore is not implemented by blindly restoring the register value, but by using the existing cpg_div6_clock_{en,dis}able() helpers. Note that this does not yet support DIV6 clocks with multiple parents, which do not exist on R-Car Gen3 SoCs. Signed-off-by:Geert Uytterhoeven <geert+renesas@glider.be> Tested-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
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