Commit 9f92c202 authored by Saaem Rizvi's avatar Saaem Rizvi Committed by Alex Deucher

drm/amd/display: HDMI ODM Combine Policy Correction

[WHY]
Reprogramming the stream despite no changes in ODM combine mode.
Reprogramming the stream would cause intermittent black screen on
display which could only be recovered through enable/disable sequence.

[HOW]
Fixed bug where we detected a change in ODM combine mode despite ODM
combine mode being disabled. Also removed code which required stream to
be reprogrammed once a change in ODM combine mode was noticed. Lastly we
do not support dynamic ODM switching for HDMI TMDS and FRL on DCN32,
therefore we never want to change its ODM policy.
Reviewed-by: default avatarSamson Tam <Samson.Tam@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarSaaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f577c7c7
...@@ -1904,9 +1904,6 @@ bool dc_is_stream_unchanged( ...@@ -1904,9 +1904,6 @@ bool dc_is_stream_unchanged(
if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0) if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0)
return false; return false;
if (old_stream->odm_2to1_policy_applied != stream->odm_2to1_policy_applied)
return false;
return true; return true;
} }
......
...@@ -268,8 +268,6 @@ struct dc_stream_state { ...@@ -268,8 +268,6 @@ struct dc_stream_state {
bool has_non_synchronizable_pclk; bool has_non_synchronizable_pclk;
bool vblank_synchronized; bool vblank_synchronized;
struct mall_stream_config mall_stream_config; struct mall_stream_config mall_stream_config;
bool odm_2to1_policy_applied;
}; };
#define ABM_LEVEL_IMMEDIATE_DISABLE 255 #define ABM_LEVEL_IMMEDIATE_DISABLE 255
......
...@@ -1904,13 +1904,11 @@ int dcn32_populate_dml_pipes_from_context( ...@@ -1904,13 +1904,11 @@ int dcn32_populate_dml_pipes_from_context(
timing = &pipe->stream->timing; timing = &pipe->stream->timing;
pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal; pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
res_ctx->pipe_ctx[i].stream->odm_2to1_policy_applied = false; if (context->stream_count == 1 && !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal)) {
if (context->stream_count == 1 && timing->dsc_cfg.num_slices_h != 1) {
if (dc->debug.enable_single_display_2to1_odm_policy) { if (dc->debug.enable_single_display_2to1_odm_policy) {
if (!((plane_count > 2) && pipe->top_pipe)) if (!((plane_count > 2) && pipe->top_pipe))
pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
} }
res_ctx->pipe_ctx[i].stream->odm_2to1_policy_applied = true;
} }
pipe_cnt++; pipe_cnt++;
} }
......
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