ARM: dts: add HiSilicon hip04 ethernet controller resource

add the device tree binding for the HiSilicon hip04 ethernet controller
based on Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

arch/arm/boot/dts/hip04.dtsi

@@ -352,6 +352,56 @@ nand: nand@4020000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 		};
+
+		mdio {
+			compatible = "hisilicon,hip04-mdio";
+			reg = <0x28f1000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			phy0: ethernet-phy@0 {
+				compatible = "ethernet-phy-ieee802.3-c22";
+				reg = <0>;
+				marvell,reg-init = <18 0x14 0 0x8001>;
+			};
+
+			phy1: ethernet-phy@1 {
+				compatible = "ethernet-phy-ieee802.3-c22";
+				reg = <1>;
+				marvell,reg-init = <18 0x14 0 0x8001>;
+			};
+		};
+
+		ppe: ppe@28c0000 {
+			compatible = "hisilicon,hip04-ppe", "syscon";
+			reg = <0x28c0000 0x10000>;
+		};
+
+		fe: ethernet@28b0000 {
+			compatible = "hisilicon,hip04-mac";
+			reg = <0x28b0000 0x10000>;
+			interrupts = <0 413 4>;
+			phy-mode = "mii";
+			port-handle = <&ppe 31 0>;
+		};
+
+		ge0: ethernet@2800000 {
+			compatible = "hisilicon,hip04-mac";
+			reg = <0x2800000 0x10000>;
+			interrupts = <0 402 4>;
+			phy-mode = "sgmii";
+			port-handle = <&ppe 0 1>;
+			phy-handle = <&phy0>;
+		};
+
+		ge8: ethernet@2880000 {
+			compatible = "hisilicon,hip04-mac";
+			reg = <0x2880000 0x10000>;
+			interrupts = <0 410 4>;
+			phy-mode = "sgmii";
+			port-handle = <&ppe 8 2>;
+			phy-handle = <&phy1>;
+		};
 	};
 
 	etb@0,e3c42000 {