Commit a16ae2d5 authored by Anjali Singhai Jain's avatar Anjali Singhai Jain Committed by Jeff Kirsher

i40e: Do not disable queues in the Legacy/MSI Interrupt handler

The queues should never be enabled/disabled in the interrupt handler,
ICR0 interrupt enable should be the only thing that needs to be
dynamically changed in the handler.

This patch fixes that. Without this patch X722 platforms were
seeing weird ping timings when in Legacy mode since it takes
a whole lot of time for the HW/FW to re-enable queues.

Change-ID: If065afc45d81c5a19d4a94a00cd5b8f61cefc40c
Signed-off-by: default avatarAnjali Singhai Jain <anjali.singhai@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 16fd08b8
...@@ -3462,16 +3462,12 @@ static irqreturn_t i40e_intr(int irq, void *data) ...@@ -3462,16 +3462,12 @@ static irqreturn_t i40e_intr(int irq, void *data)
struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
struct i40e_q_vector *q_vector = vsi->q_vectors[0]; struct i40e_q_vector *q_vector = vsi->q_vectors[0];
/* temporarily disable queue cause for NAPI processing */ /* We do not have a way to disarm Queue causes while leaving
u32 qval = rd32(hw, I40E_QINT_RQCTL(0)); * interrupt enabled for all other causes, ideally
* interrupt should be disabled while we are in NAPI but
qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK; * this is not a performance path and napi_schedule()
wr32(hw, I40E_QINT_RQCTL(0), qval); * can deal with rescheduling.
*/
qval = rd32(hw, I40E_QINT_TQCTL(0));
qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
wr32(hw, I40E_QINT_TQCTL(0), qval);
if (!test_bit(__I40E_DOWN, &pf->state)) if (!test_bit(__I40E_DOWN, &pf->state))
napi_schedule_irqoff(&q_vector->napi); napi_schedule_irqoff(&q_vector->napi);
} }
......
...@@ -2051,19 +2051,6 @@ int i40e_napi_poll(struct napi_struct *napi, int budget) ...@@ -2051,19 +2051,6 @@ int i40e_napi_poll(struct napi_struct *napi, int budget)
if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) { if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
i40e_update_enable_itr(vsi, q_vector); i40e_update_enable_itr(vsi, q_vector);
} else { /* Legacy mode */ } else { /* Legacy mode */
struct i40e_hw *hw = &vsi->back->hw;
/* We re-enable the queue 0 cause, but
* don't worry about dynamic_enable
* because we left it on for the other
* possible interrupts during napi
*/
u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
I40E_QINT_RQCTL_CAUSE_ENA_MASK;
wr32(hw, I40E_QINT_RQCTL(0), qval);
qval = rd32(hw, I40E_QINT_TQCTL(0)) |
I40E_QINT_TQCTL_CAUSE_ENA_MASK;
wr32(hw, I40E_QINT_TQCTL(0), qval);
i40e_irq_dynamic_enable_icr0(vsi->back, false); i40e_irq_dynamic_enable_icr0(vsi->back, false);
} }
return 0; return 0;
......
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