Commit a201b6ac authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher

drm/amd/powerplay: make athub pg bit configured by pg_flags

The athub pg features enabling should be indicated by pg_flags.
Reported-by: default avatarLijo Lazar <Lijo.Lazar@amd.com>
Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c12d410f
...@@ -509,7 +509,8 @@ static int nv_common_early_init(void *handle) ...@@ -509,7 +509,8 @@ static int nv_common_early_init(void *handle)
AMD_CG_SUPPORT_BIF_LS; AMD_CG_SUPPORT_BIF_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN | adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG | AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_MMHUB; AMD_PG_SUPPORT_MMHUB |
AMD_PG_SUPPORT_ATHUB;
adev->external_rev_id = adev->rev_id + 0x1; adev->external_rev_id = adev->rev_id + 0x1;
break; break;
default: default:
......
...@@ -115,7 +115,8 @@ enum amd_powergating_state { ...@@ -115,7 +115,8 @@ enum amd_powergating_state {
#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
#define AMD_PG_SUPPORT_MMHUB (1 << 13) #define AMD_PG_SUPPORT_MMHUB (1 << 13)
#define AMD_PG_SUPPORT_VCN (1 << 14) #define AMD_PG_SUPPORT_VCN (1 << 14)
#define AMD_PG_SUPPORT_VCN_DPG (1 << 15) #define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
#define AMD_PG_SUPPORT_ATHUB (1 << 16)
enum PP_FEATURE_MASK { enum PP_FEATURE_MASK {
PP_SCLK_DPM_MASK = 0x1, PP_SCLK_DPM_MASK = 0x1,
......
...@@ -325,7 +325,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, ...@@ -325,7 +325,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
| FEATURE_MASK(FEATURE_THERMAL_BIT) | FEATURE_MASK(FEATURE_THERMAL_BIT)
| FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
| FEATURE_MASK(FEATURE_ATHUB_PG_BIT)
| FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)
| FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
...@@ -348,6 +347,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, ...@@ -348,6 +347,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
......
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