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Commit a29add8c authored by Philipp Zabel's avatar Philipp Zabel Committed by Mauro Carvalho Chehab
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media: rockchip/vpu: rename from rockchip to hantro 

Rename the driver and all relevant identifiers from Rockchip to Hantro,
as other Hantro IP based VPU implementations can be supported by the
same driver.
The RK3288 decoder is Hantro G1 based, the encoder is Hantro H1.

This patch just renames, no functional changes.
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 4e8c120d
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Showing with 1572 additions and 1129 deletions
MAINTAINERS
View file @ a29add8c
......@@ -13512,11 +13512,11 @@ S: Maintained
F: drivers/media/platform/rockchip/rga/
F: Documentation/devicetree/bindings/media/rockchip-rga.txt
ROCKCHIP VPU CODEC DRIVER
HANTRO VPU CODEC DRIVER
M: Ezequiel Garcia <ezequiel@collabora.com>
L: linux-media@vger.kernel.org
S: Maintained
F: drivers/staging/media/platform/rockchip/vpu/
F: drivers/staging/media/platform/hantro/
F: Documentation/devicetree/bindings/media/rockchip-vpu.txt
ROCKER DRIVER
......
drivers/staging/media/Kconfig
View file @ a29add8c
......@@ -26,14 +26,14 @@ source "drivers/staging/media/bcm2048/Kconfig"
source "drivers/staging/media/davinci_vpfe/Kconfig"
source "drivers/staging/media/hantro/Kconfig"
source "drivers/staging/media/imx/Kconfig"
source "drivers/staging/media/meson/vdec/Kconfig"
source "drivers/staging/media/omap4iss/Kconfig"
source "drivers/staging/media/rockchip/vpu/Kconfig"
source "drivers/staging/media/sunxi/Kconfig"
source "drivers/staging/media/tegra-vde/Kconfig"
......
drivers/staging/media/Makefile
View file @ a29add8c
......@@ -7,6 +7,6 @@ obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/
obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/
obj-$(CONFIG_VIDEO_SUNXI) += sunxi/
obj-$(CONFIG_TEGRA_VDE) += tegra-vde/
obj-$(CONFIG_VIDEO_ROCKCHIP_VPU) += rockchip/vpu/
obj-$(CONFIG_VIDEO_HANTRO) += hantro/
obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/
obj-$(CONFIG_SOC_CAMERA) += soc_camera/
drivers/staging/media/rockchip/vpu/Kconfig → drivers/staging/media/hantro/Kconfig
View file @ a29add8c
# SPDX-License-Identifier: GPL-2.0
config VIDEO_ROCKCHIP_VPU
tristate "Rockchip VPU driver"
config VIDEO_HANTRO
tristate "Hantro VPU driver"
depends on ARCH_ROCKCHIP || COMPILE_TEST
depends on VIDEO_DEV && VIDEO_V4L2 && MEDIA_CONTROLLER
depends on MEDIA_CONTROLLER_REQUEST_API
......@@ -8,7 +8,16 @@ config VIDEO_ROCKCHIP_VPU
select VIDEOBUF2_VMALLOC
select V4L2_MEM2MEM_DEV
help
Support for the Video Processing Unit present on Rockchip SoC,
which accelerates video and image encoding and decoding.
Support for the Hantro IP based Video Processing Unit present on
Rockchip SoC, which accelerates video and image encoding and
decoding.
To compile this driver as a module, choose M here: the module
will be called rockchip-vpu.
will be called hantro-vpu.
config VIDEO_HANTRO_ROCKCHIP
bool "Hantro VPU Rockchip support"
depends on VIDEO_HANTRO
depends on ARCH_ROCKCHIP || COMPILE_TEST
default y
help
Enable support for RK3288 and RK3399 SoCs.
drivers/staging/media/hantro/Makefile 0 → 100644
View file @ a29add8c
obj-$(CONFIG_VIDEO_HANTRO) += hantro-vpu.o
hantro-vpu-y += \
hantro_drv.o \
hantro_v4l2.o \
hantro_h1_jpeg_enc.o \
hantro_g1_mpeg2_dec.o \
rk3399_vpu_hw_jpeg_enc.o \
rk3399_vpu_hw_mpeg2_dec.o \
hantro_jpeg.o \
hantro_mpeg2.o
hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \
rk3288_vpu_hw.o \
rk3399_vpu_hw.o
drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c 0 → 100644
View file @ a29add8c
// SPDX-License-Identifier: GPL-2.0
/*
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
*/
#include <asm/unaligned.h>
#include <linux/bitfield.h>
#include <media/v4l2-mem2mem.h>
#include "hantro.h"
#include "hantro_hw.h"
#define G1_SWREG(nr) ((nr) * 4)
#define G1_REG_RLC_VLC_BASE G1_SWREG(12)
#define G1_REG_DEC_OUT_BASE G1_SWREG(13)
#define G1_REG_REFER0_BASE G1_SWREG(14)
#define G1_REG_REFER1_BASE G1_SWREG(15)
#define G1_REG_REFER2_BASE G1_SWREG(16)
#define G1_REG_REFER3_BASE G1_SWREG(17)
#define G1_REG_QTABLE_BASE G1_SWREG(40)
#define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0)
#define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24))
#define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0)
#define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0)
#define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0)
#define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0)
#define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0)
#define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0)
#define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11))
#define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0)
#define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0)
#define G1_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(8) : 0)
#define G1_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(6) : 0)
#define G1_REG_DEC_SCMD_DIS(v) ((v) ? BIT(5) : 0)
#define G1_REG_DEC_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0))
#define G1_REG_DEC_MODE(v) (((v) << 28) & GENMASK(31, 28))
#define G1_REG_RLC_MODE_E(v) ((v) ? BIT(27) : 0)
#define G1_REG_PIC_INTERLACE_E(v) ((v) ? BIT(23) : 0)
#define G1_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(22) : 0)
#define G1_REG_PIC_B_E(v) ((v) ? BIT(21) : 0)
#define G1_REG_PIC_INTER_E(v) ((v) ? BIT(20) : 0)
#define G1_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(19) : 0)
#define G1_REG_FWD_INTERLACE_E(v) ((v) ? BIT(18) : 0)
#define G1_REG_FILTERING_DIS(v) ((v) ? BIT(14) : 0)
#define G1_REG_WRITE_MVS_E(v) ((v) ? BIT(12) : 0)
#define G1_REG_DEC_AXI_WR_ID(v) (((v) << 0) & GENMASK(7, 0))
#define G1_REG_PIC_MB_WIDTH(v) (((v) << 23) & GENMASK(31, 23))
#define G1_REG_PIC_MB_HEIGHT_P(v) (((v) << 11) & GENMASK(18, 11))
#define G1_REG_ALT_SCAN_E(v) ((v) ? BIT(6) : 0)
#define G1_REG_TOPFIELDFIRST_E(v) ((v) ? BIT(5) : 0)
#define G1_REG_STRM_START_BIT(v) (((v) << 26) & GENMASK(31, 26))
#define G1_REG_QSCALE_TYPE(v) ((v) ? BIT(24) : 0)
#define G1_REG_CON_MV_E(v) ((v) ? BIT(4) : 0)
#define G1_REG_INTRA_DC_PREC(v) (((v) << 2) & GENMASK(3, 2))
#define G1_REG_INTRA_VLC_TAB(v) ((v) ? BIT(1) : 0)
#define G1_REG_FRAME_PRED_DCT(v) ((v) ? BIT(0) : 0)
#define G1_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25))
#define G1_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0))
#define G1_REG_ALT_SCAN_FLAG_E(v) ((v) ? BIT(19) : 0)
#define G1_REG_FCODE_FWD_HOR(v) (((v) << 15) & GENMASK(18, 15))
#define G1_REG_FCODE_FWD_VER(v) (((v) << 11) & GENMASK(14, 11))
#define G1_REG_FCODE_BWD_HOR(v) (((v) << 7) & GENMASK(10, 7))
#define G1_REG_FCODE_BWD_VER(v) (((v) << 3) & GENMASK(6, 3))
#define G1_REG_MV_ACCURACY_FWD(v) ((v) ? BIT(2) : 0)
#define G1_REG_MV_ACCURACY_BWD(v) ((v) ? BIT(1) : 0)
#define G1_REG_STARTMB_X(v) (((v) << 23) & GENMASK(31, 23))
#define G1_REG_STARTMB_Y(v) (((v) << 15) & GENMASK(22, 15))
#define G1_REG_APF_THRESHOLD(v) (((v) << 0) & GENMASK(13, 0))
#define PICT_TOP_FIELD 1
#define PICT_BOTTOM_FIELD 2
#define PICT_FRAME 3
static void
hantro_g1_mpeg2_dec_set_quantization(struct hantro_dev *vpu,
struct hantro_ctx *ctx)
{
struct v4l2_ctrl_mpeg2_quantization *quantization;
quantization = hantro_get_ctrl(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu,
quantization);
vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma,
G1_REG_QTABLE_BASE);
}
static void
hantro_g1_mpeg2_dec_set_buffers(struct hantro_dev *vpu, struct hantro_ctx *ctx,
struct vb2_buffer *src_buf,
struct vb2_buffer *dst_buf,
const struct v4l2_mpeg2_sequence *sequence,
const struct v4l2_mpeg2_picture *picture,
const struct v4l2_ctrl_mpeg2_slice_params *slice_params)
{
dma_addr_t forward_addr = 0, backward_addr = 0;
dma_addr_t current_addr, addr;
struct vb2_queue *vq;
vq = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
switch (picture->picture_coding_type) {
case V4L2_MPEG2_PICTURE_CODING_TYPE_B:
backward_addr = hantro_get_ref(vq,
slice_params->backward_ref_ts);
/* fall-through */
case V4L2_MPEG2_PICTURE_CODING_TYPE_P:
forward_addr = hantro_get_ref(vq,
slice_params->forward_ref_ts);
}
/* Source bitstream buffer */
addr = vb2_dma_contig_plane_dma_addr(src_buf, 0);
vdpu_write_relaxed(vpu, addr, G1_REG_RLC_VLC_BASE);
/* Destination frame buffer */
addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
current_addr = addr;
if (picture->picture_structure == PICT_BOTTOM_FIELD)
addr += ALIGN(ctx->dst_fmt.width, 16);
vdpu_write_relaxed(vpu, addr, G1_REG_DEC_OUT_BASE);
if (!forward_addr)
forward_addr = current_addr;
if (!backward_addr)
backward_addr = current_addr;
/* Set forward ref frame (top/bottom field) */
if (picture->picture_structure == PICT_FRAME ||
picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B ||
(picture->picture_structure == PICT_TOP_FIELD &&
picture->top_field_first) ||
(picture->picture_structure == PICT_BOTTOM_FIELD &&
!picture->top_field_first)) {
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
} else if (picture->picture_structure == PICT_TOP_FIELD) {
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER1_BASE);
} else if (picture->picture_structure == PICT_BOTTOM_FIELD) {
vdpu_write_relaxed(vpu, current_addr, G1_REG_REFER0_BASE);
vdpu_write_relaxed(vpu, forward_addr, G1_REG_REFER1_BASE);
}
/* Set backward ref frame (top/bottom field) */
vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER2_BASE);
vdpu_write_relaxed(vpu, backward_addr, G1_REG_REFER3_BASE);
}
void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx)
{
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
const struct v4l2_mpeg2_sequence *sequence;
const struct v4l2_mpeg2_picture *picture;
u32 reg;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
/* Apply request controls if any */
v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
&ctx->ctrl_handler);
slice_params = hantro_get_ctrl(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
sequence = &slice_params->sequence;
picture = &slice_params->picture;
reg = G1_REG_DEC_AXI_RD_ID(0) |
G1_REG_DEC_TIMEOUT_E(1) |
G1_REG_DEC_STRSWAP32_E(1) |
G1_REG_DEC_STRENDIAN_E(1) |
G1_REG_DEC_INSWAP32_E(1) |
G1_REG_DEC_OUTSWAP32_E(1) |
G1_REG_DEC_DATA_DISC_E(0) |
G1_REG_DEC_LATENCY(0) |
G1_REG_DEC_CLK_GATE_E(1) |
G1_REG_DEC_IN_ENDIAN(1) |
G1_REG_DEC_OUT_ENDIAN(1) |
G1_REG_DEC_ADV_PRE_DIS(0) |
G1_REG_DEC_SCMD_DIS(0) |
G1_REG_DEC_MAX_BURST(16);
vdpu_write_relaxed(vpu, reg, G1_SWREG(2));
reg = G1_REG_DEC_MODE(5) |
G1_REG_RLC_MODE_E(0) |
G1_REG_PIC_INTERLACE_E(!sequence->progressive_sequence) |
G1_REG_PIC_FIELDMODE_E(picture->picture_structure != PICT_FRAME) |
G1_REG_PIC_B_E(picture->picture_coding_type == V4L2_MPEG2_PICTURE_CODING_TYPE_B) |
G1_REG_PIC_INTER_E(picture->picture_coding_type != V4L2_MPEG2_PICTURE_CODING_TYPE_I) |
G1_REG_PIC_TOPFIELD_E(picture->picture_structure == PICT_TOP_FIELD) |
G1_REG_FWD_INTERLACE_E(0) |
G1_REG_FILTERING_DIS(1) |
G1_REG_WRITE_MVS_E(0) |
G1_REG_DEC_AXI_WR_ID(0);
vdpu_write_relaxed(vpu, reg, G1_SWREG(3));
reg = G1_REG_PIC_MB_WIDTH(MPEG2_MB_WIDTH(ctx->dst_fmt.width)) |
G1_REG_PIC_MB_HEIGHT_P(MPEG2_MB_HEIGHT(ctx->dst_fmt.height)) |
G1_REG_ALT_SCAN_E(picture->alternate_scan) |
G1_REG_TOPFIELDFIRST_E(picture->top_field_first);
vdpu_write_relaxed(vpu, reg, G1_SWREG(4));
reg = G1_REG_STRM_START_BIT(slice_params->data_bit_offset) |
G1_REG_QSCALE_TYPE(picture->q_scale_type) |
G1_REG_CON_MV_E(picture->concealment_motion_vectors) |
G1_REG_INTRA_DC_PREC(picture->intra_dc_precision) |
G1_REG_INTRA_VLC_TAB(picture->intra_vlc_format) |
G1_REG_FRAME_PRED_DCT(picture->frame_pred_frame_dct);
vdpu_write_relaxed(vpu, reg, G1_SWREG(5));
reg = G1_REG_INIT_QP(1) |
G1_REG_STREAM_LEN(slice_params->bit_size >> 3);
vdpu_write_relaxed(vpu, reg, G1_SWREG(6));
reg = G1_REG_ALT_SCAN_FLAG_E(picture->alternate_scan) |
G1_REG_FCODE_FWD_HOR(picture->f_code[0][0]) |
G1_REG_FCODE_FWD_VER(picture->f_code[0][1]) |
G1_REG_FCODE_BWD_HOR(picture->f_code[1][0]) |
G1_REG_FCODE_BWD_VER(picture->f_code[1][1]) |
G1_REG_MV_ACCURACY_FWD(1) |
G1_REG_MV_ACCURACY_BWD(1);
vdpu_write_relaxed(vpu, reg, G1_SWREG(18));
reg = G1_REG_STARTMB_X(0) |
G1_REG_STARTMB_Y(0);
vdpu_write_relaxed(vpu, reg, G1_SWREG(48));
reg = G1_REG_APF_THRESHOLD(8);
vdpu_write_relaxed(vpu, reg, G1_SWREG(55));
hantro_g1_mpeg2_dec_set_quantization(vpu, ctx);
hantro_g1_mpeg2_dec_set_buffers(vpu, ctx, &src_buf->vb2_buf,
&dst_buf->vb2_buf,
sequence, picture, slice_params);
/* Controls no longer in-use, we can complete them */
v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
&ctx->ctrl_handler);
/* Kick the watchdog and start decoding */
schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
reg = G1_REG_DEC_E(1);
vdpu_write(vpu, reg, G1_SWREG(1));
}
drivers/staging/media/hantro/hantro_g1_regs.h 0 → 100644
View file @ a29add8c
This diff is collapsed.
drivers/staging/media/rockchip/vpu/rk3288_vpu_hw_jpeg_enc.c → drivers/staging/media/hantro/hantro_h1_jpeg_enc.c
View file @ a29add8c
// SPDX-License-Identifier: GPL-2.0
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
*/
#include <asm/unaligned.h>
#include <media/v4l2-mem2mem.h>
#include "rockchip_vpu_jpeg.h"
#include "rockchip_vpu.h"
#include "rockchip_vpu_v4l2.h"
#include "rockchip_vpu_hw.h"
#include "rk3288_vpu_regs.h"
#include "hantro_jpeg.h"
#include "hantro.h"
#include "hantro_v4l2.h"
#include "hantro_hw.h"
#include "hantro_h1_regs.h"
#define VEPU_JPEG_QUANT_TABLE_COUNT 16
#define H1_JPEG_QUANT_TABLE_COUNT 16
static void rk3288_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx)
static void hantro_h1_set_src_img_ctrl(struct hantro_dev *vpu,
struct hantro_ctx *ctx)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
u32 reg;
reg = VEPU_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width)
| VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(0)
| VEPU_REG_IN_IMG_CTRL_OVRFLB_D4(0)
| VEPU_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
vepu_write_relaxed(vpu, reg, VEPU_REG_IN_IMG_CTRL);
reg = H1_REG_IN_IMG_CTRL_ROW_LEN(pix_fmt->width)
| H1_REG_IN_IMG_CTRL_OVRFLR_D4(0)
| H1_REG_IN_IMG_CTRL_OVRFLB_D4(0)
| H1_REG_IN_IMG_CTRL_FMT(ctx->vpu_src_fmt->enc_fmt);
vepu_write_relaxed(vpu, reg, H1_REG_IN_IMG_CTRL);
}
static void rk3288_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx,
struct vb2_buffer *src_buf)
static void hantro_h1_jpeg_enc_set_buffers(struct hantro_dev *vpu,
struct hantro_ctx *ctx,
struct vb2_buffer *src_buf)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
dma_addr_t src[3];
......@@ -38,50 +38,50 @@ static void rk3288_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu,
WARN_ON(pix_fmt->num_planes > 3);
vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.dma,
VEPU_REG_ADDR_OUTPUT_STREAM);
H1_REG_ADDR_OUTPUT_STREAM);
vepu_write_relaxed(vpu, ctx->jpeg_enc.bounce_buffer.size,
VEPU_REG_STR_BUF_LIMIT);
H1_REG_STR_BUF_LIMIT);
if (pix_fmt->num_planes == 1) {
src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
/* single plane formats we supported are all interlaced */
vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
} else if (pix_fmt->num_planes == 2) {
src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);
vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);
} else {
src[0] = vb2_dma_contig_plane_dma_addr(src_buf, 0);
src[1] = vb2_dma_contig_plane_dma_addr(src_buf, 1);
src[2] = vb2_dma_contig_plane_dma_addr(src_buf, 2);
vepu_write_relaxed(vpu, src[0], VEPU_REG_ADDR_IN_PLANE_0);
vepu_write_relaxed(vpu, src[1], VEPU_REG_ADDR_IN_PLANE_1);
vepu_write_relaxed(vpu, src[2], VEPU_REG_ADDR_IN_PLANE_2);
vepu_write_relaxed(vpu, src[0], H1_REG_ADDR_IN_PLANE_0);
vepu_write_relaxed(vpu, src[1], H1_REG_ADDR_IN_PLANE_1);
vepu_write_relaxed(vpu, src[2], H1_REG_ADDR_IN_PLANE_2);
}
}
static void
rk3288_vpu_jpeg_enc_set_qtable(struct rockchip_vpu_dev *vpu,
unsigned char *luma_qtable,
unsigned char *chroma_qtable)
hantro_h1_jpeg_enc_set_qtable(struct hantro_dev *vpu,
unsigned char *luma_qtable,
unsigned char *chroma_qtable)
{
u32 reg, i;
for (i = 0; i < VEPU_JPEG_QUANT_TABLE_COUNT; i++) {
for (i = 0; i < H1_JPEG_QUANT_TABLE_COUNT; i++) {
reg = get_unaligned_be32(&luma_qtable[i]);
vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_LUMA_QUAT(i));
vepu_write_relaxed(vpu, reg, H1_REG_JPEG_LUMA_QUAT(i));
reg = get_unaligned_be32(&chroma_qtable[i]);
vepu_write_relaxed(vpu, reg, VEPU_REG_JPEG_CHROMA_QUAT(i));
vepu_write_relaxed(vpu, reg, H1_REG_JPEG_CHROMA_QUAT(i));
}
}
void rk3288_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx)
void hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct rockchip_vpu_jpeg_ctx jpeg_ctx;
struct hantro_jpeg_ctx jpeg_ctx;
u32 reg;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
......@@ -92,34 +92,34 @@ void rk3288_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx)
jpeg_ctx.width = ctx->dst_fmt.width;
jpeg_ctx.height = ctx->dst_fmt.height;
jpeg_ctx.quality = ctx->jpeg_quality;
rockchip_vpu_jpeg_header_assemble(&jpeg_ctx);
hantro_jpeg_header_assemble(&jpeg_ctx);
/* Switch to JPEG encoder mode before writing registers */
vepu_write_relaxed(vpu, VEPU_REG_ENC_CTRL_ENC_MODE_JPEG,
VEPU_REG_ENC_CTRL);
rk3288_vpu_set_src_img_ctrl(vpu, ctx);
rk3288_vpu_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);
rk3288_vpu_jpeg_enc_set_qtable(vpu,
rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 0),
rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 1));
reg = VEPU_REG_AXI_CTRL_OUTPUT_SWAP16
| VEPU_REG_AXI_CTRL_INPUT_SWAP16
| VEPU_REG_AXI_CTRL_BURST_LEN(16)
| VEPU_REG_AXI_CTRL_OUTPUT_SWAP32
| VEPU_REG_AXI_CTRL_INPUT_SWAP32
| VEPU_REG_AXI_CTRL_OUTPUT_SWAP8
| VEPU_REG_AXI_CTRL_INPUT_SWAP8;
vepu_write_relaxed(vpu, H1_REG_ENC_CTRL_ENC_MODE_JPEG,
H1_REG_ENC_CTRL);
hantro_h1_set_src_img_ctrl(vpu, ctx);
hantro_h1_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);
hantro_h1_jpeg_enc_set_qtable(vpu,
hantro_jpeg_get_qtable(&jpeg_ctx, 0),
hantro_jpeg_get_qtable(&jpeg_ctx, 1));
reg = H1_REG_AXI_CTRL_OUTPUT_SWAP16
| H1_REG_AXI_CTRL_INPUT_SWAP16
| H1_REG_AXI_CTRL_BURST_LEN(16)
| H1_REG_AXI_CTRL_OUTPUT_SWAP32
| H1_REG_AXI_CTRL_INPUT_SWAP32
| H1_REG_AXI_CTRL_OUTPUT_SWAP8
| H1_REG_AXI_CTRL_INPUT_SWAP8;
/* Make sure that all registers are written at this point. */
vepu_write(vpu, reg, VEPU_REG_AXI_CTRL);
vepu_write(vpu, reg, H1_REG_AXI_CTRL);
reg = VEPU_REG_ENC_CTRL_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width))
| VEPU_REG_ENC_CTRL_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height))
| VEPU_REG_ENC_CTRL_ENC_MODE_JPEG
| VEPU_REG_ENC_PIC_INTRA
| VEPU_REG_ENC_CTRL_EN_BIT;
reg = H1_REG_ENC_CTRL_WIDTH(JPEG_MB_WIDTH(ctx->src_fmt.width))
| H1_REG_ENC_CTRL_HEIGHT(JPEG_MB_HEIGHT(ctx->src_fmt.height))
| H1_REG_ENC_CTRL_ENC_MODE_JPEG
| H1_REG_ENC_PIC_INTRA
| H1_REG_ENC_CTRL_EN_BIT;
/* Kick the watchdog and start encoding */
schedule_delayed_work(&vpu->watchdog_work, msecs_to_jiffies(2000));
vepu_write(vpu, reg, VEPU_REG_ENC_CTRL);
vepu_write(vpu, reg, H1_REG_ENC_CTRL);
}
drivers/staging/media/hantro/hantro_h1_regs.h 0 → 100644
View file @ a29add8c
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Hantro VPU codec driver
*
* Copyright 2018 Google LLC.
* Tomasz Figa <tfiga@chromium.org>
*/
#ifndef HANTRO_H1_REGS_H_
#define HANTRO_H1_REGS_H_
/* Encoder registers. */
#define H1_REG_INTERRUPT 0x004
#define H1_REG_INTERRUPT_FRAME_RDY BIT(2)
#define H1_REG_INTERRUPT_DIS_BIT BIT(1)
#define H1_REG_INTERRUPT_BIT BIT(0)
#define H1_REG_AXI_CTRL 0x008
#define H1_REG_AXI_CTRL_OUTPUT_SWAP16 BIT(15)
#define H1_REG_AXI_CTRL_INPUT_SWAP16 BIT(14)
#define H1_REG_AXI_CTRL_BURST_LEN(x) ((x) << 8)
#define H1_REG_AXI_CTRL_GATE_BIT BIT(4)
#define H1_REG_AXI_CTRL_OUTPUT_SWAP32 BIT(3)
#define H1_REG_AXI_CTRL_INPUT_SWAP32 BIT(2)
#define H1_REG_AXI_CTRL_OUTPUT_SWAP8 BIT(1)
#define H1_REG_AXI_CTRL_INPUT_SWAP8 BIT(0)
#define H1_REG_ADDR_OUTPUT_STREAM 0x014
#define H1_REG_ADDR_OUTPUT_CTRL 0x018
#define H1_REG_ADDR_REF_LUMA 0x01c
#define H1_REG_ADDR_REF_CHROMA 0x020
#define H1_REG_ADDR_REC_LUMA 0x024
#define H1_REG_ADDR_REC_CHROMA 0x028
#define H1_REG_ADDR_IN_PLANE_0 0x02c
#define H1_REG_ADDR_IN_PLANE_1 0x030
#define H1_REG_ADDR_IN_PLANE_2 0x034
#define H1_REG_ENC_CTRL 0x038
#define H1_REG_ENC_CTRL_TIMEOUT_EN BIT(31)
#define H1_REG_ENC_CTRL_NAL_MODE_BIT BIT(29)
#define H1_REG_ENC_CTRL_WIDTH(w) ((w) << 19)
#define H1_REG_ENC_CTRL_HEIGHT(h) ((h) << 10)
#define H1_REG_ENC_PIC_INTER (0x0 << 3)
#define H1_REG_ENC_PIC_INTRA (0x1 << 3)
#define H1_REG_ENC_PIC_MVCINTER (0x2 << 3)
#define H1_REG_ENC_CTRL_ENC_MODE_H264 (0x3 << 1)
#define H1_REG_ENC_CTRL_ENC_MODE_JPEG (0x2 << 1)
#define H1_REG_ENC_CTRL_ENC_MODE_VP8 (0x1 << 1)
#define H1_REG_ENC_CTRL_EN_BIT BIT(0)
#define H1_REG_IN_IMG_CTRL 0x03c
#define H1_REG_IN_IMG_CTRL_ROW_LEN(x) ((x) << 12)
#define H1_REG_IN_IMG_CTRL_OVRFLR_D4(x) ((x) << 10)
#define H1_REG_IN_IMG_CTRL_OVRFLB_D4(x) ((x) << 6)
#define H1_REG_IN_IMG_CTRL_FMT(x) ((x) << 2)
#define H1_REG_ENC_CTRL0 0x040
#define H1_REG_ENC_CTRL0_INIT_QP(x) ((x) << 26)
#define H1_REG_ENC_CTRL0_SLICE_ALPHA(x) ((x) << 22)
#define H1_REG_ENC_CTRL0_SLICE_BETA(x) ((x) << 18)
#define H1_REG_ENC_CTRL0_CHROMA_QP_OFFSET(x) ((x) << 13)
#define H1_REG_ENC_CTRL0_FILTER_DIS(x) ((x) << 5)
#define H1_REG_ENC_CTRL0_IDR_PICID(x) ((x) << 1)
#define H1_REG_ENC_CTRL0_CONSTR_INTRA_PRED BIT(0)
#define H1_REG_ENC_CTRL1 0x044
#define H1_REG_ENC_CTRL1_PPS_ID(x) ((x) << 24)
#define H1_REG_ENC_CTRL1_INTRA_PRED_MODE(x) ((x) << 16)
#define H1_REG_ENC_CTRL1_FRAME_NUM(x) ((x))
#define H1_REG_ENC_CTRL2 0x048
#define H1_REG_ENC_CTRL2_DEBLOCKING_FILETER_MODE(x) ((x) << 30)
#define H1_REG_ENC_CTRL2_H264_SLICE_SIZE(x) ((x) << 23)
#define H1_REG_ENC_CTRL2_DISABLE_QUARTER_PIXMV BIT(22)
#define H1_REG_ENC_CTRL2_TRANS8X8_MODE_EN BIT(21)
#define H1_REG_ENC_CTRL2_CABAC_INIT_IDC(x) ((x) << 19)
#define H1_REG_ENC_CTRL2_ENTROPY_CODING_MODE BIT(18)
#define H1_REG_ENC_CTRL2_H264_INTER4X4_MODE BIT(17)
#define H1_REG_ENC_CTRL2_H264_STREAM_MODE BIT(16)
#define H1_REG_ENC_CTRL2_INTRA16X16_MODE(x) ((x))
#define H1_REG_ENC_CTRL3 0x04c
#define H1_REG_ENC_CTRL3_MUTIMV_EN BIT(30)
#define H1_REG_ENC_CTRL3_MV_PENALTY_1_4P(x) ((x) << 20)
#define H1_REG_ENC_CTRL3_MV_PENALTY_4P(x) ((x) << 10)
#define H1_REG_ENC_CTRL3_MV_PENALTY_1P(x) ((x))
#define H1_REG_ENC_CTRL4 0x050
#define H1_REG_ENC_CTRL4_MV_PENALTY_16X8_8X16(x) ((x) << 20)
#define H1_REG_ENC_CTRL4_MV_PENALTY_8X8(x) ((x) << 10)
#define H1_REG_ENC_CTRL4_8X4_4X8(x) ((x))
#define H1_REG_ENC_CTRL5 0x054
#define H1_REG_ENC_CTRL5_MACROBLOCK_PENALTY(x) ((x) << 24)
#define H1_REG_ENC_CTRL5_COMPLETE_SLICES(x) ((x) << 16)
#define H1_REG_ENC_CTRL5_INTER_MODE(x) ((x))
#define H1_REG_STR_HDR_REM_MSB 0x058
#define H1_REG_STR_HDR_REM_LSB 0x05c
#define H1_REG_STR_BUF_LIMIT 0x060
#define H1_REG_MAD_CTRL 0x064
#define H1_REG_MAD_CTRL_QP_ADJUST(x) ((x) << 28)
#define H1_REG_MAD_CTRL_MAD_THREDHOLD(x) ((x) << 22)
#define H1_REG_MAD_CTRL_QP_SUM_DIV2(x) ((x))
#define H1_REG_ADDR_VP8_PROB_CNT 0x068
#define H1_REG_QP_VAL 0x06c
#define H1_REG_QP_VAL_LUM(x) ((x) << 26)
#define H1_REG_QP_VAL_MAX(x) ((x) << 20)
#define H1_REG_QP_VAL_MIN(x) ((x) << 14)
#define H1_REG_QP_VAL_CHECKPOINT_DISTAN(x) ((x))
#define H1_REG_VP8_QP_VAL(i) (0x06c + ((i) * 0x4))
#define H1_REG_CHECKPOINT(i) (0x070 + ((i) * 0x4))
#define H1_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff))
#define H1_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16)
#define H1_REG_CHECKPOINT_RESULT(x) ((((x) >> (16 - 16 \
* (i & 1))) & 0xffff) \
* 32)
#define H1_REG_CHKPT_WORD_ERR(i) (0x084 + ((i) * 0x4))
#define H1_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff))
#define H1_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16)
#define H1_REG_VP8_BOOL_ENC 0x08c
#define H1_REG_CHKPT_DELTA_QP 0x090
#define H1_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0)
#define H1_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4)
#define H1_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8)
#define H1_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12)
#define H1_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16)
#define H1_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20)
#define H1_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24)
#define H1_REG_VP8_CTRL0 0x090
#define H1_REG_RLC_CTRL 0x094
#define H1_REG_RLC_CTRL_STR_OFFS_SHIFT 23
#define H1_REG_RLC_CTRL_STR_OFFS_MASK (0x3f << 23)
#define H1_REG_RLC_CTRL_RLC_SUM(x) ((x))
#define H1_REG_MB_CTRL 0x098
#define H1_REG_MB_CNT_OUT(x) (((x) & 0xffff))
#define H1_REG_MB_CNT_SET(x) (((x) & 0xffff) << 16)
#define H1_REG_ADDR_NEXT_PIC 0x09c
#define H1_REG_JPEG_LUMA_QUAT(i) (0x100 + ((i) * 0x4))
#define H1_REG_JPEG_CHROMA_QUAT(i) (0x140 + ((i) * 0x4))
#define H1_REG_STABILIZATION_OUTPUT 0x0A0
#define H1_REG_ADDR_CABAC_TBL 0x0cc
#define H1_REG_ADDR_MV_OUT 0x0d0
#define H1_REG_RGB_YUV_COEFF(i) (0x0d4 + ((i) * 0x4))
#define H1_REG_RGB_MASK_MSB 0x0dc
#define H1_REG_INTRA_AREA_CTRL 0x0e0
#define H1_REG_CIR_INTRA_CTRL 0x0e4
#define H1_REG_INTRA_SLICE_BITMAP(i) (0x0e8 + ((i) * 0x4))
#define H1_REG_ADDR_VP8_DCT_PART(i) (0x0e8 + ((i) * 0x4))
#define H1_REG_FIRST_ROI_AREA 0x0f0
#define H1_REG_SECOND_ROI_AREA 0x0f4
#define H1_REG_MVC_CTRL 0x0f8
#define H1_REG_MVC_CTRL_MV16X16_FAVOR(x) ((x) << 28)
#define H1_REG_VP8_INTRA_PENALTY(i) (0x100 + ((i) * 0x4))
#define H1_REG_ADDR_VP8_SEG_MAP 0x11c
#define H1_REG_VP8_SEG_QP(i) (0x120 + ((i) * 0x4))
#define H1_REG_DMV_4P_1P_PENALTY(i) (0x180 + ((i) * 0x4))
#define H1_REG_DMV_4P_1P_PENALTY_BIT(x, i) ((x) << (i) * 8)
#define H1_REG_DMV_QPEL_PENALTY(i) (0x200 + ((i) * 0x4))
#define H1_REG_DMV_QPEL_PENALTY_BIT(x, i) ((x) << (i) * 8)
#define H1_REG_VP8_CTRL1 0x280
#define H1_REG_VP8_BIT_COST_GOLDEN 0x284
#define H1_REG_VP8_LOOP_FLT_DELTA(i) (0x288 + ((i) * 0x4))
#endif /* HANTRO_H1_REGS_H_ */
drivers/staging/media/rockchip/vpu/rockchip_vpu_hw.h → drivers/staging/media/hantro/hantro_hw.h
View file @ a29add8c
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright 2018 Google LLC.
* Tomasz Figa <tfiga@chromium.org>
*/
#ifndef ROCKCHIP_VPU_HW_H_
#define ROCKCHIP_VPU_HW_H_
#ifndef HANTRO_HW_H_
#define HANTRO_HW_H_
#include <linux/interrupt.h>
#include <linux/v4l2-controls.h>
#include <media/mpeg2-ctrls.h>
#include <media/videobuf2-core.h>
struct rockchip_vpu_dev;
struct rockchip_vpu_ctx;
struct rockchip_vpu_buf;
struct rockchip_vpu_variant;
struct hantro_dev;
struct hantro_ctx;
struct hantro_buf;
struct hantro_variant;
/**
* struct rockchip_vpu_aux_buf - auxiliary DMA buffer for hardware data
* struct hantro_aux_buf - auxiliary DMA buffer for hardware data
* @cpu: CPU pointer to the buffer.
* @dma: DMA address of the buffer.
* @size: Size of the buffer.
*/
struct rockchip_vpu_aux_buf {
struct hantro_aux_buf {
void *cpu;
dma_addr_t dma;
size_t size;
};
/**
* struct rockchip_vpu_jpeg_enc_hw_ctx
* struct hantro_jpeg_enc_hw_ctx
* @bounce_buffer: Bounce buffer
*/
struct rockchip_vpu_jpeg_enc_hw_ctx {
struct rockchip_vpu_aux_buf bounce_buffer;
struct hantro_jpeg_enc_hw_ctx {
struct hantro_aux_buf bounce_buffer;
};
/**
* struct rockchip_vpu_mpeg2_dec_hw_ctx
* struct hantro_mpeg2_dec_hw_ctx
* @qtable: Quantization table
*/
struct rockchip_vpu_mpeg2_dec_hw_ctx {
struct rockchip_vpu_aux_buf qtable;
struct hantro_mpeg2_dec_hw_ctx {
struct hantro_aux_buf qtable;
};
/**
* struct rockchip_vpu_codec_ops - codec mode specific operations
* struct hantro_codec_ops - codec mode specific operations
*
* @init: If needed, can be used for initialization.
* Optional and called from process context.
......@@ -60,43 +60,43 @@ struct rockchip_vpu_mpeg2_dec_hw_ctx {
* @done: Read back processing results and additional data from hardware.
* @reset: Reset the hardware in case of a timeout.
*/
struct rockchip_vpu_codec_ops {
int (*init)(struct rockchip_vpu_ctx *ctx);
void (*exit)(struct rockchip_vpu_ctx *ctx);
void (*run)(struct rockchip_vpu_ctx *ctx);
void (*done)(struct rockchip_vpu_ctx *ctx, enum vb2_buffer_state);
void (*reset)(struct rockchip_vpu_ctx *ctx);
struct hantro_codec_ops {
int (*init)(struct hantro_ctx *ctx);
void (*exit)(struct hantro_ctx *ctx);
void (*run)(struct hantro_ctx *ctx);
void (*done)(struct hantro_ctx *ctx, enum vb2_buffer_state);
void (*reset)(struct hantro_ctx *ctx);
};
/**
* enum rockchip_vpu_enc_fmt - source format ID for hardware registers.
* enum hantro_enc_fmt - source format ID for hardware registers.
*/
enum rockchip_vpu_enc_fmt {
enum hantro_enc_fmt {
RK3288_VPU_ENC_FMT_YUV420P = 0,
RK3288_VPU_ENC_FMT_YUV420SP = 1,
RK3288_VPU_ENC_FMT_YUYV422 = 2,
RK3288_VPU_ENC_FMT_UYVY422 = 3,
};
extern const struct rockchip_vpu_variant rk3399_vpu_variant;
extern const struct rockchip_vpu_variant rk3288_vpu_variant;
extern const struct hantro_variant rk3399_vpu_variant;
extern const struct hantro_variant rk3328_vpu_variant;
extern const struct hantro_variant rk3288_vpu_variant;
void rockchip_vpu_watchdog(struct work_struct *work);
void rockchip_vpu_run(struct rockchip_vpu_ctx *ctx);
void rockchip_vpu_irq_done(struct rockchip_vpu_dev *vpu,
unsigned int bytesused,
enum vb2_buffer_state result);
void hantro_watchdog(struct work_struct *work);
void hantro_run(struct hantro_ctx *ctx);
void hantro_irq_done(struct hantro_dev *vpu, unsigned int bytesused,
enum vb2_buffer_state result);
void rk3288_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx);
void rk3399_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx);
int rockchip_vpu_jpeg_enc_init(struct rockchip_vpu_ctx *ctx);
void rockchip_vpu_jpeg_enc_exit(struct rockchip_vpu_ctx *ctx);
void hantro_h1_jpeg_enc_run(struct hantro_ctx *ctx);
void rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx);
int hantro_jpeg_enc_init(struct hantro_ctx *ctx);
void hantro_jpeg_enc_exit(struct hantro_ctx *ctx);
void rk3288_vpu_mpeg2_dec_run(struct rockchip_vpu_ctx *ctx);
void rk3399_vpu_mpeg2_dec_run(struct rockchip_vpu_ctx *ctx);
void rockchip_vpu_mpeg2_dec_copy_qtable(u8 *qtable,
void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx);
void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
const struct v4l2_ctrl_mpeg2_quantization *ctrl);
int rockchip_vpu_mpeg2_dec_init(struct rockchip_vpu_ctx *ctx);
void rockchip_vpu_mpeg2_dec_exit(struct rockchip_vpu_ctx *ctx);
int hantro_mpeg2_dec_init(struct hantro_ctx *ctx);
void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx);
#endif /* ROCKCHIP_VPU_HW_H_ */
#endif /* HANTRO_HW_H_ */
drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.c → drivers/staging/media/hantro/hantro_jpeg.c
View file @ a29add8c
......@@ -9,8 +9,8 @@
#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include "rockchip_vpu_jpeg.h"
#include "rockchip_vpu.h"
#include "hantro_jpeg.h"
#include "hantro.h"
#define LUMA_QUANT_OFF 7
#define CHROMA_QUANT_OFF 72
......@@ -118,7 +118,7 @@ static const unsigned char chroma_ac_table[] = {
* and we'll use fixed offsets to change the width, height
* quantization tables, etc.
*/
static const unsigned char rockchip_vpu_jpeg_header[JPEG_HEADER_SIZE] = {
static const unsigned char hantro_jpeg_header[JPEG_HEADER_SIZE] = {
/* SOI */
0xff, 0xd8,
......@@ -262,19 +262,19 @@ static void jpeg_set_quality(unsigned char *buffer, int quality)
}
unsigned char *
rockchip_vpu_jpeg_get_qtable(struct rockchip_vpu_jpeg_ctx *ctx, int index)
hantro_jpeg_get_qtable(struct hantro_jpeg_ctx *ctx, int index)
{
if (index == 0)
return ctx->buffer + LUMA_QUANT_OFF;
return ctx->buffer + CHROMA_QUANT_OFF;
}
void rockchip_vpu_jpeg_header_assemble(struct rockchip_vpu_jpeg_ctx *ctx)
void hantro_jpeg_header_assemble(struct hantro_jpeg_ctx *ctx)
{
char *buf = ctx->buffer;
memcpy(buf, rockchip_vpu_jpeg_header,
sizeof(rockchip_vpu_jpeg_header));
memcpy(buf, hantro_jpeg_header,
sizeof(hantro_jpeg_header));
buf[HEIGHT_OFF + 0] = ctx->height >> 8;
buf[HEIGHT_OFF + 1] = ctx->height;
......@@ -291,7 +291,7 @@ void rockchip_vpu_jpeg_header_assemble(struct rockchip_vpu_jpeg_ctx *ctx)
jpeg_set_quality(buf, ctx->quality);
}
int rockchip_vpu_jpeg_enc_init(struct rockchip_vpu_ctx *ctx)
int hantro_jpeg_enc_init(struct hantro_ctx *ctx)
{
ctx->jpeg_enc.bounce_buffer.size =
ctx->dst_fmt.plane_fmt[0].sizeimage -
......@@ -309,7 +309,7 @@ int rockchip_vpu_jpeg_enc_init(struct rockchip_vpu_ctx *ctx)
return 0;
}
void rockchip_vpu_jpeg_enc_exit(struct rockchip_vpu_ctx *ctx)
void hantro_jpeg_enc_exit(struct hantro_ctx *ctx)
{
dma_free_attrs(ctx->dev->dev,
ctx->jpeg_enc.bounce_buffer.size,
......
drivers/staging/media/rockchip/vpu/rockchip_vpu_jpeg.h → drivers/staging/media/hantro/hantro_jpeg.h
View file @ a29add8c
......@@ -2,13 +2,12 @@
#define JPEG_HEADER_SIZE 601
struct rockchip_vpu_jpeg_ctx {
struct hantro_jpeg_ctx {
int width;
int height;
int quality;
unsigned char *buffer;
};
unsigned char *
rockchip_vpu_jpeg_get_qtable(struct rockchip_vpu_jpeg_ctx *ctx, int index);
void rockchip_vpu_jpeg_header_assemble(struct rockchip_vpu_jpeg_ctx *ctx);
unsigned char *hantro_jpeg_get_qtable(struct hantro_jpeg_ctx *ctx, int index);
void hantro_jpeg_header_assemble(struct hantro_jpeg_ctx *ctx);
drivers/staging/media/rockchip/vpu/rockchip_vpu_mpeg2.c → drivers/staging/media/hantro/hantro_mpeg2.c
View file @ a29add8c
// SPDX-License-Identifier: GPL-2.0
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
*/
#include "rockchip_vpu.h"
#include "hantro.h"
static const u8 zigzag[64] = {
0, 1, 8, 16, 9, 2, 3, 10,
......@@ -18,7 +18,7 @@ static const u8 zigzag[64] = {
53, 60, 61, 54, 47, 55, 62, 63
};
void rockchip_vpu_mpeg2_dec_copy_qtable(u8 *qtable,
void hantro_mpeg2_dec_copy_qtable(u8 *qtable,
const struct v4l2_ctrl_mpeg2_quantization *ctrl)
{
int i, n;
......@@ -35,9 +35,9 @@ void rockchip_vpu_mpeg2_dec_copy_qtable(u8 *qtable,
}
}
int rockchip_vpu_mpeg2_dec_init(struct rockchip_vpu_ctx *ctx)
int hantro_mpeg2_dec_init(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
ctx->mpeg2_dec.qtable.size = ARRAY_SIZE(zigzag) * 4;
ctx->mpeg2_dec.qtable.cpu =
......@@ -50,9 +50,9 @@ int rockchip_vpu_mpeg2_dec_init(struct rockchip_vpu_ctx *ctx)
return 0;
}
void rockchip_vpu_mpeg2_dec_exit(struct rockchip_vpu_ctx *ctx)
void hantro_mpeg2_dec_exit(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
dma_free_coherent(vpu->dev,
ctx->mpeg2_dec.qtable.size,
......
drivers/staging/media/rockchip/vpu/rockchip_vpu_v4l2.h → drivers/staging/media/hantro/hantro_v4l2.h
View file @ a29add8c
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
* Alpha Lin <Alpha.Lin@rock-chips.com>
......@@ -13,14 +13,14 @@
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
*/
#ifndef ROCKCHIP_VPU_V4L2_H_
#define ROCKCHIP_VPU_V4L2_H_
#ifndef HANTRO_V4L2_H_
#define HANTRO_V4L2_H_
#include "rockchip_vpu.h"
#include "hantro.h"
extern const struct v4l2_ioctl_ops rockchip_vpu_ioctl_ops;
extern const struct vb2_ops rockchip_vpu_queue_ops;
extern const struct v4l2_ioctl_ops hantro_ioctl_ops;
extern const struct vb2_ops hantro_queue_ops;
void rockchip_vpu_reset_fmts(struct rockchip_vpu_ctx *ctx);
void hantro_reset_fmts(struct hantro_ctx *ctx);
#endif /* ROCKCHIP_VPU_V4L2_H_ */
#endif /* HANTRO_V4L2_H_ */
drivers/staging/media/rockchip/vpu/rk3288_vpu_hw.c → drivers/staging/media/hantro/rk3288_vpu_hw.c
View file @ a29add8c
// SPDX-License-Identifier: GPL-2.0
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
* Jeffy Chen <jeffy.chen@rock-chips.com>
......@@ -8,9 +8,10 @@
#include <linux/clk.h>
#include "rockchip_vpu.h"
#include "rockchip_vpu_jpeg.h"
#include "rk3288_vpu_regs.h"
#include "hantro.h"
#include "hantro_jpeg.h"
#include "hantro_g1_regs.h"
#include "hantro_h1_regs.h"
#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
......@@ -18,30 +19,30 @@
* Supported formats.
*/
static const struct rockchip_vpu_fmt rk3288_vpu_enc_fmts[] = {
static const struct hantro_fmt rk3288_vpu_enc_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_YUV420M,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
},
{
.fourcc = V4L2_PIX_FMT_NV12M,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
},
{
.fourcc = V4L2_PIX_FMT_YUYV,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
},
{
.fourcc = V4L2_PIX_FMT_UYVY,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
},
{
.fourcc = V4L2_PIX_FMT_JPEG,
.codec_mode = RK_VPU_MODE_JPEG_ENC,
.codec_mode = HANTRO_MODE_JPEG_ENC,
.max_depth = 2,
.header_size = JPEG_HEADER_SIZE,
.frmsize = {
......@@ -55,14 +56,14 @@ static const struct rockchip_vpu_fmt rk3288_vpu_enc_fmts[] = {
},
};
static const struct rockchip_vpu_fmt rk3288_vpu_dec_fmts[] = {
static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_NV12,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
},
{
.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
.codec_mode = RK_VPU_MODE_MPEG2_DEC,
.codec_mode = HANTRO_MODE_MPEG2_DEC,
.max_depth = 2,
.frmsize = {
.min_width = 48,
......@@ -77,82 +78,82 @@ static const struct rockchip_vpu_fmt rk3288_vpu_dec_fmts[] = {
static irqreturn_t rk3288_vepu_irq(int irq, void *dev_id)
{
struct rockchip_vpu_dev *vpu = dev_id;
struct hantro_dev *vpu = dev_id;
enum vb2_buffer_state state;
u32 status, bytesused;
status = vepu_read(vpu, VEPU_REG_INTERRUPT);
bytesused = vepu_read(vpu, VEPU_REG_STR_BUF_LIMIT) / 8;
state = (status & VEPU_REG_INTERRUPT_FRAME_RDY) ?
status = vepu_read(vpu, H1_REG_INTERRUPT);
bytesused = vepu_read(vpu, H1_REG_STR_BUF_LIMIT) / 8;
state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
vepu_write(vpu, 0, H1_REG_INTERRUPT);
vepu_write(vpu, 0, H1_REG_AXI_CTRL);
rockchip_vpu_irq_done(vpu, bytesused, state);
hantro_irq_done(vpu, bytesused, state);
return IRQ_HANDLED;
}
static irqreturn_t rk3288_vdpu_irq(int irq, void *dev_id)
{
struct rockchip_vpu_dev *vpu = dev_id;
struct hantro_dev *vpu = dev_id;
enum vb2_buffer_state state;
u32 status;
status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
state = (status & VDPU_REG_INTERRUPT_DEC_RDY_INT) ?
status = vdpu_read(vpu, G1_REG_INTERRUPT);
state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?
VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
vdpu_write(vpu, VDPU_REG_CONFIG_DEC_CLK_GATE_E, VDPU_REG_CONFIG);
vdpu_write(vpu, 0, G1_REG_INTERRUPT);
vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
rockchip_vpu_irq_done(vpu, 0, state);
hantro_irq_done(vpu, 0, state);
return IRQ_HANDLED;
}
static int rk3288_vpu_hw_init(struct rockchip_vpu_dev *vpu)
static int rk3288_vpu_hw_init(struct hantro_dev *vpu)
{
/* Bump ACLK to max. possible freq. to improve performance. */
clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
return 0;
}
static void rk3288_vpu_enc_reset(struct rockchip_vpu_ctx *ctx)
static void rk3288_vpu_enc_reset(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
vepu_write(vpu, 0, VEPU_REG_ENC_CTRL);
vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
vepu_write(vpu, 0, H1_REG_ENC_CTRL);
vepu_write(vpu, 0, H1_REG_AXI_CTRL);
}
static void rk3288_vpu_dec_reset(struct rockchip_vpu_ctx *ctx)
static void rk3288_vpu_dec_reset(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
vdpu_write(vpu, VDPU_REG_CONFIG_DEC_CLK_GATE_E, VDPU_REG_CONFIG);
vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
vdpu_write(vpu, 1, G1_REG_SOFT_RESET);
}
/*
* Supported codec ops.
*/
static const struct rockchip_vpu_codec_ops rk3288_vpu_codec_ops[] = {
[RK_VPU_MODE_JPEG_ENC] = {
.run = rk3288_vpu_jpeg_enc_run,
static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
[HANTRO_MODE_JPEG_ENC] = {
.run = hantro_h1_jpeg_enc_run,
.reset = rk3288_vpu_enc_reset,
.init = rockchip_vpu_jpeg_enc_init,
.exit = rockchip_vpu_jpeg_enc_exit,
.init = hantro_jpeg_enc_init,
.exit = hantro_jpeg_enc_exit,
},
[RK_VPU_MODE_MPEG2_DEC] = {
.run = rk3288_vpu_mpeg2_dec_run,
[HANTRO_MODE_MPEG2_DEC] = {
.run = hantro_g1_mpeg2_dec_run,
.reset = rk3288_vpu_dec_reset,
.init = rockchip_vpu_mpeg2_dec_init,
.exit = rockchip_vpu_mpeg2_dec_exit,
.init = hantro_mpeg2_dec_init,
.exit = hantro_mpeg2_dec_exit,
},
};
......@@ -160,14 +161,14 @@ static const struct rockchip_vpu_codec_ops rk3288_vpu_codec_ops[] = {
* VPU variant.
*/
const struct rockchip_vpu_variant rk3288_vpu_variant = {
const struct hantro_variant rk3288_vpu_variant = {
.enc_offset = 0x0,
.enc_fmts = rk3288_vpu_enc_fmts,
.num_enc_fmts = ARRAY_SIZE(rk3288_vpu_enc_fmts),
.dec_offset = 0x400,
.dec_fmts = rk3288_vpu_dec_fmts,
.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
.codec = RK_VPU_JPEG_ENCODER | RK_VPU_MPEG2_DECODER,
.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER,
.codec_ops = rk3288_vpu_codec_ops,
.vepu_irq = rk3288_vepu_irq,
.vdpu_irq = rk3288_vdpu_irq,
......
drivers/staging/media/rockchip/vpu/rk3399_vpu_hw.c → drivers/staging/media/hantro/rk3399_vpu_hw.c
View file @ a29add8c
// SPDX-License-Identifier: GPL-2.0
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
* Jeffy Chen <jeffy.chen@rock-chips.com>
......@@ -8,8 +8,8 @@
#include <linux/clk.h>
#include "rockchip_vpu.h"
#include "rockchip_vpu_jpeg.h"
#include "hantro.h"
#include "hantro_jpeg.h"
#include "rk3399_vpu_regs.h"
#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
......@@ -18,30 +18,30 @@
* Supported formats.
*/
static const struct rockchip_vpu_fmt rk3399_vpu_enc_fmts[] = {
static const struct hantro_fmt rk3399_vpu_enc_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_YUV420M,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
},
{
.fourcc = V4L2_PIX_FMT_NV12M,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
},
{
.fourcc = V4L2_PIX_FMT_YUYV,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
},
{
.fourcc = V4L2_PIX_FMT_UYVY,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
.enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
},
{
.fourcc = V4L2_PIX_FMT_JPEG,
.codec_mode = RK_VPU_MODE_JPEG_ENC,
.codec_mode = HANTRO_MODE_JPEG_ENC,
.max_depth = 2,
.header_size = JPEG_HEADER_SIZE,
.frmsize = {
......@@ -55,14 +55,14 @@ static const struct rockchip_vpu_fmt rk3399_vpu_enc_fmts[] = {
},
};
static const struct rockchip_vpu_fmt rk3399_vpu_dec_fmts[] = {
static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
{
.fourcc = V4L2_PIX_FMT_NV12,
.codec_mode = RK_VPU_MODE_NONE,
.codec_mode = HANTRO_MODE_NONE,
},
{
.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
.codec_mode = RK_VPU_MODE_MPEG2_DEC,
.codec_mode = HANTRO_MODE_MPEG2_DEC,
.max_depth = 2,
.frmsize = {
.min_width = 48,
......@@ -77,7 +77,7 @@ static const struct rockchip_vpu_fmt rk3399_vpu_dec_fmts[] = {
static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id)
{
struct rockchip_vpu_dev *vpu = dev_id;
struct hantro_dev *vpu = dev_id;
enum vb2_buffer_state state;
u32 status, bytesused;
......@@ -89,14 +89,14 @@ static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id)
vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
rockchip_vpu_irq_done(vpu, bytesused, state);
hantro_irq_done(vpu, bytesused, state);
return IRQ_HANDLED;
}
static irqreturn_t rk3399_vdpu_irq(int irq, void *dev_id)
{
struct rockchip_vpu_dev *vpu = dev_id;
struct hantro_dev *vpu = dev_id;
enum vb2_buffer_state state;
u32 status;
......@@ -107,30 +107,30 @@ static irqreturn_t rk3399_vdpu_irq(int irq, void *dev_id)
vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
rockchip_vpu_irq_done(vpu, 0, state);
hantro_irq_done(vpu, 0, state);
return IRQ_HANDLED;
}
static int rk3399_vpu_hw_init(struct rockchip_vpu_dev *vpu)
static int rk3399_vpu_hw_init(struct hantro_dev *vpu)
{
/* Bump ACLK to max. possible freq. to improve performance. */
clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
return 0;
}
static void rk3399_vpu_enc_reset(struct rockchip_vpu_ctx *ctx)
static void rk3399_vpu_enc_reset(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
}
static void rk3399_vpu_dec_reset(struct rockchip_vpu_ctx *ctx)
static void rk3399_vpu_dec_reset(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
......@@ -141,18 +141,18 @@ static void rk3399_vpu_dec_reset(struct rockchip_vpu_ctx *ctx)
* Supported codec ops.
*/
static const struct rockchip_vpu_codec_ops rk3399_vpu_codec_ops[] = {
[RK_VPU_MODE_JPEG_ENC] = {
static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
[HANTRO_MODE_JPEG_ENC] = {
.run = rk3399_vpu_jpeg_enc_run,
.reset = rk3399_vpu_enc_reset,
.init = rockchip_vpu_jpeg_enc_init,
.exit = rockchip_vpu_jpeg_enc_exit,
.init = hantro_jpeg_enc_init,
.exit = hantro_jpeg_enc_exit,
},
[RK_VPU_MODE_MPEG2_DEC] = {
[HANTRO_MODE_MPEG2_DEC] = {
.run = rk3399_vpu_mpeg2_dec_run,
.reset = rk3399_vpu_dec_reset,
.init = rockchip_vpu_mpeg2_dec_init,
.exit = rockchip_vpu_mpeg2_dec_exit,
.init = hantro_mpeg2_dec_init,
.exit = hantro_mpeg2_dec_exit,
},
};
......@@ -160,14 +160,14 @@ static const struct rockchip_vpu_codec_ops rk3399_vpu_codec_ops[] = {
* VPU variant.
*/
const struct rockchip_vpu_variant rk3399_vpu_variant = {
const struct hantro_variant rk3399_vpu_variant = {
.enc_offset = 0x0,
.enc_fmts = rk3399_vpu_enc_fmts,
.num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),
.dec_offset = 0x400,
.dec_fmts = rk3399_vpu_dec_fmts,
.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
.codec = RK_VPU_JPEG_ENCODER | RK_VPU_MPEG2_DECODER,
.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER,
.codec_ops = rk3399_vpu_codec_ops,
.vepu_irq = rk3399_vepu_irq,
.vdpu_irq = rk3399_vdpu_irq,
......
drivers/staging/media/rockchip/vpu/rk3399_vpu_hw_jpeg_enc.c → drivers/staging/media/hantro/rk3399_vpu_hw_jpeg_enc.c
View file @ a29add8c
// SPDX-License-Identifier: GPL-2.0
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
*
......@@ -25,16 +25,16 @@
#include <asm/unaligned.h>
#include <media/v4l2-mem2mem.h>
#include "rockchip_vpu_jpeg.h"
#include "rockchip_vpu.h"
#include "rockchip_vpu_v4l2.h"
#include "rockchip_vpu_hw.h"
#include "hantro_jpeg.h"
#include "hantro.h"
#include "hantro_v4l2.h"
#include "hantro_hw.h"
#include "rk3399_vpu_regs.h"
#define VEPU_JPEG_QUANT_TABLE_COUNT 16
static void rk3399_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx)
static void rk3399_vpu_set_src_img_ctrl(struct hantro_dev *vpu,
struct hantro_ctx *ctx)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
u32 reg;
......@@ -60,8 +60,8 @@ static void rk3399_vpu_set_src_img_ctrl(struct rockchip_vpu_dev *vpu,
vepu_write_relaxed(vpu, reg, VEPU_REG_ENC_CTRL1);
}
static void rk3399_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx,
static void rk3399_vpu_jpeg_enc_set_buffers(struct hantro_dev *vpu,
struct hantro_ctx *ctx,
struct vb2_buffer *src_buf)
{
struct v4l2_pix_format_mplane *pix_fmt = &ctx->src_fmt;
......@@ -93,7 +93,7 @@ static void rk3399_vpu_jpeg_enc_set_buffers(struct rockchip_vpu_dev *vpu,
}
static void
rk3399_vpu_jpeg_enc_set_qtable(struct rockchip_vpu_dev *vpu,
rk3399_vpu_jpeg_enc_set_qtable(struct hantro_dev *vpu,
unsigned char *luma_qtable,
unsigned char *chroma_qtable)
{
......@@ -108,11 +108,11 @@ rk3399_vpu_jpeg_enc_set_qtable(struct rockchip_vpu_dev *vpu,
}
}
void rk3399_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx)
void rk3399_vpu_jpeg_enc_run(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct rockchip_vpu_jpeg_ctx jpeg_ctx;
struct hantro_jpeg_ctx jpeg_ctx;
struct media_request *src_req;
u32 reg;
......@@ -127,7 +127,7 @@ void rk3399_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx)
jpeg_ctx.width = ctx->dst_fmt.width;
jpeg_ctx.height = ctx->dst_fmt.height;
jpeg_ctx.quality = ctx->jpeg_quality;
rockchip_vpu_jpeg_header_assemble(&jpeg_ctx);
hantro_jpeg_header_assemble(&jpeg_ctx);
/* Switch to JPEG encoder mode before writing registers */
vepu_write_relaxed(vpu, VEPU_REG_ENCODE_FORMAT_JPEG,
......@@ -136,8 +136,8 @@ void rk3399_vpu_jpeg_enc_run(struct rockchip_vpu_ctx *ctx)
rk3399_vpu_set_src_img_ctrl(vpu, ctx);
rk3399_vpu_jpeg_enc_set_buffers(vpu, ctx, &src_buf->vb2_buf);
rk3399_vpu_jpeg_enc_set_qtable(vpu,
rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 0),
rockchip_vpu_jpeg_get_qtable(&jpeg_ctx, 1));
hantro_jpeg_get_qtable(&jpeg_ctx, 0),
hantro_jpeg_get_qtable(&jpeg_ctx, 1));
reg = VEPU_REG_OUTPUT_SWAP32
| VEPU_REG_OUTPUT_SWAP16
......
drivers/staging/media/rockchip/vpu/rk3399_vpu_hw_mpeg2_dec.c → drivers/staging/media/hantro/rk3399_vpu_hw_mpeg2_dec.c
View file @ a29add8c
// SPDX-License-Identifier: GPL-2.0
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
*/
......@@ -8,8 +8,8 @@
#include <asm/unaligned.h>
#include <linux/bitfield.h>
#include <media/v4l2-mem2mem.h>
#include "rockchip_vpu.h"
#include "rockchip_vpu_hw.h"
#include "hantro.h"
#include "hantro_hw.h"
#define VDPU_SWREG(nr) ((nr) * 4)
......@@ -84,22 +84,21 @@
#define PICT_FRAME 3
static void
rk3399_vpu_mpeg2_dec_set_quantization(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx)
rk3399_vpu_mpeg2_dec_set_quantization(struct hantro_dev *vpu,
struct hantro_ctx *ctx)
{
struct v4l2_ctrl_mpeg2_quantization *quantization;
quantization = rockchip_vpu_get_ctrl(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
rockchip_vpu_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu,
quantization);
quantization = hantro_get_ctrl(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION);
hantro_mpeg2_dec_copy_qtable(ctx->mpeg2_dec.qtable.cpu, quantization);
vdpu_write_relaxed(vpu, ctx->mpeg2_dec.qtable.dma,
VDPU_REG_QTABLE_BASE);
}
static void
rk3399_vpu_mpeg2_dec_set_buffers(struct rockchip_vpu_dev *vpu,
struct rockchip_vpu_ctx *ctx,
rk3399_vpu_mpeg2_dec_set_buffers(struct hantro_dev *vpu,
struct hantro_ctx *ctx,
struct vb2_buffer *src_buf,
struct vb2_buffer *dst_buf,
const struct v4l2_mpeg2_sequence *sequence,
......@@ -114,12 +113,12 @@ rk3399_vpu_mpeg2_dec_set_buffers(struct rockchip_vpu_dev *vpu,
switch (picture->picture_coding_type) {
case V4L2_MPEG2_PICTURE_CODING_TYPE_B:
backward_addr = rockchip_vpu_get_ref(vq,
slice_params->backward_ref_ts);
backward_addr = hantro_get_ref(vq,
slice_params->backward_ref_ts);
/* fall-through */
case V4L2_MPEG2_PICTURE_CODING_TYPE_P:
forward_addr = rockchip_vpu_get_ref(vq,
slice_params->forward_ref_ts);
forward_addr = hantro_get_ref(vq,
slice_params->forward_ref_ts);
}
/* Source bitstream buffer */
......@@ -161,9 +160,9 @@ rk3399_vpu_mpeg2_dec_set_buffers(struct rockchip_vpu_dev *vpu,
vdpu_write_relaxed(vpu, backward_addr, VDPU_REG_REFER3_BASE);
}
void rk3399_vpu_mpeg2_dec_run(struct rockchip_vpu_ctx *ctx)
void rk3399_vpu_mpeg2_dec_run(struct hantro_ctx *ctx)
{
struct rockchip_vpu_dev *vpu = ctx->dev;
struct hantro_dev *vpu = ctx->dev;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
const struct v4l2_mpeg2_sequence *sequence;
......@@ -177,8 +176,8 @@ void rk3399_vpu_mpeg2_dec_run(struct rockchip_vpu_ctx *ctx)
v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
&ctx->ctrl_handler);
slice_params = rockchip_vpu_get_ctrl(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
slice_params = hantro_get_ctrl(ctx,
V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS);
sequence = &slice_params->sequence;
picture = &slice_params->picture;
......
drivers/staging/media/rockchip/vpu/rk3399_vpu_regs.h → drivers/staging/media/hantro/rk3399_vpu_regs.h
View file @ a29add8c
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Rockchip VPU codec driver
* Hantro VPU codec driver
*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd.
* Alpha Lin <alpha.lin@rock-chips.com>
......
drivers/staging/media/rockchip/vpu/Makefile deleted 100644 → 0
View file @ 4e8c120d
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_VIDEO_ROCKCHIP_VPU) += rockchip-vpu.o
rockchip-vpu-y += \
rockchip_vpu_drv.o \
rockchip_vpu_v4l2.o \
rk3288_vpu_hw.o \
rk3288_vpu_hw_jpeg_enc.o \
rk3288_vpu_hw_mpeg2_dec.o \
rk3399_vpu_hw.o \
rk3399_vpu_hw_jpeg_enc.o \
rk3399_vpu_hw_mpeg2_dec.o \
rockchip_vpu_jpeg.o \
rockchip_vpu_mpeg2.o
drivers/staging/media/rockchip/vpu/rk3288_vpu_regs.h deleted 100644 → 0
View file @ 4e8c120d
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