Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into home.osdl.org:/home/torvalds/v2.5/linux

arch/arm/Kconfig

@@ -239,7 +239,7 @@ config DISCONTIGMEM
 
 # Now handle the bus types
 config PCI
-	bool "PCI support" if ARCH_INTEGRATOR
+	bool "PCI support" if ARCH_INTEGRATOR_AP
 	default y if ARCH_FTVPCI || ARCH_SHARK || FOOTBRIDGE_HOST || ARCH_IOP3XX
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
@@ -645,8 +645,6 @@ source "drivers/misc/Kconfig"
 
 source "drivers/usb/Kconfig"
 
-source "net/bluetooth/Kconfig"
-
 
 menu "Kernel hacking"
 

arch/arm/Makefile

@@ -182,7 +182,6 @@ define archhelp
   echo  '* zImage        - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
   echo  '  Image         - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
   echo  '  bootpImage    - Combined zImage and initial RAM disk' 
-  echo  '  initrd        - Create an initial image'
   echo  '  install       - Install uncompressed kernel'
   echo  '  zinstall      - Install compressed kernel'
   echo  '                  Install using (your) ~/bin/installkernel or'

arch/arm/boot/compressed/head.S

@@ -477,6 +477,12 @@ proc_types:
 @		b	__arm6_cache_off
 @		b	__armv3_cache_flush
 
+		.word	0x00000000		@ old ARM ID
+		.word	0x0000f000
+		mov	pc, lr
+		mov	pc, lr
+		mov	pc, lr
+
 		.word	0x41007000		@ ARM7/710
 		.word	0xfff8fe00
 		b	__arm7_cache_off
@@ -489,6 +495,14 @@ proc_types:
 		b	__armv4_cache_off
 		mov	pc, lr
 
+		.word	0x00007000		@ ARM7 IDs
+		.word	0x0000f000
+		mov	pc, lr
+		mov	pc, lr
+		mov	pc, lr
+
+		@ Everything from here on will be the new ID system.
+
 		.word	0x41129200		@ ARM920T
 		.word	0xff00fff0
 		b	__armv4_cache_on
@@ -507,8 +521,16 @@ proc_types:
 		b	__armv4_cache_off
 		b	__armv4_cache_flush
 
-		.word	0x69050000		@ xscale
-		.word	0xffff0000
+		@ These match on the architecture ID
+
+		.word	0x00050000		@ ARMv5TE
+		.word	0x000f0000
+		b	__armv4_cache_on
+		b	__armv4_cache_off
+		b	__armv4_cache_flush
+
+		.word	0x00060000		@ ARMv5TEJ
+		.word	0x000f0000
 		b	__armv4_cache_on
 		b	__armv4_cache_off
 		b	__armv4_cache_flush

arch/arm/kernel/apm.c

@@ -179,13 +179,10 @@ static void queue_event(apm_event_t event, struct apm_user *sender)
 	wake_up_interruptible(&apm_waitqueue);
 }
 
-/* defined in pm.c */
-extern int suspend(void);
-
 static int apm_suspend(void)
 {
 	struct list_head *l;
-	int err = suspend();
+	int err = pm_suspend(PM_SUSPEND_MEM);
 
 	/*
 	 * Anyone on the APM queues will think we're still suspended.

arch/arm/kernel/entry-armv.S

@@ -439,20 +439,25 @@ ENTRY(soft_irq_mask)
 
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 /* FIXME: should not be using soo many LDRs here */
-		ldr	\irqnr, =IO_ADDRESS(INTEGRATOR_IC_BASE)
-		ldr	\irqstat, [\irqnr, #IRQ_STATUS]		@ get masked status
-		ldr	\irqnr, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
-		ldr	\irqnr, [\irqnr, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
-		orr	\irqstat, \irqstat, \irqnr, lsl #INTEGRATOR_CM_INT0
+		ldr	\base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
+		mov	\irqnr, #IRQ_PIC_START
+		ldr	\irqstat, [\base, #IRQ_STATUS]		@ get masked status
+		ldr	\base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
+		teq	\irqstat, #0
+		ldreq	\irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
+		moveq	\irqnr, #IRQ_CIC_START
 
-		mov	\irqnr, #0
-1001:		tst	\irqstat, #1
+1001:		tst	\irqstat, #15
 		bne	1002f
+		add	\irqnr, \irqnr, #4
+		movs	\irqstat, \irqstat, lsr #4
+		bne	1001b
+1002:		tst	\irqstat, #1
+		bne	1003f
 		add	\irqnr, \irqnr, #1
-		mov	\irqstat, \irqstat, lsr #1
-		cmp	\irqnr, #22
-		bcc	1001b
-1002:		/* EQ will be set if we reach 22 */
+		movs	\irqstat, \irqstat, lsr #1
+		bne	1002b
+1003:		/* EQ will be set if no irqs pending */
 		.endm
 
 		.macro	irq_prio_table

arch/arm/kernel/pm.c

@@ -9,68 +9,18 @@
  *  sleep.
  */
 #include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sysctl.h>
 #include <linux/pm.h>
-#include <linux/device.h>
-#include <linux/sysdev.h>
 #include <linux/errno.h>
 #include <linux/sched.h>
 
-#include <asm/leds.h>
-#include <asm/system.h>
-
-/*
- * Tell the linker that pm_do_suspend may not be present.
- */
-extern int pm_do_suspend(void) __attribute__((weak));
-
-int suspend(void)
-{
-	int ret;
-
-	if (!pm_do_suspend)
-		return -ENOSYS;
-
-	/*
-	 * Suspend "legacy" devices.
-	 */
-	ret = pm_send_all(PM_SUSPEND, (void *)3);
-	if (ret != 0)
-		goto out;
-
-	ret = device_suspend(3);
-	if (ret)
-		goto resume_legacy;
-
-	local_irq_disable();
-	leds_event(led_stop);
-
-	sysdev_suspend(3);
-
-	ret = pm_do_suspend();
-
-	sysdev_resume();
-
-	leds_event(led_start);
-	local_irq_enable();
-
-	device_resume();
-
- resume_legacy:
-	pm_send_all(PM_RESUME, (void *)0);
-
- out:
-	return ret;
-}
-
 #ifdef CONFIG_SYSCTL
 /*
  * We really want this to die.  It's a disgusting hack using unallocated
  * sysctl numbers.  We should be using a real interface.
  */
 
-#include <linux/init.h>
-#include <linux/sysctl.h>
-
 static int
 pm_sysctl_proc_handler(ctl_table *ctl, int write, struct file *filp,
 		       void *buffer, size_t *lenp)
@@ -79,7 +29,7 @@ pm_sysctl_proc_handler(ctl_table *ctl, int write, struct file *filp,
 	printk("PM: task %s (pid %d) uses deprecated sysctl PM interface\n",
 		current->comm, current->pid);
 	if (write)
-		ret = suspend();
+		ret = pm_suspend(PM_SUSPEND_MEM);
 	return ret;
 }
 

arch/arm/kernel/process.c

@@ -117,12 +117,10 @@ __setup("reboot=", reboot_setup);
 
 void machine_halt(void)
 {
-	leds_event(led_halted);
 }
 
 void machine_power_off(void)
 {
-	leds_event(led_halted);
 	if (pm_power_off)
 		pm_power_off();
 }

arch/arm/kernel/setup.c

@@ -182,7 +182,7 @@ static const char *proc_arch[] = {
 	"5",
 	"5T",
 	"5TE",
-	"?(8)",
+	"5TEJ",
 	"?(9)",
 	"?(10)",
 	"?(11)",

arch/arm/kernel/signal.c

@@ -21,6 +21,7 @@
 #include <linux/tty.h>
 #include <linux/binfmts.h>
 #include <linux/elf.h>
+#include <linux/suspend.h>
 
 #include <asm/pgalloc.h>
 #include <asm/ucontext.h>
@@ -539,6 +540,11 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
 	if (!user_mode(regs))
 		return 0;
 
+	if (current->flags & PF_FREEZE) {
+		refrigerator(0);
+		goto no_signal;
+	}
+
 	if (current->ptrace & PT_SINGLESTEP)
 		ptrace_cancel_bpt(current);
 
@@ -550,6 +556,7 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
 		return 1;
 	}
 
+ no_signal:
 	/*
 	 * No signal to deliver to the process - restart the syscall.
 	 */

arch/arm/kernel/time.c

@@ -26,6 +26,7 @@
 #include <linux/timex.h>
 #include <linux/errno.h>
 #include <linux/profile.h>
+#include <linux/sysdev.h>
 
 #include <asm/hardware.h>
 #include <asm/io.h>
@@ -72,8 +73,6 @@ unsigned long (*gettimeoffset)(void) = dummy_gettimeoffset;
  */
 unsigned long long sched_clock(void)
 {
-	unsigned long long this_offset;
-
 	return (unsigned long long)jiffies * (1000000000 / HZ);
 }
 
@@ -137,6 +136,47 @@ static void dummy_leds_event(led_event_t evt)
 
 void (*leds_event)(led_event_t) = dummy_leds_event;
 
+static int leds_suspend(struct sys_device *dev, u32 state)
+{
+	leds_event(led_stop);
+	return 0;
+}
+
+static int leds_resume(struct sys_device *dev)
+{
+	leds_event(led_start);
+	return 0;
+}
+
+static int leds_shutdown(struct sys_device *dev)
+{
+	leds_event(led_halted);
+	return 0;
+}
+
+static struct sysdev_class leds_sysclass = {
+	set_kset_name("leds"),
+	.shutdown	= leds_shutdown,
+	.suspend	= leds_suspend,
+	.resume		= leds_resume,
+};
+
+static struct sys_device leds_device = {
+	.id		= 0,
+	.cls		= &leds_sysclass,
+};
+
+static int __init leds_init(void)
+{
+	int ret;
+	ret = sysdev_class_register(&leds_sysclass);
+	if (ret == 0)
+		ret = sys_device_register(&leds_device);
+	return ret;
+}
+
+device_initcall(leds_init);
+
 EXPORT_SYMBOL(leds_event);
 #endif
 

arch/arm/kernel/traps.c

@@ -212,10 +212,10 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
 	printk("CPU: %d\n", smp_processor_id());
 	show_regs(regs);
 	printk("Process %s (pid: %d, stack limit = 0x%p)\n",
-		current->comm, current->pid, tsk->thread_info + 1);
+		tsk->comm, tsk->pid, tsk->thread_info + 1);
 
 	if (!user_mode(regs) || in_interrupt()) {
-		dump_mem("Stack: ", (unsigned long)(regs + 1), 8192+(unsigned long)tsk->thread_info);
+		dump_mem("Stack: ", regs->ARM_sp, 8192+(unsigned long)tsk->thread_info);
 		dump_backtrace(regs, tsk);
 		dump_instr(regs);
 	}

arch/arm/lib/io-readsl-armv4.S

@@ -9,7 +9,6 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/hardware.h>
 
 /*
  * Note that some reads can be aligned on half-word boundaries.
@@ -31,6 +30,10 @@ ENTRY(__raw_readsl)
 		blt	4f
 		bgt	6f
 
+#ifndef	__ARMEB__
+
+		/* little endian code */
+
 		strh	ip, [r1], #2
 		mov	ip, ip, lsr #16
 3:		subs	r2, r2, #1
@@ -68,3 +71,48 @@ ENTRY(__raw_readsl)
 		strb	ip, [r1]
 		mov	pc, lr
 
+#else
+
+		/* big endian code */
+
+
+		mov	r3, ip, lsr #16
+		strh	r3, [r1], #2
+3:		mov	r3, ip, lsl #16
+		subs	r2, r2, #1
+		ldrne	ip, [r0]
+		orrne	r3, r3, ip, lsr #16
+		strne	r3, [r1], #4
+		bne	3b
+ 		strh	ip, [r1], #2
+ 		mov	pc, lr
+
+4:		mov	r3, ip, lsr #24
+		strb	r3, [r1], #1
+		mov	r3, ip, lsr #8
+		strh	r3, [r1], #2
+5:		mov	r3, ip, lsl #24
+		subs	r2, r2, #1
+		ldrne	ip, [r0]
+		orrne	r3, r3, ip, lsr #8
+		strne	r3, [r1], #4
+		bne	5b
+		strb	ip, [r1], #1
+		mov	pc, lr
+
+6:		mov	r3, ip, lsr #24
+		strb	r3, [r1], #1
+7:		mov	r3, ip, lsl #8
+		subs	r2, r2, #1
+		ldrne	ip, [r0]
+		orrne	r3, r3, ip, lsr #24
+		strne	r3, [r1], #4
+		bne	7b
+		mov	r3, ip, lsr #8
+		strh	r3, [r1], #2
+		strb	ip, [r1], #1
+		mov	pc, lr
+
+#endif
+
+

arch/arm/lib/io-readsw-armv4.S

@@ -9,7 +9,14 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/hardware.h>
+
+		.macro	pack, rd, hw1, hw2
+#ifndef __ARMEB__
+		orr	\rd, \hw1, \hw2, lsl #16
+#else
+		orr	\rd, \hw2, \hw1, lsl #16
+#endif
+		.endm
 
 .insw_bad_alignment:
 		adr	r0, .insw_bad_align_msg
@@ -41,19 +48,19 @@ ENTRY(__raw_readsw)
 
 .insw_8_lp:	ldrh	r3, [r0]
 		ldrh	r4, [r0]
-		orr	r3, r3, r4, lsl #16
+		pack	r3, r3, r4
 
 		ldrh	r4, [r0]
 		ldrh	r5, [r0]
-		orr	r4, r4, r5, lsl #16
+		pack	r4, r4, r5
 
 		ldrh	r5, [r0]
 		ldrh	ip, [r0]
-		orr	r5, r5, ip, lsl #16
+		pack	r5, r5, ip
 
 		ldrh	ip, [r0]
 		ldrh	lr, [r0]
-		orr	ip, ip, lr, lsl #16
+		pack	ip, ip, lr
 
 		stmia	r1!, {r3 - r5, ip}
 
@@ -68,11 +75,11 @@ ENTRY(__raw_readsw)
 
 		ldrh	r3, [r0]
 		ldrh	r4, [r0]
-		orr	r3, r3, r4, lsl #16
+		pack	r3, r3, r4
 
 		ldrh	r4, [r0]
 		ldrh	ip, [r0]
-		orr	r4, r4, ip, lsl #16
+		pack	r4, r4, ip
 
 		stmia	r1!, {r3, r4}
 
@@ -81,7 +88,7 @@ ENTRY(__raw_readsw)
 
 		ldrh	r3, [r0]
 		ldrh	ip, [r0]
-		orr	r3, r3, ip, lsl #16
+		pack	r3, r3, ip
 
 		str	r3, [r1], #4
 

arch/arm/lib/io-writesw-armv4.S

@@ -9,7 +9,18 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/hardware.h>
+
+		.macro	outword, rd
+#ifndef __ARMEB__
+		strh	\rd, [r0]
+		mov	\rd, \rd, lsr #16
+		strh	\rd, [r0]
+#else
+		mov	lr, \rd, lsr #16
+		strh	lr, [r0]
+		strh	\rd, [r0]
+#endif
+		.endm
 
 .outsw_bad_alignment:
 		adr	r0, .outsw_bad_align_msg
@@ -40,20 +51,10 @@ ENTRY(__raw_writesw)
 		bmi	.no_outsw_8
 
 .outsw_8_lp:	ldmia	r1!, {r3, r4, r5, ip}
-
-		strh	r3, [r0]
-		mov	r3, r3, lsr #16
-		strh	r3, [r0]
-		strh	r4, [r0]
-		mov	r4, r4, lsr #16
-		strh	r4, [r0]
-		strh	r5, [r0]
-		mov	r5, r5, lsr #16
-		strh	r5, [r0]
-		strh	ip, [r0]
-		mov	ip, ip, lsr #16
-		strh	ip, [r0]
-
+		outword	r3
+		outword	r4
+		outword	r5
+		outword	ip
 		subs	r2, r2, #8
 		bpl	.outsw_8_lp
 
@@ -64,20 +65,14 @@ ENTRY(__raw_writesw)
 		beq	.no_outsw_4
 
 		ldmia	r1!, {r3, ip}
-		strh	r3, [r0]
-		mov	r3, r3, lsr #16
-		strh	r3, [r0]
-		strh	ip, [r0]
-		mov	ip, ip, lsr #16
-		strh	ip, [r0]
+		outword	r3
+		outword	ip
 
 .no_outsw_4:	tst	r2, #2
 		beq	.no_outsw_2
 
 		ldr	r3, [r1], #4
-		strh	r3, [r0]
-		mov	r3, r3, lsr #16
-		strh	r3, [r0]
+		outword	r3
 
 .no_outsw_2:	tst	r2, #1
 		ldrneh	r3, [r1]

arch/arm/mach-integrator/Kconfig

 menu "Integrator Options"
 	depends on ARCH_INTEGRATOR
 
+config ARCH_INTEGRATOR_AP
+	bool "Support Integrator/AP and Integrator/PP2 platforms"
+	help
+	  Include support for the ARM(R) Integrator/AP and
+	  Integrator/PP2 platforms.
+
 config INTEGRATOR_IMPD1
 	tristate "Include support for Integrator/IM-PD1"
+	depends on ARCH_INTEGRATOR_AP
 	help
 	  The IM-PD1 is an add-on logic module for the Integrator which
 	  allows ARM(R) Ltd PrimeCells to be developed and evaluated.

arch/arm/mach-integrator/Makefile

@@ -4,9 +4,10 @@
 
 # Object file lists.
 
-obj-y			:= core.o lm.o time.o
+obj-y					:= core.o lm.o time.o
+obj-$(CONFIG_ARCH_INTEGRATOR_AP)	+= integrator_ap.o
 
-obj-$(CONFIG_LEDS)	+= leds.o
-obj-$(CONFIG_PCI)	+= pci_v3.o pci.o
+obj-$(CONFIG_LEDS)			+= leds.o
+obj-$(CONFIG_PCI)			+= pci_v3.o pci.o
 obj-$(CONFIG_CPU_FREQ_INTEGRATOR)	+= cpu.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)		+= impd1.o

arch/arm/mach-integrator/core.c

 /*
- *  linux/arch/arm/mach-integrator/arch.c
+ *  linux/arch/arm/mach-integrator/core.c
  *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
  */
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/list.h>
 #include <linux/device.h>
-#include <linux/slab.h>
-#include <linux/string.h>
 
 #include <asm/hardware.h>
-#include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
 #include <asm/hardware/amba.h>
-#include <asm/hardware/amba_kmi.h>
-
-#include <asm/arch/lm.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-
-/* 
- * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
- * is the (PA >> 12).
- *
- * Setup a VA for the Integrator interrupt controller (for header #0,
- * just for now).
- */
-#define VA_IC_BASE	IO_ADDRESS(INTEGRATOR_IC_BASE) 
-#define VA_SC_BASE	IO_ADDRESS(INTEGRATOR_SC_BASE)
-#define VA_CMIC_BASE	IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
 
-/*
- * Logical      Physical
- * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
- * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
- * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
- * ee000000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
- * ef000000			Cache flush
- * f1000000	10000000	Core module registers
- * f1100000	11000000	System controller registers
- * f1200000	12000000	EBI registers
- * f1300000	13000000	Counter/Timer
- * f1400000	14000000	Interrupt controller
- * f1500000	15000000	RTC
- * f1600000	16000000	UART 0
- * f1700000	17000000	UART 1
- * f1a00000	1a000000	Debug LEDs
- * f1b00000	1b000000	GPIO
- */
-
-static struct map_desc integrator_io_desc[] __initdata = {
- { IO_ADDRESS(INTEGRATOR_HDR_BASE),   INTEGRATOR_HDR_BASE,   SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_SC_BASE),    INTEGRATOR_SC_BASE,    SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_EBI_BASE),   INTEGRATOR_EBI_BASE,   SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_CT_BASE),    INTEGRATOR_CT_BASE,    SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_IC_BASE),    INTEGRATOR_IC_BASE,    SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_RTC_BASE),   INTEGRATOR_RTC_BASE,   SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_DBG_BASE),   INTEGRATOR_DBG_BASE,   SZ_4K,  MT_DEVICE },
- { IO_ADDRESS(INTEGRATOR_GPIO_BASE),  INTEGRATOR_GPIO_BASE,  SZ_4K,  MT_DEVICE },
- { PCI_MEMORY_VADDR,                  PHYS_PCI_MEM_BASE,     SZ_16M, MT_DEVICE },
- { PCI_CONFIG_VADDR,                  PHYS_PCI_CONFIG_BASE,  SZ_16M, MT_DEVICE },
- { PCI_V3_VADDR,                      PHYS_PCI_V3_BASE,      SZ_64K, MT_DEVICE },
- { PCI_IO_VADDR,                      PHYS_PCI_IO_BASE,      SZ_64K, MT_DEVICE }
+static struct amba_device rtc_device = {
+	.dev		= {
+		.bus_id	= "mb:15",
+	},
+	.res		= {
+		.start	= INTEGRATOR_RTC_BASE,
+		.end	= INTEGRATOR_RTC_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	.irq		= IRQ_RTCINT,
+	.periphid	= 0x00041030,
 };
 
-static void __init integrator_map_io(void)
-{
-	iotable_init(integrator_io_desc, ARRAY_SIZE(integrator_io_desc));
-}
-
-#define ALLPCI ( (1 << IRQ_PCIINT0) | (1 << IRQ_PCIINT1) | (1 << IRQ_PCIINT2) | (1 << IRQ_PCIINT3) )
-
-static void sc_mask_irq(unsigned int irq)
-{
-	writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-}
-
-static void sc_unmask_irq(unsigned int irq)
-{
-	writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
-}
-
-static struct irqchip sc_chip = {
-	.ack	= sc_mask_irq,
-	.mask	= sc_mask_irq,
-	.unmask = sc_unmask_irq,
+static struct amba_device uart0_device = {
+	.dev		= {
+		.bus_id	= "mb:16",
+	},
+	.res		= {
+		.start	= INTEGRATOR_UART0_BASE,
+		.end	= INTEGRATOR_UART0_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	.irq		= IRQ_UARTINT0,
+	.periphid	= 0x0041010,
 };
 
-static void __init integrator_init_irq(void)
-{
-	unsigned int i;
-
-	/* Disable all interrupts initially. */
-	/* Do the core module ones */
-	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
-
-	/* do the header card stuff next */
-	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
-	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-
-	for (i = 0; i < NR_IRQS; i++) {
-		if (((1 << i) && INTEGRATOR_SC_VALID_INT) != 0) {
-			set_irq_chip(i, &sc_chip);
-			set_irq_handler(i, do_level_IRQ);
-			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-		}
-	}
-}
+static struct amba_device uart1_device = {
+	.dev		= {
+		.bus_id	= "mb:17",
+	},
+	.res		= {
+		.start	= INTEGRATOR_UART1_BASE,
+		.end	= INTEGRATOR_UART1_BASE + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	.irq		= IRQ_UARTINT1,
+	.periphid	= 0x0041010,
+};
 
 static struct amba_device kmi0_device = {
 	.dev		= {
@@ -136,7 +61,7 @@ static struct amba_device kmi0_device = {
 	},
 	.res		= {
 		.start	= KMI0_BASE,
-		.end	= KMI0_BASE + KMI_SIZE - 1,
+		.end	= KMI0_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	.irq		= IRQ_KMIINT0,
@@ -149,7 +74,7 @@ static struct amba_device kmi1_device = {
 	},
 	.res		= {
 		.start	= KMI1_BASE,
-		.end	= KMI1_BASE + KMI_SIZE - 1,
+		.end	= KMI1_BASE + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	.irq		= IRQ_KMIINT1,
@@ -157,52 +82,23 @@ static struct amba_device kmi1_device = {
 };
 
 static struct amba_device *amba_devs[] __initdata = {
+	&rtc_device,
+	&uart0_device,
+	&uart1_device,
 	&kmi0_device,
 	&kmi1_device,
 };
 
-static int __init register_devices(void)
+static int __init integrator_init(void)
 {
-	unsigned long sc_dec;
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 		struct amba_device *d = amba_devs[i];
-
 		amba_device_register(d, &iomem_resource);
 	}
 
-	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
-	for (i = 0; i < 4; i++) {
-		struct lm_device *lmdev;
-
-		if ((sc_dec & (16 << i)) == 0)
-			continue;
-
-		lmdev = kmalloc(sizeof(struct lm_device), GFP_KERNEL);
-		if (!lmdev)
-			continue;
-
-		memset(lmdev, 0, sizeof(struct lm_device));
-
-		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
-		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
-		lmdev->resource.flags = IORESOURCE_MEM;
-		lmdev->irq = IRQ_EXPINT0 + i;
-		lmdev->id = i;
-
-		lm_device_register(lmdev);
-	}
-
 	return 0;
 }
 
-arch_initcall(register_devices);
-
-MACHINE_START(INTEGRATOR, "ARM-Integrator")
-	MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
-	BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
-	BOOT_PARAMS(0x00000100)
-	MAPIO(integrator_map_io)
-	INITIRQ(integrator_init_irq)
-MACHINE_END
+arch_initcall(integrator_init);

arch/arm/mach-integrator/integrator_ap.c

+/*
+ *  linux/arch/arm/mach-integrator/integrator_ap.c
+ *
+ *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sysdev.h>
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/amba.h>
+#include <asm/hardware/amba_kmi.h>
+
+#include <asm/arch/lm.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+
+
+/* 
+ * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
+ * is the (PA >> 12).
+ *
+ * Setup a VA for the Integrator interrupt controller (for header #0,
+ * just for now).
+ */
+#define VA_IC_BASE	IO_ADDRESS(INTEGRATOR_IC_BASE) 
+#define VA_SC_BASE	IO_ADDRESS(INTEGRATOR_SC_BASE)
+#define VA_EBI_BASE	IO_ADDRESS(INTEGRATOR_EBI_BASE)
+#define VA_CMIC_BASE	IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
+
+/*
+ * Logical      Physical
+ * e8000000	40000000	PCI memory		PHYS_PCI_MEM_BASE	(max 512M)
+ * ec000000	61000000	PCI config space	PHYS_PCI_CONFIG_BASE	(max 16M)
+ * ed000000	62000000	PCI V3 regs		PHYS_PCI_V3_BASE	(max 64k)
+ * ee000000	60000000	PCI IO			PHYS_PCI_IO_BASE	(max 16M)
+ * ef000000			Cache flush
+ * f1000000	10000000	Core module registers
+ * f1100000	11000000	System controller registers
+ * f1200000	12000000	EBI registers
+ * f1300000	13000000	Counter/Timer
+ * f1400000	14000000	Interrupt controller
+ * f1500000	15000000	RTC
+ * f1600000	16000000	UART 0
+ * f1700000	17000000	UART 1
+ * f1a00000	1a000000	Debug LEDs
+ * f1b00000	1b000000	GPIO
+ */
+
+static struct map_desc ap_io_desc[] __initdata = {
+ { IO_ADDRESS(INTEGRATOR_HDR_BASE),   INTEGRATOR_HDR_BASE,   SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_SC_BASE),    INTEGRATOR_SC_BASE,    SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_EBI_BASE),   INTEGRATOR_EBI_BASE,   SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_CT_BASE),    INTEGRATOR_CT_BASE,    SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_IC_BASE),    INTEGRATOR_IC_BASE,    SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_RTC_BASE),   INTEGRATOR_RTC_BASE,   SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_DBG_BASE),   INTEGRATOR_DBG_BASE,   SZ_4K,  MT_DEVICE },
+ { IO_ADDRESS(INTEGRATOR_GPIO_BASE),  INTEGRATOR_GPIO_BASE,  SZ_4K,  MT_DEVICE },
+ { PCI_MEMORY_VADDR,                  PHYS_PCI_MEM_BASE,     SZ_16M, MT_DEVICE },
+ { PCI_CONFIG_VADDR,                  PHYS_PCI_CONFIG_BASE,  SZ_16M, MT_DEVICE },
+ { PCI_V3_VADDR,                      PHYS_PCI_V3_BASE,      SZ_64K, MT_DEVICE },
+ { PCI_IO_VADDR,                      PHYS_PCI_IO_BASE,      SZ_64K, MT_DEVICE }
+};
+
+static void __init ap_map_io(void)
+{
+	iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
+}
+
+#define INTEGRATOR_SC_VALID_INT	0x003fffff
+
+static void sc_mask_irq(unsigned int irq)
+{
+	writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+}
+
+static void sc_unmask_irq(unsigned int irq)
+{
+	writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
+}
+
+static struct irqchip sc_chip = {
+	.ack	= sc_mask_irq,
+	.mask	= sc_mask_irq,
+	.unmask = sc_unmask_irq,
+};
+
+static void __init ap_init_irq(void)
+{
+	unsigned int i;
+
+	/* Disable all interrupts initially. */
+	/* Do the core module ones */
+	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+
+	/* do the header card stuff next */
+	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+
+	for (i = 0; i < NR_IRQS; i++) {
+		if (((1 << i) && INTEGRATOR_SC_VALID_INT) != 0) {
+			set_irq_chip(i, &sc_chip);
+			set_irq_handler(i, do_level_IRQ);
+			set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+		}
+	}
+}
+
+#ifdef CONFIG_PM
+static unsigned long ic_irq_enable;
+
+static int irq_suspend(struct sys_device *dev, u32 state)
+{
+	ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
+	return 0;
+}
+
+static int irq_resume(struct sys_device *dev)
+{
+	/* disable all irq sources */
+	writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
+	writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
+	writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
+
+	writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
+	return 0;
+}
+#else
+#define irq_suspend NULL
+#define irq_resume NULL
+#endif
+
+static struct sysdev_class irq_class = {
+	set_kset_name("irq"),
+	.suspend	= irq_suspend,
+	.resume		= irq_resume,
+};
+
+static struct sys_device irq_device = {
+	.id	= 0,
+	.cls	= &irq_class,
+};
+
+static int __init irq_init_sysfs(void)
+{
+	int ret = sysdev_class_register(&irq_class);
+	if (ret == 0)
+		ret = sys_device_register(&irq_device);
+	return ret;
+}
+
+device_initcall(irq_init_sysfs);
+
+/*
+ * Flash handling.
+ */
+#define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
+#define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
+#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
+#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
+
+static int ap_flash_init(void)
+{
+	u32 tmp;
+
+	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
+
+	tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
+	writel(tmp, EBI_CSR1);
+
+	if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
+		writel(0xa05f, EBI_LOCK);
+		writel(tmp, EBI_CSR1);
+		writel(0, EBI_LOCK);
+	}
+	return 0;
+}
+
+static void ap_flash_exit(void)
+{
+	u32 tmp;
+
+	writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
+
+	tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
+	writel(tmp, EBI_CSR1);
+
+	if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
+		writel(0xa05f, EBI_LOCK);
+		writel(tmp, EBI_CSR1);
+		writel(0, EBI_LOCK);
+	}
+}
+
+static void ap_flash_set_vpp(int on)
+{
+	unsigned long reg = on ? SC_CTRLS : SC_CTRLC;
+
+	writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
+}
+
+static struct flash_platform_data ap_flash_data = {
+	.map_name	= "cfi_probe",
+	.width		= 4,
+	.init		= ap_flash_init,
+	.exit		= ap_flash_exit,
+	.set_vpp	= ap_flash_set_vpp,
+};
+
+static struct resource cfi_flash_resource = {
+	.start		= INTEGRATOR_FLASH_BASE,
+	.end		= INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device cfi_flash_device = {
+	.name		= "armflash",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &ap_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &cfi_flash_resource,
+};
+
+static int __init ap_init(void)
+{
+	unsigned long sc_dec;
+	int i;
+
+	platform_add_device(&cfi_flash_device);
+
+	sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
+	for (i = 0; i < 4; i++) {
+		struct lm_device *lmdev;
+
+		if ((sc_dec & (16 << i)) == 0)
+			continue;
+
+		lmdev = kmalloc(sizeof(struct lm_device), GFP_KERNEL);
+		if (!lmdev)
+			continue;
+
+		memset(lmdev, 0, sizeof(struct lm_device));
+
+		lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
+		lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
+		lmdev->resource.flags = IORESOURCE_MEM;
+		lmdev->irq = IRQ_AP_EXPINT0 + i;
+		lmdev->id = i;
+
+		lm_device_register(lmdev);
+	}
+
+	return 0;
+}
+
+arch_initcall(ap_init);
+
+MACHINE_START(INTEGRATOR, "ARM-Integrator")
+	MAINTAINER("ARM Ltd/Deep Blue Solutions Ltd")
+	BOOT_MEM(0x00000000, 0x16000000, 0xf1600000)
+	BOOT_PARAMS(0x00000100)
+	MAPIO(ap_map_io)
+	INITIRQ(ap_init_irq)
+MACHINE_END

arch/arm/mach-integrator/pci.c

@@ -96,7 +96,7 @@ static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
 }
 
 static int irq_tab[4] __initdata = {
-	IRQ_PCIINT0,	IRQ_PCIINT1,	IRQ_PCIINT2,	IRQ_PCIINT3
+	IRQ_AP_PCIINT0,	IRQ_AP_PCIINT1,	IRQ_AP_PCIINT2,	IRQ_AP_PCIINT3
 };
 
 /*

arch/arm/mach-integrator/pci_v3.c

@@ -575,7 +575,7 @@ void __init pci_v3_preinit(void)
 	/*
 	 * Grab the PCI error interrupt.
 	 */
-	ret = request_irq(IRQ_V3INT, v3_irq, 0, "V3", NULL);
+	ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
 	if (ret)
 		printk(KERN_ERR "PCI: unable to grab PCI error "
 		       "interrupt: %d\n", ret);
@@ -596,7 +596,7 @@ void __init pci_v3_postinit(void)
 	v3_writeb(V3_LB_IMASK, 0x68);
 
 #if 0
-	ret = request_irq(IRQ_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
+	ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
 	if (ret)
 		printk(KERN_ERR "PCI: unable to grab local bus timeout "
 		       "interrupt: %d\n", ret);

arch/arm/mach-pxa/irq.c

@@ -58,7 +58,19 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 {
 	int gpio, idx;
 
-	gpio = irq - ((irq >= IRQ_GPIO(2)) ? IRQ_GPIO(2) + 2 : IRQ_GPIO(0));
+	gpio = IRQ_TO_GPIO(irq);
+	idx = gpio >> 5;
+
+	if (type == IRQT_PROBE) {
+	    /* Don't mess with enabled GPIOs using preconfigured edges or
+	       GPIOs set to alternate function during probe */
+		if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
+		    GPIO_bit(gpio))
+			return 0;
+		if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
+			return 0;
+		type = __IRQT_RISEDGE | __IRQT_FALEDGE;
+	}
 
 	printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio);
 
@@ -78,10 +90,8 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 
 	printk("edges\n");
 
-	idx = gpio >> 5;
 	GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 	GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
-
 	return 0;
 }
 

arch/arm/mach-pxa/leds.c

@@ -7,6 +7,7 @@
  *
  * Copyright (c) 2001 Jeff Sutherland, Accelent Systems Inc.
  */
+#include <linux/compiler.h>
 #include <linux/init.h>
 
 #include <asm/leds.h>

arch/arm/mach-pxa/lubbock.c

@@ -78,7 +78,7 @@ static void __init lubbock_init_irq(void)
 	pxa_init_irq();
 
 	/* setup extra lubbock irqs */
-	for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_IRQ(5); irq++) {
+	for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
 		set_irq_chip(irq, &lubbock_irq_chip);
 		set_irq_handler(irq, do_level_IRQ);
 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
@@ -124,6 +124,7 @@ static struct map_desc lubbock_io_desc[] __initdata = {
   { 0xf0000000, 0x08000000, 0x00100000, MT_DEVICE }, /* CPLD */
   { 0xf1000000, 0x0c000000, 0x00100000, MT_DEVICE }, /* LAN91C96 IO */
   { 0xf1100000, 0x0e000000, 0x00100000, MT_DEVICE }, /* LAN91C96 Attr */
+  { 0xf4000000, 0x10000000, 0x00800000, MT_DEVICE }, /* SA1111 */
 };
 
 static void __init lubbock_map_io(void)

arch/arm/mach-pxa/pm.c

@@ -11,13 +11,14 @@
  * modify it under the terms of the GNU General Public License.
  */
 #include <linux/config.h>
+#include <linux/init.h>
+#include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
 
 #include <asm/hardware.h>
 #include <asm/memory.h>
 #include <asm/system.h>
-#include <asm/leds.h>
 
 
 /*
@@ -60,13 +61,16 @@ enum {	SLEEP_SAVE_START = 0,
 };
 
 
-int pm_do_suspend(void)
+static int pxa_pm_enter(u32 state)
 {
 	unsigned long sleep_save[SLEEP_SAVE_SIZE];
 	unsigned long checksum = 0;
 	unsigned long delta;
 	int i;
 
+	if (state != PM_SUSPEND_MEM)
+		return -EINVAL;
+
 	/* preserve current time */
 	delta = xtime.tv_sec - RCNR;
 
@@ -194,3 +198,37 @@ unsigned long sleep_phys_sp(void *sp)
 {
 	return virt_to_phys(sp);
 }
+
+/*
+ * Called after processes are frozen, but before we shut down devices.
+ */
+static int pxa_pm_prepare(u32 state)
+{
+	return 0;
+}
+
+/*
+ * Called after devices are re-setup, but before processes are thawed.
+ */
+static int pxa_pm_finish(u32 state)
+{
+	return 0;
+}
+
+/*
+ * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
+ */
+static struct pm_ops pxa_pm_ops = {
+	.pm_disk_mode	= PM_DISK_FIRMWARE,
+	.prepare	= pxa_pm_prepare,
+	.enter		= pxa_pm_enter,
+	.finish		= pxa_pm_finish,
+};
+
+static int __init pxa_pm_init(void)
+{
+	pm_set_ops(&pxa_pm_ops);
+	return 0;
+}
+
+late_initcall(pxa_pm_init);

arch/arm/mach-sa1100/leds.c

@@ -5,6 +5,7 @@
  * 
  * Copyright (C) 2001 Nicolas Pitre
  */
+#include <linux/compiler.h>
 #include <linux/init.h>
 
 #include <asm/leds.h>

arch/arm/mach-sa1100/pm.c

@@ -22,6 +22,8 @@
  * 2002-05-27:	Nicolas Pitre	Killed sleep.h and the kmalloced save array.
  * 				Storage is local on the stack now.
  */
+#include <linux/init.h>
+#include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
 
@@ -54,11 +56,14 @@ enum {	SLEEP_SAVE_SP = 0,
 };
 
 
-int pm_do_suspend(void)
+static int sa11x0_pm_enter(u32 state)
 {
 	unsigned long sleep_save[SLEEP_SAVE_SIZE];
 	unsigned long delta, gpio;
 
+	if (state != PM_SUSPEND_MEM)
+		return -EINVAL;
+
 	/* preserve current time */
 	delta = xtime.tv_sec - RCNR;
 	gpio = GPLR;
@@ -139,3 +144,37 @@ unsigned long sleep_phys_sp(void *sp)
 {
 	return virt_to_phys(sp);
 }
+
+/*
+ * Called after processes are frozen, but before we shut down devices.
+ */
+static int sa11x0_pm_prepare(u32 state)
+{
+	return 0;
+}
+
+/*
+ * Called after devices are re-setup, but before processes are thawed.
+ */
+static int sa11x0_pm_finish(u32 state)
+{
+	return 0;
+}
+
+/*
+ * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
+ */
+static struct pm_ops sa11x0_pm_ops = {
+	.pm_disk_mode	= PM_DISK_FIRMWARE,
+	.prepare	= sa11x0_pm_prepare,
+	.enter		= sa11x0_pm_enter,
+	.finish		= sa11x0_pm_finish,
+};
+
+static int __init sa11x0_pm_init(void)
+{
+	pm_set_ops(&sa11x0_pm_ops);
+	return 0;
+}
+
+late_initcall(sa11x0_pm_init);

drivers/mtd/maps/integrator-flash.c

@@ -31,223 +31,181 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/ioport.h>
+#include <linux/device.h>
 #include <linux/init.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
 
+#include <asm/mach/flash.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include <asm/system.h>
 
-// board specific stuff - sorry, it should be in arch/arm/mach-*.
-#ifdef CONFIG_ARCH_INTEGRATOR
-
-#define FLASH_BASE	INTEGRATOR_FLASH_BASE
-#define FLASH_SIZE	INTEGRATOR_FLASH_SIZE
-
-#define FLASH_PART_SIZE 0x400000
-
-#define SC_CTRLC	(IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
-#define SC_CTRLS	(IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
-#define EBI_CSR1	(IO_ADDRESS(INTEGRATOR_EBI_BASE) + INTEGRATOR_EBI_CSR1_OFFSET)
-#define EBI_LOCK	(IO_ADDRESS(INTEGRATOR_EBI_BASE) + INTEGRATOR_EBI_LOCK_OFFSET)
-
-/*
- * Initialise the flash access systems:
- *  - Disable VPP
- *  - Assert WP
- *  - Set write enable bit in EBI reg
- */
-static void armflash_flash_init(void)
-{
-	unsigned int tmp;
-
-	__raw_writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
-
-	tmp = __raw_readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
-	__raw_writel(tmp, EBI_CSR1);
-
-	if (!(__raw_readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
-		__raw_writel(0xa05f, EBI_LOCK);
-		__raw_writel(tmp, EBI_CSR1);
-		__raw_writel(0, EBI_LOCK);
-	}
-}
-
-/*
- * Shutdown the flash access systems:
- *  - Disable VPP
- *  - Assert WP
- *  - Clear write enable bit in EBI reg
- */
-static void armflash_flash_exit(void)
-{
-	unsigned int tmp;
-
-	__raw_writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
-
-	/*
-	 * Clear the write enable bit in system controller EBI register.
-	 */
-	tmp = __raw_readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
-	__raw_writel(tmp, EBI_CSR1);
-
-	if (__raw_readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
-		__raw_writel(0xa05f, EBI_LOCK);
-		__raw_writel(tmp, EBI_CSR1);
-		__raw_writel(0, EBI_LOCK);
-	}
-}
-
-static void armflash_flash_wp(int on)
-{
-	unsigned int reg;
-
-	if (on)
-		reg = SC_CTRLC;
-	else
-		reg = SC_CTRLS;
-
-	__raw_writel(INTEGRATOR_SC_CTRL_nFLWP, reg);
-}
-
-static void armflash_set_vpp(struct map_info *map, int on)
-{
-	unsigned int reg;
-
-	if (on)
-		reg = SC_CTRLS;
-	else
-		reg = SC_CTRLC;
-
-	__raw_writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
-}
-#endif
-
 #ifdef CONFIG_ARCH_P720T
-
 #define FLASH_BASE		(0x04000000)
 #define FLASH_SIZE		(64*1024*1024)
+#endif
 
-#define FLASH_PART_SIZE 	(4*1024*1024)
-#define FLASH_BLOCK_SIZE	(128*1024)
+struct armflash_info {
+	struct flash_platform_data *plat;
+	struct resource		*res;
+	struct mtd_partition	*parts;
+	struct mtd_info		*mtd;
+	struct map_info		map;
+};
 
-static void armflash_flash_init(void)
+static void armflash_set_vpp(struct map_info *map, int on)
 {
-}
+	struct armflash_info *info = container_of(map, struct armflash_info, map);
 
-static void armflash_flash_exit(void)
-{
+	if (info->plat && info->plat->set_vpp)
+		info->plat->set_vpp(on);
 }
 
-static void armflash_flash_wp(int on)
-{
-}
+static const char *probes[] = { "RedBoot", "afs", NULL };
 
-static void armflash_set_vpp(struct map_info *map, int on)
+static int armflash_probe(struct device *_dev)
 {
-}
-#endif
+	struct platform_device *dev = to_platform_device(_dev);
+	struct flash_platform_data *plat = dev->dev.platform_data;
+	struct resource *res = dev->resource;
+	unsigned int size = res->end - res->start + 1;
+	struct armflash_info *info;
+	int err;
+	void *base;
 
+	info = kmalloc(sizeof(struct armflash_info), GFP_KERNEL);
+	if (!info) {
+		err = -ENOMEM;
+		goto out;
+	}
 
-static struct map_info armflash_map =
-{
-	.name =		"AFS",
-	.set_vpp =	armflash_set_vpp,
-	.phys =		FLASH_BASE,
-};
+	memset(info, 0, sizeof(struct armflash_info));
 
-static struct mtd_info *mtd;
-static struct mtd_partition *parts;
-static const char *probes[] = { "RedBoot", "afs", NULL };
+	info->plat = plat;
+	if (plat && plat->init) {
+		err = plat->init();
+		if (err)
+			goto no_resource;
+	}
 
-static int __init armflash_cfi_init(void *base, u_int size)
-{
-	int ret;
+	info->res = request_mem_region(res->start, size, "armflash");
+	if (!info->res) {
+		err = -EBUSY;
+		goto no_resource;
+	}
 
-	armflash_flash_init();
-	armflash_flash_wp(1);
+	base = ioremap(res->start, size);
+	if (!base) {
+		err = -ENOMEM;
+		goto no_mem;
+	}
 
 	/*
 	 * look for CFI based flash parts fitted to this board
 	 */
-	armflash_map.size       = size;
-	armflash_map.buswidth   = 4;
-	armflash_map.virt = (unsigned long) base;
+	info->map.size		= size;
+	info->map.buswidth	= plat->width;
+	info->map.phys		= res->start;
+	info->map.virt		= (unsigned long) base;
+	info->map.name		= dev->dev.bus_id;
+	info->map.set_vpp	= armflash_set_vpp;
 
-	simple_map_init(&armflash_map);
+	simple_map_init(&info->map);
 
 	/*
 	 * Also, the CFI layer automatically works out what size
 	 * of chips we have, and does the necessary identification
 	 * for us automatically.
 	 */
-	mtd = do_map_probe("cfi_probe", &armflash_map);
-	if (!mtd)
-		return -ENXIO;
-
-	mtd->owner = THIS_MODULE;
-
-	ret = parse_mtd_partitions(mtd, probes, &parts, (void *)0);
-	if (ret > 0) {
-		ret = add_mtd_partitions(mtd, parts, ret);
-		if (ret)
-			printk(KERN_ERR "mtd partition registration "
-				"failed: %d\n", ret);
+	info->mtd = do_map_probe(plat->map_name, &info->map);
+	if (!info->mtd) {
+		err = -ENXIO;
+		goto no_device;
 	}
 
+	info->mtd->owner = THIS_MODULE;
+
+	err = parse_mtd_partitions(info->mtd, probes, &info->parts, 0);
+	if (err > 0) {
+		err = add_mtd_partitions(info->mtd, info->parts, err);
+		if (err)
+			printk(KERN_ERR
+			       "mtd partition registration failed: %d\n", err);
+	}
+
+	if (err == 0)
+		dev_set_drvdata(&dev->dev, info);
+
 	/*
 	 * If we got an error, free all resources.
 	 */
-	if (ret < 0) {
-		del_mtd_partitions(mtd);
-		map_destroy(mtd);
+	if (err < 0) {
+		if (info->mtd) {
+			del_mtd_partitions(info->mtd);
+			map_destroy(info->mtd);
+		}
+		if (info->parts)
+			kfree(info->parts);
+
+ no_device:
+		iounmap(base);
+ no_mem:
+		release_mem_region(res->start, size);
+ no_resource:
+		if (plat && plat->exit)
+			plat->exit();
+		kfree(info);
 	}
-
-	return ret;
+ out:
+	return err;
 }
 
-static void armflash_cfi_exit(void)
+static int armflash_remove(struct device *_dev)
 {
-	if (mtd) {
-		del_mtd_partitions(mtd);
-		map_destroy(mtd);
-	}
-	if (parts)
-		kfree(parts);
-}
+	struct platform_device *dev = to_platform_device(_dev);
+	struct armflash_info *info = dev_get_drvdata(&dev->dev);
 
-static int __init armflash_init(void)
-{
-	int err = -EBUSY;
-	void *base;
+	dev_set_drvdata(&dev->dev, NULL);
 
-	if (request_mem_region(FLASH_BASE, FLASH_SIZE, "flash") == NULL)
-		goto out;
+	if (info) {
+		if (info->mtd) {
+			del_mtd_partitions(info->mtd);
+			map_destroy(info->mtd);
+		}
+		if (info->parts)
+			kfree(info->parts);
 
-	base = ioremap(FLASH_BASE, FLASH_SIZE);
-	err = -ENOMEM;
-	if (base == NULL)
-		goto release;
+		iounmap((void *)info->map.virt);
+		release_resource(info->res);
+		kfree(info->res);
 
-	err = armflash_cfi_init(base, FLASH_SIZE);
-	if (err) {
-		iounmap(base);
-release:
-		release_mem_region(FLASH_BASE, FLASH_SIZE);
+		if (info->plat && info->plat->exit)
+			info->plat->exit();
+
+		kfree(info);
 	}
-out:
-	return err;
+
+	return 0;
+}
+
+static struct device_driver armflash_driver = {
+	.name		= "armflash",
+	.bus		= &platform_bus_type,
+	.probe		= armflash_probe,
+	.remove		= armflash_remove,
+};
+
+static int __init armflash_init(void)
+{
+	return driver_register(&armflash_driver);
 }
 
 static void __exit armflash_exit(void)
 {
-	armflash_cfi_exit();
-	iounmap((void *)armflash_map.virt);
-	release_mem_region(FLASH_BASE, FLASH_SIZE);
-	armflash_flash_exit();
+	driver_unregister(&armflash_driver);
 }
 
 module_init(armflash_init);

include/asm-arm/arch-integrator/irqs.h

@@ -19,116 +19,39 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-/* Use the integrator definitions */
-#include <asm/arch/platform.h>
-
-/* 
- *  IRQ interrupts definitions are the same the INT definitions
- *  held within platform.h
- */
-#define IRQ_SOFTINT                     INT_SOFTINT
-#define IRQ_UARTINT0                    INT_UARTINT0
-#define IRQ_UARTINT1                    INT_UARTINT1
-#define IRQ_KMIINT0                     INT_KMIINT0
-#define IRQ_KMIINT1                     INT_KMIINT1
-#define IRQ_TIMERINT0                   INT_TIMERINT0
-#define IRQ_TIMERINT1                   INT_TIMERINT1
-#define IRQ_TIMERINT2                   INT_TIMERINT2
-#define IRQ_RTCINT                      INT_RTCINT
-#define IRQ_EXPINT0                     INT_EXPINT0
-#define IRQ_EXPINT1                     INT_EXPINT1
-#define IRQ_EXPINT2                     INT_EXPINT2
-#define IRQ_EXPINT3                     INT_EXPINT3
-#define IRQ_PCIINT0                     INT_PCIINT0
-#define IRQ_PCIINT1                     INT_PCIINT1
-#define IRQ_PCIINT2                     INT_PCIINT2
-#define IRQ_PCIINT3                     INT_PCIINT3
-#define IRQ_V3INT                       INT_V3INT
-#define IRQ_CPINT0                      INT_CPINT0
-#define IRQ_CPINT1                      INT_CPINT1
-#define IRQ_LBUSTIMEOUT                 INT_LBUSTIMEOUT
-#define IRQ_APCINT                      INT_APCINT
-
-#define IRQMASK_SOFTINT                 INTMASK_SOFTINT
-#define IRQMASK_UARTINT0                INTMASK_UARTINT0
-#define IRQMASK_UARTINT1                INTMASK_UARTINT1
-#define IRQMASK_KMIINT0                 INTMASK_KMIINT0
-#define IRQMASK_KMIINT1                 INTMASK_KMIINT1
-#define IRQMASK_TIMERINT0               INTMASK_TIMERINT0
-#define IRQMASK_TIMERINT1               INTMASK_TIMERINT1
-#define IRQMASK_TIMERINT2               INTMASK_TIMERINT2
-#define IRQMASK_RTCINT                  INTMASK_RTCINT
-#define IRQMASK_EXPINT0                 INTMASK_EXPINT0
-#define IRQMASK_EXPINT1                 INTMASK_EXPINT1
-#define IRQMASK_EXPINT2                 INTMASK_EXPINT2
-#define IRQMASK_EXPINT3                 INTMASK_EXPINT3
-#define IRQMASK_PCIINT0                 INTMASK_PCIINT0
-#define IRQMASK_PCIINT1                 INTMASK_PCIINT1
-#define IRQMASK_PCIINT2                 INTMASK_PCIINT2
-#define IRQMASK_PCIINT3                 INTMASK_PCIINT3
-#define IRQMASK_V3INT                   INTMASK_V3INT
-#define IRQMASK_CPINT0                  INTMASK_CPINT0
-#define IRQMASK_CPINT1                  INTMASK_CPINT1
-#define IRQMASK_LBUSTIMEOUT             INTMASK_LBUSTIMEOUT
-#define IRQMASK_APCINT                  INTMASK_APCINT
-
 /* 
- *  FIQ interrupts definitions are the same the INT definitions.
+ *  Interrupt numbers
  */
-#define FIQ_SOFTINT                     INT_SOFTINT
-#define FIQ_UARTINT0                    INT_UARTINT0
-#define FIQ_UARTINT1                    INT_UARTINT1
-#define FIQ_KMIINT0                     INT_KMIINT0
-#define FIQ_KMIINT1                     INT_KMIINT1
-#define FIQ_TIMERINT0                   INT_TIMERINT0
-#define FIQ_TIMERINT1                   INT_TIMERINT1
-#define FIQ_TIMERINT2                   INT_TIMERINT2
-#define FIQ_RTCINT                      INT_RTCINT
-#define FIQ_EXPINT0                     INT_EXPINT0
-#define FIQ_EXPINT1                     INT_EXPINT1
-#define FIQ_EXPINT2                     INT_EXPINT2
-#define FIQ_EXPINT3                     INT_EXPINT3
-#define FIQ_PCIINT0                     INT_PCIINT0
-#define FIQ_PCIINT1                     INT_PCIINT1
-#define FIQ_PCIINT2                     INT_PCIINT2
-#define FIQ_PCIINT3                     INT_PCIINT3
-#define FIQ_V3INT                       INT_V3INT
-#define FIQ_CPINT0                      INT_CPINT0
-#define FIQ_CPINT1                      INT_CPINT1
-#define FIQ_LBUSTIMEOUT                 INT_LBUSTIMEOUT
-#define FIQ_APCINT                      INT_APCINT
-
-#define FIQMASK_SOFTINT                 INTMASK_SOFTINT
-#define FIQMASK_UARTINT0                INTMASK_UARTINT0
-#define FIQMASK_UARTINT1                INTMASK_UARTINT1
-#define FIQMASK_KMIINT0                 INTMASK_KMIINT0
-#define FIQMASK_KMIINT1                 INTMASK_KMIINT1
-#define FIQMASK_TIMERINT0               INTMASK_TIMERINT0
-#define FIQMASK_TIMERINT1               INTMASK_TIMERINT1
-#define FIQMASK_TIMERINT2               INTMASK_TIMERINT2
-#define FIQMASK_RTCINT                  INTMASK_RTCINT
-#define FIQMASK_EXPINT0                 INTMASK_EXPINT0
-#define FIQMASK_EXPINT1                 INTMASK_EXPINT1
-#define FIQMASK_EXPINT2                 INTMASK_EXPINT2
-#define FIQMASK_EXPINT3                 INTMASK_EXPINT3
-#define FIQMASK_PCIINT0                 INTMASK_PCIINT0
-#define FIQMASK_PCIINT1                 INTMASK_PCIINT1
-#define FIQMASK_PCIINT2                 INTMASK_PCIINT2
-#define FIQMASK_PCIINT3                 INTMASK_PCIINT3
-#define FIQMASK_V3INT                   INTMASK_V3INT
-#define FIQMASK_CPINT0                  INTMASK_CPINT0
-#define FIQMASK_CPINT1                  INTMASK_CPINT1
-#define FIQMASK_LBUSTIMEOUT             INTMASK_LBUSTIMEOUT
-#define FIQMASK_APCINT                  INTMASK_APCINT
-
-/* 
- *  Misc. interrupt definitions
- */
-#define IRQ_KEYBDINT                    INT_KMIINT0
-#define IRQ_MOUSEINT                    INT_KMIINT1
-
-#define IRQMASK_KEYBDINT                INTMASK_KMIINT0
-#define IRQMASK_MOUSEINT                INTMASK_KMIINT1
-
-#define NR_IRQS                         (MAXIRQNUM + 1)
+#define IRQ_PIC_START			0
+#define IRQ_SOFTINT			0
+#define IRQ_UARTINT0			1
+#define IRQ_UARTINT1			2
+#define IRQ_KMIINT0			3
+#define IRQ_KMIINT1			4
+#define IRQ_TIMERINT0			5
+#define IRQ_TIMERINT1			6
+#define IRQ_TIMERINT2			7
+#define IRQ_RTCINT			8
+#define IRQ_AP_EXPINT0			9
+#define IRQ_AP_EXPINT1			10
+#define IRQ_AP_EXPINT2			11
+#define IRQ_AP_EXPINT3			12
+#define IRQ_AP_PCIINT0			13
+#define IRQ_AP_PCIINT1			14
+#define IRQ_AP_PCIINT2			15
+#define IRQ_AP_PCIINT3			16
+#define IRQ_AP_V3INT			17
+#define IRQ_AP_CPINT0			18
+#define IRQ_AP_CPINT1			19
+#define IRQ_AP_LBUSTIMEOUT 		20
+#define IRQ_AP_APCINT			21
+#define IRQ_PIC_END			31
+
+#define IRQ_CIC_START			32
+#define IRQ_CM_SOFTINT			32
+#define IRQ_CM_COMMRX			33
+#define IRQ_CM_COMMTX			34
+#define IRQ_CIC_END			34
+
+#define NR_IRQS                         47
 

include/asm-arm/arch-integrator/platform.h

@@ -386,85 +386,6 @@
  * 
  */
 
-/* 
- *  As the interrupt bit definitions for FIQ/IRQ there is a common
- *  set of definitions prefixed INT/INTMASK.  The FIQ/IRQ definitions
- *  have been left to maintain backwards compatible.
- * 
- */
-
-/* 
- *  Interrupt numbers
- * 
- */
-#define INT_SOFTINT                     0
-#define INT_UARTINT0                    1
-#define INT_UARTINT1                    2
-#define INT_KMIINT0                     3
-#define INT_KMIINT1                     4
-#define INT_TIMERINT0                   5
-#define INT_TIMERINT1                   6
-#define INT_TIMERINT2                   7
-#define INT_RTCINT                      8
-#define INT_EXPINT0                     9
-#define INT_EXPINT1                     10
-#define INT_EXPINT2                     11
-#define INT_EXPINT3                     12
-#define INT_PCIINT0                     13
-#define INT_PCIINT1                     14
-#define INT_PCIINT2                     15
-#define INT_PCIINT3                     16
-#define INT_V3INT                       17
-#define INT_CPINT0                      18
-#define INT_CPINT1                      19
-#define INT_LBUSTIMEOUT                 20
-#define INT_APCINT                      21
-#define INT_CM_SOFTINT                  24
-#define INT_CM_COMMRX                   25
-#define INT_CM_COMMTX                   26
-
-/* 
- *  Interrupt bit positions
- * 
- */
-#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
-#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
-#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
-#define INTMASK_KMIINT0                 (1 << INT_KMIINT0)
-#define INTMASK_KMIINT1                 (1 << INT_KMIINT1)
-#define INTMASK_TIMERINT0               (1 << INT_TIMERINT0)
-#define INTMASK_TIMERINT1               (1 << INT_TIMERINT1)
-#define INTMASK_TIMERINT2               (1 << INT_TIMERINT2)
-#define INTMASK_RTCINT                  (1 << INT_RTCINT)
-#define INTMASK_EXPINT0                 (1 << INT_EXPINT0)
-#define INTMASK_EXPINT1                 (1 << INT_EXPINT1)
-#define INTMASK_EXPINT2                 (1 << INT_EXPINT2)
-#define INTMASK_EXPINT3                 (1 << INT_EXPINT3)
-#define INTMASK_PCIINT0                 (1 << INT_PCIINT0)
-#define INTMASK_PCIINT1                 (1 << INT_PCIINT1)
-#define INTMASK_PCIINT2                 (1 << INT_PCIINT2)
-#define INTMASK_PCIINT3                 (1 << INT_PCIINT3)
-#define INTMASK_V3INT                   (1 << INT_V3INT)
-#define INTMASK_CPINT0                  (1 << INT_CPINT0)
-#define INTMASK_CPINT1                  (1 << INT_CPINT1)
-#define INTMASK_LBUSTIMEOUT             (1 << INT_LBUSTIMEOUT)
-#define INTMASK_APCINT                  (1 << INT_APCINT)
-#define INTMASK_CM_SOFTINT              (1 << INT_CM_SOFTINT)
-#define INTMASK_CM_COMMRX               (1 << INT_CM_COMMRX)
-#define INTMASK_CM_COMMTX               (1 << INT_CM_COMMTX)
-
-/* 
- *  INTEGRATOR_CM_INT0      - Interrupt number of first CM interrupt
- *  INTEGRATOR_SC_VALID_INT - Mask of valid system controller interrupts
- * 
- */
-#define INTEGRATOR_CM_INT0              INT_CM_SOFTINT
-#define INTEGRATOR_SC_VALID_INT         0x003FFFFF
-
-#define MAXIRQNUM                       31
-#define MAXFIQNUM                       31
-#define MAXSWINUM                       31
- 
 /* ------------------------------------------------------------------------
  *  LED's - The header LED is not accessible via the uHAL API
  * ------------------------------------------------------------------------

include/asm-arm/arch-integrator/time.h

@@ -86,7 +86,7 @@ static unsigned long integrator_gettimeoffset(void)
 	/*
 	 * Interrupt pending?  If so, we've reloaded once already.
 	 */
-	if (status & IRQMASK_TIMERINT1)
+	if (status & (1 << IRQ_TIMERINT1))
 		ticks1 += TIMER_RELOAD;
 
 	/*

include/asm-arm/arch-pxa/irqs.h

@@ -13,7 +13,7 @@
 #include <linux/config.h>
 
 #define PXA_IRQ_SKIP	7	/* The first 7 IRQs are not yet used */
-#define PXA_IRQ(x)		((x) - PXA_IRQ_SKIP)
+#define PXA_IRQ(x)	((x) - PXA_IRQ_SKIP)
 
 #define IRQ_HWUART	PXA_IRQ(7)	/* HWUART Transmit/Receive/Error */
 #define	IRQ_GPIO0	PXA_IRQ(8)	/* GPIO0 Edge Detect */
@@ -47,7 +47,7 @@
 
 #define IRQ_TO_GPIO_2_80(i)	\
 			((i) - PXA_IRQ(32) + 2)
-#define IRQ_TO_GPIO(i)	((i) - (((i) > IRQ_GPIO1) ? IRQ_GPIO(2) : IRQ_GPIO(0)))
+#define IRQ_TO_GPIO(i)	((i) - (((i) > IRQ_GPIO1) ? IRQ_GPIO(2) - 2 : IRQ_GPIO(0)))
 
 /*
  * The next 16 interrupts are for board specific purposes.  Since
@@ -131,8 +131,10 @@
 #define LUBBOCK_IRQ(x)		(IRQ_BOARD_START + (x))
 #define LUBBOCK_SD_IRQ		LUBBOCK_IRQ(0)
 #define LUBBOCK_SA1111_IRQ	LUBBOCK_IRQ(1)
-#define LUBBOCK_USB_IRQ		LUBBOCK_IRQ(2)
+#define LUBBOCK_USB_IRQ		LUBBOCK_IRQ(2)  /* usb connect */
 #define LUBBOCK_ETH_IRQ		LUBBOCK_IRQ(3)
 #define LUBBOCK_UCB1400_IRQ	LUBBOCK_IRQ(4)
 #define LUBBOCK_BB_IRQ		LUBBOCK_IRQ(5)
+#define LUBBOCK_USB_DISC_IRQ	LUBBOCK_IRQ(6)  /* usb disconnect */
+#define LUBBOCK_LAST_IRQ	LUBBOCK_IRQ(6)
 

include/asm-arm/arch-pxa/lubbock.h

@@ -12,7 +12,8 @@
 
 #define LUBBOCK_FPGA_PHYS	PXA_CS2_PHYS
 #define LUBBOCK_FPGA_VIRT	(0xf0000000)	/* phys 0x08000000 */
-#define LUBBOCK_ETH_BASE	(0xf1000000)	/* phys 0x0c000000 */
+#define LUBBOCK_ETH_PHYS	PXA_CS3_PHYS
+#define LUBBOCK_ETH_VIRT	(0xf1000000)
 
 #define LUB_P2V(x)		((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
 #define LUB_V2P(x)		((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)

include/asm-arm/mach/flash.h

+/*
+ *  linux/include/asm-arm/mach/flash.h
+ *
+ *  Copyright (C) 2003 Russell King, All Rights Reserved.
+ */
+#ifndef ASMARM_MACH_FLASH_H
+#define ASMAMR_MACH_FLASH_H
+
+struct mtd_partition;
+
+struct flash_platform_data {
+	const char	*map_name;
+	int		width;
+	int		(*init)(void);
+	void		(*exit)(void);
+	void		(*set_vpp)(int on);
+};
+
+#endif

include/asm-arm/unistd.h

@@ -32,7 +32,7 @@
 #define __NR_write			(__NR_SYSCALL_BASE+  4)
 #define __NR_open			(__NR_SYSCALL_BASE+  5)
 #define __NR_close			(__NR_SYSCALL_BASE+  6)
-#define __NR_waitpid			(__NR_SYSCALL_BASE+  7)	/* removed */
+					/* 7 was sys_waitpid */
 #define __NR_creat			(__NR_SYSCALL_BASE+  8)
 #define __NR_link			(__NR_SYSCALL_BASE+  9)
 #define __NR_unlink			(__NR_SYSCALL_BASE+ 10)
@@ -42,7 +42,7 @@
 #define __NR_mknod			(__NR_SYSCALL_BASE+ 14)
 #define __NR_chmod			(__NR_SYSCALL_BASE+ 15)
 #define __NR_lchown			(__NR_SYSCALL_BASE+ 16)
-#define __NR_break			(__NR_SYSCALL_BASE+ 17)	/* removed */
+					/* 17 was sys_break */
 					/* 18 was sys_stat */
 #define __NR_lseek			(__NR_SYSCALL_BASE+ 19)
 #define __NR_getpid			(__NR_SYSCALL_BASE+ 20)
@@ -53,14 +53,14 @@
 #define __NR_stime			(__NR_SYSCALL_BASE+ 25)
 #define __NR_ptrace			(__NR_SYSCALL_BASE+ 26)
 #define __NR_alarm			(__NR_SYSCALL_BASE+ 27)
-
+					/* 28 was sys_fstat */
 #define __NR_pause			(__NR_SYSCALL_BASE+ 29)
 #define __NR_utime			(__NR_SYSCALL_BASE+ 30)
-#define __NR_stty			(__NR_SYSCALL_BASE+ 31)	/* removed */
-#define __NR_gtty			(__NR_SYSCALL_BASE+ 32)	/* removed */
+					/* 31 was sys_stty */
+					/* 32 was sys_gtty */
 #define __NR_access			(__NR_SYSCALL_BASE+ 33)
 #define __NR_nice			(__NR_SYSCALL_BASE+ 34)
-#define __NR_ftime			(__NR_SYSCALL_BASE+ 35)	/* removed */
+					/* 35 was sys_ftime */
 #define __NR_sync			(__NR_SYSCALL_BASE+ 36)
 #define __NR_kill			(__NR_SYSCALL_BASE+ 37)
 #define __NR_rename			(__NR_SYSCALL_BASE+ 38)
@@ -69,21 +69,21 @@
 #define __NR_dup			(__NR_SYSCALL_BASE+ 41)
 #define __NR_pipe			(__NR_SYSCALL_BASE+ 42)
 #define __NR_times			(__NR_SYSCALL_BASE+ 43)
-#define __NR_prof			(__NR_SYSCALL_BASE+ 44)	/* removed */
+					/* 44 was sys_prof */
 #define __NR_brk			(__NR_SYSCALL_BASE+ 45)
 #define __NR_setgid			(__NR_SYSCALL_BASE+ 46)
 #define __NR_getgid			(__NR_SYSCALL_BASE+ 47)
-#define __NR_signal			(__NR_SYSCALL_BASE+ 48)	/* removed */
+					/* 48 was sys_signal */
 #define __NR_geteuid			(__NR_SYSCALL_BASE+ 49)
 #define __NR_getegid			(__NR_SYSCALL_BASE+ 50)
 #define __NR_acct			(__NR_SYSCALL_BASE+ 51)
 #define __NR_umount2			(__NR_SYSCALL_BASE+ 52)
-#define __NR_lock			(__NR_SYSCALL_BASE+ 53)	/* removed */
+					/* 53 was sys_lock */
 #define __NR_ioctl			(__NR_SYSCALL_BASE+ 54)
 #define __NR_fcntl			(__NR_SYSCALL_BASE+ 55)
-#define __NR_mpx			(__NR_SYSCALL_BASE+ 56)	/* removed */
+					/* 56 was sys_mpx */
 #define __NR_setpgid			(__NR_SYSCALL_BASE+ 57)
-#define __NR_ulimit			(__NR_SYSCALL_BASE+ 58)	/* removed */
+					/* 58 was sys_ulimit */
 					/* 59 was sys_olduname */
 #define __NR_umask			(__NR_SYSCALL_BASE+ 60)
 #define __NR_chroot			(__NR_SYSCALL_BASE+ 61)
@@ -93,8 +93,8 @@
 #define __NR_getpgrp			(__NR_SYSCALL_BASE+ 65)
 #define __NR_setsid			(__NR_SYSCALL_BASE+ 66)
 #define __NR_sigaction			(__NR_SYSCALL_BASE+ 67)
-#define __NR_sgetmask			(__NR_SYSCALL_BASE+ 68)	/* removed */
-#define __NR_ssetmask			(__NR_SYSCALL_BASE+ 69)	/* removed */
+					/* 68 was sys_sgetmask */
+					/* 69 was sys_ssetmask */
 #define __NR_setreuid			(__NR_SYSCALL_BASE+ 70)
 #define __NR_setregid			(__NR_SYSCALL_BASE+ 71)
 #define __NR_sigsuspend			(__NR_SYSCALL_BASE+ 72)
@@ -123,10 +123,10 @@
 #define __NR_fchown			(__NR_SYSCALL_BASE+ 95)
 #define __NR_getpriority		(__NR_SYSCALL_BASE+ 96)
 #define __NR_setpriority		(__NR_SYSCALL_BASE+ 97)
-#define __NR_profil			(__NR_SYSCALL_BASE+ 98)	/* removed */
+					/* 98 was sys_profil */
 #define __NR_statfs			(__NR_SYSCALL_BASE+ 99)
 #define __NR_fstatfs			(__NR_SYSCALL_BASE+100)
-#define __NR_ioperm			(__NR_SYSCALL_BASE+101)
+					/* 101 was sys_ioperm */
 #define __NR_socketcall			(__NR_SYSCALL_BASE+102)
 #define __NR_syslog			(__NR_SYSCALL_BASE+103)
 #define __NR_setitimer			(__NR_SYSCALL_BASE+104)
@@ -137,7 +137,7 @@
 					/* 109 was sys_uname */
 					/* 110 was sys_iopl */
 #define __NR_vhangup			(__NR_SYSCALL_BASE+111)
-#define __NR_idle			(__NR_SYSCALL_BASE+112)
+					/* 112 was sys_idle */
 #define __NR_syscall			(__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */
 #define __NR_wait4			(__NR_SYSCALL_BASE+114)
 #define __NR_swapoff			(__NR_SYSCALL_BASE+115)
@@ -148,21 +148,21 @@
 #define __NR_clone			(__NR_SYSCALL_BASE+120)
 #define __NR_setdomainname		(__NR_SYSCALL_BASE+121)
 #define __NR_uname			(__NR_SYSCALL_BASE+122)
-#define __NR_modify_ldt			(__NR_SYSCALL_BASE+123)
+					/* 123 was sys_modify_ldt */
 #define __NR_adjtimex			(__NR_SYSCALL_BASE+124)
 #define __NR_mprotect			(__NR_SYSCALL_BASE+125)
 #define __NR_sigprocmask		(__NR_SYSCALL_BASE+126)
-#define __NR_create_module		(__NR_SYSCALL_BASE+127)	/* removed */
+					/* 127 was sys_create_module */
 #define __NR_init_module		(__NR_SYSCALL_BASE+128)
 #define __NR_delete_module		(__NR_SYSCALL_BASE+129)
-#define __NR_get_kernel_syms		(__NR_SYSCALL_BASE+130)	/* removed */
+					/* 130 was sys_get_kernel_syms */
 #define __NR_quotactl			(__NR_SYSCALL_BASE+131)
 #define __NR_getpgid			(__NR_SYSCALL_BASE+132)
 #define __NR_fchdir			(__NR_SYSCALL_BASE+133)
 #define __NR_bdflush			(__NR_SYSCALL_BASE+134)
 #define __NR_sysfs			(__NR_SYSCALL_BASE+135)
 #define __NR_personality		(__NR_SYSCALL_BASE+136)
-#define __NR_afs_syscall		(__NR_SYSCALL_BASE+137) /* Syscall for Andrew File System */
+					/* 137 was sys_afs_syscall */
 #define __NR_setfsuid			(__NR_SYSCALL_BASE+138)
 #define __NR_setfsgid			(__NR_SYSCALL_BASE+139)
 #define __NR__llseek			(__NR_SYSCALL_BASE+140)
@@ -191,8 +191,8 @@
 #define __NR_mremap			(__NR_SYSCALL_BASE+163)
 #define __NR_setresuid			(__NR_SYSCALL_BASE+164)
 #define __NR_getresuid			(__NR_SYSCALL_BASE+165)
-#define __NR_vm86			(__NR_SYSCALL_BASE+166)	/* removed */
-#define __NR_query_module		(__NR_SYSCALL_BASE+167)	/* removed */
+					/* 166 was sys_vm86 */
+					/* 167 was sys_query_module */
 #define __NR_poll			(__NR_SYSCALL_BASE+168)
 #define __NR_nfsservctl			(__NR_SYSCALL_BASE+169)
 #define __NR_setresgid			(__NR_SYSCALL_BASE+170)