Commit a330a9c5 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Paul Burton

MIPS: Octeon: move swiotlb declarations out of dma-coherence.h

No need to pull them into a global header.
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Patchwork: https://patchwork.linux-mips.org/patch/19538/Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: Tom Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: iommu@lists.linux-foundation.org
Cc: linux-mips@linux-mips.org
parent 1f99e4b1
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
#include <linux/bug.h>
struct device;
extern void octeon_pci_dma_init(void);
extern char *octeon_swiotlb;
#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
...@@ -63,4 +63,7 @@ enum octeon_dma_bar_type { ...@@ -63,4 +63,7 @@ enum octeon_dma_bar_type {
*/ */
extern enum octeon_dma_bar_type octeon_dma_bar_type; extern enum octeon_dma_bar_type octeon_dma_bar_type;
void octeon_pci_dma_init(void);
extern char *octeon_swiotlb;
#endif #endif
...@@ -21,8 +21,6 @@ ...@@ -21,8 +21,6 @@
#include <asm/octeon/cvmx-pci-defs.h> #include <asm/octeon/cvmx-pci-defs.h>
#include <asm/octeon/pci-octeon.h> #include <asm/octeon/pci-octeon.h>
#include <dma-coherence.h>
#define USE_OCTEON_INTERNAL_ARBITER #define USE_OCTEON_INTERNAL_ARBITER
/* /*
......
...@@ -94,8 +94,6 @@ union cvmx_pcie_address { ...@@ -94,8 +94,6 @@ union cvmx_pcie_address {
static int cvmx_pcie_rc_initialize(int pcie_port); static int cvmx_pcie_rc_initialize(int pcie_port);
#include <dma-coherence.h>
/** /**
* Return the Core virtual base address for PCIe IO access. IOs are * Return the Core virtual base address for PCIe IO access. IOs are
* read/written as an offset from this address. * read/written as an offset from this address.
......
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