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Commit a3a3c466 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge branch 'davinci/cleanups' into next/cleanup 

* davinci/cleanups:
  ARM: davinci: add back dummy header files
  ARM: davinci: dm644x: don't force vpfe registeration on all boards
  ARM: davinci: dm644x: fix inconsistent variable naming
  ARM: davinci: dm644x: improve readability using macro
  ARM: davinci: streamline sysmod access
  ARM: davinci: create new common platform header for davinci
  ARM: davinci: dm646x: move private definitions to C file
  ARM: davinci: dm365: move private definitions to C file
  ARM: davinci: dm644x: move private definitions to C file

Conflicts:
	arch/arm/mach-davinci/board-dm644x-evm.c
	arch/arm/mach-davinci/board-neuros-osd2.c
	arch/arm/mach-davinci/board-sffsdr.c
parents 96a3eab3 6ea96e11
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Showing with 220 additions and 255 deletions
arch/arm/mach-davinci/board-dm355-evm.c
View file @ a3a3c466
......@@ -26,13 +26,14 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dm355.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/nand.h>
#include <mach/mmc.h>
#include <mach/usb.h>
#include "davinci.h"
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
......
arch/arm/mach-davinci/board-dm355-leopard.c
View file @ a3a3c466
......@@ -23,13 +23,14 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dm355.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/nand.h>
#include <mach/mmc.h>
#include <mach/usb.h>
#include "davinci.h"
/* NOTE: this is geared for the standard config, with a socketed
* 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you
* swap chips, maybe with a different block size, partitioning may
......
arch/arm/mach-davinci/board-dm365-evm.c
View file @ a3a3c466
......@@ -32,7 +32,6 @@
#include <asm/mach/arch.h>
#include <mach/mux.h>
#include <mach/dm365.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
......@@ -42,6 +41,8 @@
#include <media/tvp514x.h>
#include "davinci.h"
static inline int have_imager(void)
{
/* REVISIT when it's supported, trigger via Kconfig */
......
arch/arm/mach-davinci/board-dm644x-evm.c
View file @ a3a3c466
......@@ -30,7 +30,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dm644x.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
......@@ -40,6 +39,8 @@
#include <mach/usb.h>
#include <mach/aemif.h>
#include "davinci.h"
#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
#define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0)
......@@ -189,7 +190,7 @@ static struct platform_device davinci_fb_device = {
.num_resources = 0,
};
static struct tvp514x_platform_data tvp5146_pdata = {
static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
.clk_polarity = 0,
.hs_polarity = 1,
.vs_polarity = 1
......@@ -197,7 +198,7 @@ static struct tvp514x_platform_data tvp5146_pdata = {
#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
/* Inputs available at the TVP5146 */
static struct v4l2_input tvp5146_inputs[] = {
static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
{
.index = 0,
.name = "Composite",
......@@ -217,7 +218,7 @@ static struct v4l2_input tvp5146_inputs[] = {
* ouput that goes to vpfe. There is a one to one correspondence
* with tvp5146_inputs
*/
static struct vpfe_route tvp5146_routes[] = {
static struct vpfe_route dm644xevm_tvp5146_routes[] = {
{
.input = INPUT_CVBS_VI2B,
.output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
......@@ -228,13 +229,13 @@ static struct vpfe_route tvp5146_routes[] = {
},
};
static struct vpfe_subdev_info vpfe_sub_devs[] = {
static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
{
.name = "tvp5146",
.grp_id = 0,
.num_inputs = ARRAY_SIZE(tvp5146_inputs),
.inputs = tvp5146_inputs,
.routes = tvp5146_routes,
.num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
.inputs = dm644xevm_tvp5146_inputs,
.routes = dm644xevm_tvp5146_routes,
.can_route = 1,
.ccdc_if_params = {
.if_type = VPFE_BT656,
......@@ -243,15 +244,15 @@ static struct vpfe_subdev_info vpfe_sub_devs[] = {
},
.board_info = {
I2C_BOARD_INFO("tvp5146", 0x5d),
.platform_data = &tvp5146_pdata,
.platform_data = &dm644xevm_tvp5146_pdata,
},
},
};
static struct vpfe_config vpfe_cfg = {
.num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
static struct vpfe_config dm644xevm_capture_cfg = {
.num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
.i2c_adapter_id = 1,
.sub_devs = vpfe_sub_devs,
.sub_devs = dm644xevm_vpfe_sub_devs,
.card_name = "DM6446 EVM",
.ccdc = "DM6446 CCDC",
};
......@@ -624,8 +625,6 @@ static struct davinci_uart_config uart_config __initdata = {
static void __init
davinci_evm_map_io(void)
{
/* setup input configuration for VPFE input devices */
dm644x_set_vpfe_config(&vpfe_cfg);
dm644x_init();
}
......@@ -697,6 +696,7 @@ static __init void davinci_evm_init(void)
evm_init_i2c();
davinci_setup_mmc(0, &dm6446evm_mmc_config);
dm644x_init_video(&dm644xevm_capture_cfg);
davinci_serial_init(&uart_config);
dm644x_init_asp(&dm644x_evm_snd_data);
......
arch/arm/mach-davinci/board-dm646x-evm.c
View file @ a3a3c466
......@@ -36,7 +36,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dm646x.h>
#include <mach/common.h>
#include <mach/serial.h>
#include <mach/i2c.h>
......@@ -45,6 +44,7 @@
#include <mach/cdce949.h>
#include <mach/aemif.h>
#include "davinci.h"
#include "clock.h"
#define NAND_BLOCK_SIZE SZ_128K
......@@ -410,8 +410,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
.bus_delay = 0 /* usec */,
};
#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
#define VCH2CLK_SYSCLK8 (BIT(9))
#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
......@@ -429,8 +427,6 @@ static struct davinci_i2c_platform_data i2c_pdata = {
#define TVP5147_CH0 "tvp514x-0"
#define TVP5147_CH1 "tvp514x-1"
static void __iomem *vpif_vidclkctl_reg;
static void __iomem *vpif_vsclkdis_reg;
/* spin lock for updating above registers */
static spinlock_t vpif_reg_lock;
......@@ -441,14 +437,14 @@ static int set_vpif_clock(int mux_mode, int hd)
int val = 0;
int err = 0;
if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
if (!cpld_client)
return -ENXIO;
/* disable the clock */
spin_lock_irqsave(&vpif_reg_lock, flags);
value = __raw_readl(vpif_vsclkdis_reg);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
value |= (VIDCH3CLK | VIDCH2CLK);
__raw_writel(value, vpif_vsclkdis_reg);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
spin_unlock_irqrestore(&vpif_reg_lock, flags);
val = i2c_smbus_read_byte(cpld_client);
......@@ -464,7 +460,7 @@ static int set_vpif_clock(int mux_mode, int hd)
if (err)
return err;
value = __raw_readl(vpif_vidclkctl_reg);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
value &= ~(VCH2CLK_MASK);
value &= ~(VCH3CLK_MASK);
......@@ -473,13 +469,13 @@ static int set_vpif_clock(int mux_mode, int hd)
else
value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
__raw_writel(value, vpif_vidclkctl_reg);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
spin_lock_irqsave(&vpif_reg_lock, flags);
value = __raw_readl(vpif_vsclkdis_reg);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
/* enable the clock */
value &= ~(VIDCH3CLK | VIDCH2CLK);
__raw_writel(value, vpif_vsclkdis_reg);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
spin_unlock_irqrestore(&vpif_reg_lock, flags);
return 0;
......@@ -564,7 +560,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
int val;
u32 value;
if (!vpif_vidclkctl_reg || !cpld_client)
if (!cpld_client)
return -ENXIO;
val = i2c_smbus_read_byte(cpld_client);
......@@ -572,7 +568,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
return val;
spin_lock_irqsave(&vpif_reg_lock, flags);
value = __raw_readl(vpif_vidclkctl_reg);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
if (mux_mode) {
val &= VPIF_INPUT_TWO_CHANNEL;
value |= VIDCH1CLK;
......@@ -580,7 +576,7 @@ static int setup_vpif_input_channel_mode(int mux_mode)
val |= VPIF_INPUT_ONE_CHANNEL;
value &= ~VIDCH1CLK;
}
__raw_writel(value, vpif_vidclkctl_reg);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VIDCLKCTL));
spin_unlock_irqrestore(&vpif_reg_lock, flags);
err = i2c_smbus_write_byte(cpld_client, val);
......@@ -674,12 +670,6 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
static void __init evm_init_video(void)
{
vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
return;
}
spin_lock_init(&vpif_reg_lock);
dm646x_setup_vpif(&dm646x_vpif_display_config,
......
arch/arm/mach-davinci/board-neuros-osd2.c
View file @ a3a3c466
......@@ -30,7 +30,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/dm644x.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
......@@ -39,6 +38,8 @@
#include <mach/mmc.h>
#include <mach/usb.h>
#include "davinci.h"
#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
#define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0
......
arch/arm/mach-davinci/board-sffsdr.c
View file @ a3a3c466
......@@ -35,13 +35,14 @@
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <mach/dm644x.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mux.h>
#include <mach/usb.h>
#include "davinci.h"
#define SFFSDR_PHY_ID "davinci_mdio-0:01"
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0
......
arch/arm/mach-davinci/davinci.h 0 → 100644
View file @ a3a3c466
/*
* This file contains the processor specific definitions
* of the TI DM644x, DM355, DM365, and DM646x.
*
* Copyright (C) 2011 Texas Instruments Incorporated
* Copyright (c) 2007 Deep Root Systems, LLC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DAVINCI_H
#define __DAVINCI_H
#include <linux/clk.h>
#include <linux/videodev2.h>
#include <linux/davinci_emac.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <mach/asp.h>
#include <mach/keyscan.h>
#include <mach/hardware.h>
#include <media/davinci/vpfe_capture.h>
#include <media/davinci/vpif_types.h>
#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
#define SYSMOD_VIDCLKCTL 0x38
#define SYSMOD_VDD3P3VPWDN 0x48
#define SYSMOD_VSCLKDIS 0x6c
#define SYSMOD_PUPDCTL1 0x7c
extern void __iomem *davinci_sysmod_base;
#define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x))
void davinci_map_sysmod(void);
/* DM355 base addresses */
#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000
#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define ASP1_TX_EVT_EN 1
#define ASP1_RX_EVT_EN 2
/* DM365 base addresses */
#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
/* DM644x base addresses */
#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000
#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
/* DM646x base addresses */
#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
/* DM355 function declarations */
void __init dm355_init(void);
void dm355_init_spi0(unsigned chipselect_mask,
struct spi_board_info *info, unsigned len);
void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
void dm355_set_vpfe_config(struct vpfe_config *cfg);
/* DM365 function declarations */
void __init dm365_init(void);
void __init dm365_init_asp(struct snd_platform_data *pdata);
void __init dm365_init_vc(struct snd_platform_data *pdata);
void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
void __init dm365_init_rtc(void);
void dm365_init_spi0(unsigned chipselect_mask,
struct spi_board_info *info, unsigned len);
void dm365_set_vpfe_config(struct vpfe_config *cfg);
/* DM644x function declarations */
void __init dm644x_init(void);
void __init dm644x_init_asp(struct snd_platform_data *pdata);
int __init dm644x_init_video(struct vpfe_config *);
/* DM646x function declarations */
void __init dm646x_init(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
int __init dm646x_init_edma(struct edma_rsv_info *rsv);
void dm646x_video_init(void);
void dm646x_setup_vpif(struct vpif_display_config *,
struct vpif_capture_config *);
#endif /*__DAVINCI_H */
arch/arm/mach-davinci/devices.c
View file @ a3a3c466
......@@ -23,6 +23,7 @@
#include <mach/mmc.h>
#include <mach/time.h>
#include "davinci.h"
#include "clock.h"
#define DAVINCI_I2C_BASE 0x01C21000
......@@ -33,8 +34,19 @@
#define DM365_MMCSD0_BASE 0x01D11000
#define DM365_MMCSD1_BASE 0x01D00000
/* System control register offsets */
#define DM64XX_VDD3P3V_PWDN 0x48
void __iomem *davinci_sysmod_base;
void davinci_map_sysmod(void)
{
davinci_sysmod_base = ioremap_nocache(DAVINCI_SYSTEM_MODULE_BASE,
0x800);
/*
* Throw a bug since a lot of board initialization code depends
* on system module availability. ioremap() failing this early
* need careful looking into anyway.
*/
BUG_ON(!davinci_sysmod_base);
}
static struct resource i2c_resources[] = {
{
......@@ -212,12 +224,12 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
davinci_cfg_reg(DM355_SD1_DATA2);
davinci_cfg_reg(DM355_SD1_DATA3);
} else if (cpu_is_davinci_dm365()) {
void __iomem *pupdctl1 =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
/* Configure pull down control */
__raw_writel((__raw_readl(pupdctl1) & ~0xfc0),
pupdctl1);
unsigned v;
v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
__raw_writel(v & ~0xfc0,
DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
......@@ -246,11 +258,9 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
} else if (cpu_is_davinci_dm644x()) {
/* REVISIT: should this be in board-init code? */
void __iomem *base =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
/* Power-on 3.3V IO cells */
__raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
__raw_writel(0,
DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
/*Set up the pull regiter for MMC */
davinci_cfg_reg(DM644X_MSTK);
}
......
arch/arm/mach-davinci/dm355.c
View file @ a3a3c466
......@@ -18,7 +18,6 @@
#include <asm/mach/map.h>
#include <mach/dm355.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/psc.h>
......@@ -31,6 +30,7 @@
#include <mach/spi.h>
#include <mach/gpio-davinci.h>
#include "davinci.h"
#include "clock.h"
#include "mux.h"
......@@ -871,6 +871,7 @@ void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
void __init dm355_init(void)
{
davinci_common_init(&davinci_soc_info_dm355);
davinci_map_sysmod();
}
static int __init dm355_init_devices(void)
......
arch/arm/mach-davinci/dm365.c
View file @ a3a3c466
......@@ -21,7 +21,6 @@
#include <asm/mach/map.h>
#include <mach/dm365.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/psc.h>
......@@ -35,11 +34,28 @@
#include <mach/spi.h>
#include <mach/gpio-davinci.h>
#include "davinci.h"
#include "clock.h"
#include "mux.h"
#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
/* Base of key scan register bank */
#define DM365_KEYSCAN_BASE 0x01c69400
#define DM365_RTC_BASE 0x01c69000
#define DAVINCI_DM365_VC_BASE 0x01d0c000
#define DAVINCI_DMA_VC_TX 2
#define DAVINCI_DMA_VC_RX 3
#define DM365_EMAC_BASE 0x01d07000
#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
#define DM365_EMAC_CNTRL_OFFSET 0x0000
#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
static struct pll_data pll1_data = {
.num = 1,
.phys_base = DAVINCI_PLL1_BASE,
......@@ -1122,6 +1138,7 @@ void __init dm365_init_rtc(void)
void __init dm365_init(void)
{
davinci_common_init(&davinci_soc_info_dm365);
davinci_map_sysmod();
}
static struct resource dm365_vpss_resources[] = {
......
arch/arm/mach-davinci/dm644x.c
View file @ a3a3c466
......@@ -15,7 +15,6 @@
#include <asm/mach/map.h>
#include <mach/dm644x.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/irqs.h>
......@@ -27,6 +26,7 @@
#include <mach/asp.h>
#include <mach/gpio-davinci.h>
#include "davinci.h"
#include "clock.h"
#include "mux.h"
......@@ -35,6 +35,13 @@
*/
#define DM644X_REF_FREQ 27000000
#define DM644X_EMAC_BASE 0x01c80000
#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
#define DM644X_EMAC_CNTRL_OFFSET 0x0000
#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
static struct pll_data pll1_data = {
.num = 1,
.phys_base = DAVINCI_PLL1_BASE,
......@@ -587,13 +594,15 @@ static struct platform_device dm644x_asp_device = {
.resource = dm644x_asp_resources,
};
#define DM644X_VPSS_BASE 0x01c73400
static struct resource dm644x_vpss_resources[] = {
{
/* VPSS Base address */
.name = "vpss",
.start = 0x01c73400,
.end = 0x01c73400 + 0xff,
.flags = IORESOURCE_MEM,
.start = DM644X_VPSS_BASE,
.end = DM644X_VPSS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
};
......@@ -605,7 +614,7 @@ static struct platform_device dm644x_vpss_device = {
.resource = dm644x_vpss_resources,
};
static struct resource vpfe_resources[] = {
static struct resource dm644x_vpfe_resources[] = {
{
.start = IRQ_VDINT0,
.end = IRQ_VDINT0,
......@@ -639,22 +648,17 @@ static struct platform_device dm644x_ccdc_dev = {
},
};
static struct platform_device vpfe_capture_dev = {
static struct platform_device dm644x_vpfe_dev = {
.name = CAPTURE_DRV_NAME,
.id = -1,
.num_resources = ARRAY_SIZE(vpfe_resources),
.resource = vpfe_resources,
.num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
.resource = dm644x_vpfe_resources,
.dev = {
.dma_mask = &vpfe_capture_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
void dm644x_set_vpfe_config(struct vpfe_config *cfg)
{
vpfe_capture_dev.dev.platform_data = cfg;
}
/*----------------------------------------------------------------------*/
static struct map_desc dm644x_io_desc[] = {
......@@ -779,16 +783,29 @@ void __init dm644x_init_asp(struct snd_platform_data *pdata)
void __init dm644x_init(void)
{
davinci_common_init(&davinci_soc_info_dm644x);
davinci_map_sysmod();
}
static int __init dm644x_init_devices(void)
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg)
{
if (!cpu_is_davinci_dm644x())
return 0;
dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
/* Add ccdc clock aliases */
clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
platform_device_register(&dm644x_vpss_device);
platform_device_register(&dm644x_ccdc_dev);
platform_device_register(&dm644x_vpfe_dev);
return 0;
}
static int __init dm644x_init_devices(void)
{
if (!cpu_is_davinci_dm644x())
return 0;
platform_device_register(&dm644x_edma_device);
platform_device_register(&dm644x_mdio_device);
......@@ -796,10 +813,6 @@ static int __init dm644x_init_devices(void)
clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
NULL, &dm644x_emac_device.dev);
platform_device_register(&dm644x_vpss_device);
platform_device_register(&dm644x_ccdc_dev);
platform_device_register(&vpfe_capture_dev);
return 0;
}
postcore_initcall(dm644x_init_devices);
arch/arm/mach-davinci/dm646x.c
View file @ a3a3c466
......@@ -16,7 +16,6 @@
#include <asm/mach/map.h>
#include <mach/dm646x.h>
#include <mach/cputype.h>
#include <mach/edma.h>
#include <mach/irqs.h>
......@@ -28,12 +27,11 @@
#include <mach/asp.h>
#include <mach/gpio-davinci.h>
#include "davinci.h"
#include "clock.h"
#include "mux.h"
#define DAVINCI_VPIF_BASE (0x01C12000)
#define VDD3P3V_PWDN_OFFSET (0x48)
#define VSCLKDIS_OFFSET (0x6C)
#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
BIT_MASK(0))
......@@ -46,6 +44,13 @@
#define DM646X_REF_FREQ 27000000
#define DM646X_AUX_FREQ 24000000
#define DM646X_EMAC_BASE 0x01c80000
#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
#define DM646X_EMAC_CNTRL_OFFSET 0x0000
#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
static struct pll_data pll1_data = {
.num = 1,
.phys_base = DAVINCI_PLL1_BASE,
......@@ -873,15 +878,14 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
struct vpif_capture_config *capture_config)
{
unsigned int value;
void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
value = __raw_readl(base + VSCLKDIS_OFFSET);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
value &= ~VSCLKDIS_MASK;
__raw_writel(value, base + VSCLKDIS_OFFSET);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
value &= ~VDD3P3V_VID_MASK;
__raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
__raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
......@@ -905,6 +909,7 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv)
void __init dm646x_init(void)
{
davinci_common_init(&davinci_soc_info_dm646x);
davinci_map_sysmod();
}
static int __init dm646x_init_devices(void)
......
arch/arm/mach-davinci/include/mach/dm355.h deleted 100644 → 0
View file @ 96a3eab3
/*
* Chip specific defines for DM355 SoC
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_DM355_H
#define __ASM_ARCH_DM355_H
#include <mach/hardware.h>
#include <mach/asp.h>
#include <media/davinci/vpfe_capture.h>
#define DM355_ASYNC_EMIF_CONTROL_BASE 0x01E10000
#define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define ASP1_TX_EVT_EN 1
#define ASP1_RX_EVT_EN 2
struct spi_board_info;
void __init dm355_init(void);
void dm355_init_spi0(unsigned chipselect_mask,
struct spi_board_info *info, unsigned len);
void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
void dm355_set_vpfe_config(struct vpfe_config *cfg);
#endif /* __ASM_ARCH_DM355_H */
arch/arm/mach-davinci/include/mach/dm365.h
View file @ a3a3c466
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_DM365_H
#define __ASM_ARCH_DM665_H
#include <linux/platform_device.h>
#include <linux/davinci_emac.h>
#include <mach/hardware.h>
#include <mach/asp.h>
#include <mach/keyscan.h>
#include <media/davinci/vpfe_capture.h>
#define DM365_EMAC_BASE (0x01D07000)
#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
#define DM365_EMAC_CNTRL_OFFSET (0x0000)
#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
/* Base of key scan register bank */
#define DM365_KEYSCAN_BASE (0x01C69400)
#define DM365_RTC_BASE (0x01C69000)
#define DAVINCI_DM365_VC_BASE (0x01D0C000)
#define DAVINCI_DMA_VC_TX 2
#define DAVINCI_DMA_VC_RX 3
#define DM365_ASYNC_EMIF_CONTROL_BASE 0x01D10000
#define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
void __init dm365_init(void);
void __init dm365_init_asp(struct snd_platform_data *pdata);
void __init dm365_init_vc(struct snd_platform_data *pdata);
void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
void __init dm365_init_rtc(void);
void dm365_init_spi0(unsigned chipselect_mask,
struct spi_board_info *info, unsigned len);
void dm365_set_vpfe_config(struct vpfe_config *cfg);
#endif /* __ASM_ARCH_DM365_H */
/* empty, remove once unused */
arch/arm/mach-davinci/include/mach/dm644x.h deleted 100644 → 0
View file @ 96a3eab3
/*
* This file contains the processor specific definitions
* of the TI DM644x.
*
* Copyright (C) 2008 Texas Instruments.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __ASM_ARCH_DM644X_H
#define __ASM_ARCH_DM644X_H
#include <linux/davinci_emac.h>
#include <mach/hardware.h>
#include <mach/asp.h>
#include <media/davinci/vpfe_capture.h>
#define DM644X_EMAC_BASE (0x01C80000)
#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
#define DM644X_EMAC_CNTRL_OFFSET (0x0000)
#define DM644X_EMAC_CNTRL_MOD_OFFSET (0x1000)
#define DM644X_EMAC_CNTRL_RAM_OFFSET (0x2000)
#define DM644X_EMAC_CNTRL_RAM_SIZE (0x2000)
#define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01E00000
#define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
#define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
#define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
#define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
void __init dm644x_init(void);
void __init dm644x_init_asp(struct snd_platform_data *pdata);
void dm644x_set_vpfe_config(struct vpfe_config *cfg);
#endif /* __ASM_ARCH_DM644X_H */
arch/arm/mach-davinci/include/mach/dm646x.h
View file @ a3a3c466
/*
* Chip specific defines for DM646x SoC
*
* Author: Kevin Hilman, Deep Root Systems, LLC
*
* 2007 (c) Deep Root Systems, LLC. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASM_ARCH_DM646X_H
#define __ASM_ARCH_DM646X_H
#include <mach/hardware.h>
#include <mach/asp.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/davinci_emac.h>
#include <media/davinci/vpif_types.h>
#define DM646X_EMAC_BASE (0x01C80000)
#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
#define DM646X_EMAC_CNTRL_MOD_OFFSET (0x1000)
#define DM646X_EMAC_CNTRL_RAM_OFFSET (0x2000)
#define DM646X_EMAC_CNTRL_RAM_SIZE (0x2000)
#define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000
#define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
void __init dm646x_init(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
int __init dm646x_init_edma(struct edma_rsv_info *rsv);
void dm646x_video_init(void);
void dm646x_setup_vpif(struct vpif_display_config *,
struct vpif_capture_config *);
#endif /* __ASM_ARCH_DM646X_H */
/* empty, remove once unused */
arch/arm/mach-davinci/include/mach/hardware.h
View file @ a3a3c466
......@@ -19,8 +19,6 @@
* and the chip/board init code should then explicitly include
* <chipname>.h
*/
#define DAVINCI_SYSTEM_MODULE_BASE 0x01C40000
/*
* I/O mapping
*/
......
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