Commit a3ec2d38 authored by Johan Jonker's avatar Johan Jonker Committed by Heiko Stuebner

ARM: dts: rockchip: add #power-domain-cells to power domain nodes

Add #power-domain-cells to power domain nodes, because they
are required by power-domain.yaml
Signed-off-by: default avatarJohan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20210417112952.8516-5-jbx6244@gmail.comSigned-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 970cdc53
...@@ -780,6 +780,7 @@ power-domain@RK3066_PD_VIO { ...@@ -780,6 +780,7 @@ power-domain@RK3066_PD_VIO {
<&qos_cif1>, <&qos_cif1>,
<&qos_ipp>, <&qos_ipp>,
<&qos_rga>; <&qos_rga>;
#power-domain-cells = <0>;
}; };
power-domain@RK3066_PD_VIDEO { power-domain@RK3066_PD_VIDEO {
...@@ -789,12 +790,14 @@ power-domain@RK3066_PD_VIDEO { ...@@ -789,12 +790,14 @@ power-domain@RK3066_PD_VIDEO {
<&cru HCLK_VDPU>, <&cru HCLK_VDPU>,
<&cru HCLK_VEPU>; <&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>; pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
}; };
power-domain@RK3066_PD_GPU { power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>; reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>; clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>; pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
}; };
}; };
}; };
......
...@@ -719,6 +719,7 @@ power-domain@RK3188_PD_VIO { ...@@ -719,6 +719,7 @@ power-domain@RK3188_PD_VIO {
<&qos_cif0>, <&qos_cif0>,
<&qos_ipp>, <&qos_ipp>,
<&qos_rga>; <&qos_rga>;
#power-domain-cells = <0>;
}; };
power-domain@RK3188_PD_VIDEO { power-domain@RK3188_PD_VIDEO {
...@@ -728,12 +729,14 @@ power-domain@RK3188_PD_VIDEO { ...@@ -728,12 +729,14 @@ power-domain@RK3188_PD_VIDEO {
<&cru HCLK_VDPU>, <&cru HCLK_VDPU>,
<&cru HCLK_VEPU>; <&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>; pm_qos = <&qos_vpu>;
#power-domain-cells = <0>;
}; };
power-domain@RK3188_PD_GPU { power-domain@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>; reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>; clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>; pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
}; };
}; };
}; };
......
...@@ -801,6 +801,7 @@ power-domain@RK3288_PD_VIO { ...@@ -801,6 +801,7 @@ power-domain@RK3288_PD_VIO {
<&qos_vio2_rga_r>, <&qos_vio2_rga_r>,
<&qos_vio2_rga_w>, <&qos_vio2_rga_w>,
<&qos_vio1_isp_r>; <&qos_vio1_isp_r>;
#power-domain-cells = <0>;
}; };
/* /*
...@@ -814,6 +815,7 @@ power-domain@RK3288_PD_HEVC { ...@@ -814,6 +815,7 @@ power-domain@RK3288_PD_HEVC {
<&cru SCLK_HEVC_CORE>; <&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_hevc_r>, pm_qos = <&qos_hevc_r>,
<&qos_hevc_w>; <&qos_hevc_w>;
#power-domain-cells = <0>;
}; };
/* /*
...@@ -826,6 +828,7 @@ power-domain@RK3288_PD_VIDEO { ...@@ -826,6 +828,7 @@ power-domain@RK3288_PD_VIDEO {
clocks = <&cru ACLK_VCODEC>, clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>; <&cru HCLK_VCODEC>;
pm_qos = <&qos_video>; pm_qos = <&qos_video>;
#power-domain-cells = <0>;
}; };
/* /*
...@@ -837,6 +840,7 @@ power-domain@RK3288_PD_GPU { ...@@ -837,6 +840,7 @@ power-domain@RK3288_PD_GPU {
clocks = <&cru ACLK_GPU>; clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>, pm_qos = <&qos_gpu_r>,
<&qos_gpu_w>; <&qos_gpu_w>;
#power-domain-cells = <0>;
}; };
}; };
......
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