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Commit a499e40a authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
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ARM: dts: renesas: Move enable-method to CPU nodes 

According to Documentation/devicetree/bindings/arm/cpus.yaml, the
"enable-method" property should be a property of the individual CPU
nodes, and not of the parent "cpus" container node.
However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the
"cpus" node instead.

Secondary CPU bringup and CPU hot (un)plug work regardless, as
arm_dt_init_cpu_maps() falls back to looking in the "cpus" node.

The cpuidle code does not have such a fallback, so it does not detect
the enable-method.  Note that cpuidle does not support the
"renesas,apmu" enable-method yet, so for now this does not make any
difference.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be
parent ebc666f3
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Showing with 28 additions and 10 deletions
arch/arm/boot/dts/r8a7742.dtsi
View file @ a499e40a
...@@ -47,7 +47,6 @@ can_clk: can { ...@@ -47,7 +47,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -56,6 +55,7 @@ cpu0: cpu@0 { ...@@ -56,6 +55,7 @@ cpu0: cpu@0 {
clock-frequency = <1400000000>; clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU0>; power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
...@@ -77,6 +77,7 @@ cpu1: cpu@1 { ...@@ -77,6 +77,7 @@ cpu1: cpu@1 {
clock-frequency = <1400000000>; clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU1>; power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
...@@ -98,6 +99,7 @@ cpu2: cpu@2 { ...@@ -98,6 +99,7 @@ cpu2: cpu@2 {
clock-frequency = <1400000000>; clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU2>; power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
...@@ -119,6 +121,7 @@ cpu3: cpu@3 { ...@@ -119,6 +121,7 @@ cpu3: cpu@3 {
clock-frequency = <1400000000>; clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU3>; power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
......
arch/arm/boot/dts/r8a7743.dtsi
View file @ a499e40a
...@@ -49,7 +49,6 @@ can_clk: can { ...@@ -49,7 +49,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -59,6 +58,7 @@ cpu0: cpu@0 { ...@@ -59,6 +58,7 @@ cpu0: cpu@0 {
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU0>; power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */ /* kHz - uV - OPPs unknown yet */
...@@ -78,6 +78,7 @@ cpu1: cpu@1 { ...@@ -78,6 +78,7 @@ cpu1: cpu@1 {
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU1>; power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */ /* kHz - uV - OPPs unknown yet */
......
arch/arm/boot/dts/r8a7744.dtsi
View file @ a499e40a
...@@ -49,7 +49,6 @@ can_clk: can { ...@@ -49,7 +49,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -59,6 +58,7 @@ cpu0: cpu@0 { ...@@ -59,6 +58,7 @@ cpu0: cpu@0 {
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU0>; power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */ /* kHz - uV - OPPs unknown yet */
...@@ -78,6 +78,7 @@ cpu1: cpu@1 { ...@@ -78,6 +78,7 @@ cpu1: cpu@1 {
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>; clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU1>; power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */ /* kHz - uV - OPPs unknown yet */
......
arch/arm/boot/dts/r8a7745.dtsi
View file @ a499e40a
...@@ -64,7 +64,6 @@ can_clk: can { ...@@ -64,7 +64,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -73,6 +72,7 @@ cpu0: cpu@0 { ...@@ -73,6 +72,7 @@ cpu0: cpu@0 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
power-domains = <&sysc R8A7745_PD_CA7_CPU0>; power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
...@@ -83,6 +83,7 @@ cpu1: cpu@1 { ...@@ -83,6 +83,7 @@ cpu1: cpu@1 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
power-domains = <&sysc R8A7745_PD_CA7_CPU1>; power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
......
arch/arm/boot/dts/r8a77470.dtsi
View file @ a499e40a
...@@ -25,7 +25,6 @@ aliases { ...@@ -25,7 +25,6 @@ aliases {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -34,6 +33,7 @@ cpu0: cpu@0 { ...@@ -34,6 +33,7 @@ cpu0: cpu@0 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
power-domains = <&sysc R8A77470_PD_CA7_CPU0>; power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
...@@ -44,6 +44,7 @@ cpu1: cpu@1 { ...@@ -44,6 +44,7 @@ cpu1: cpu@1 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>; clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
power-domains = <&sysc R8A77470_PD_CA7_CPU1>; power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
......
arch/arm/boot/dts/r8a7790.dtsi
View file @ a499e40a
...@@ -69,7 +69,6 @@ can_clk: can { ...@@ -69,7 +69,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -78,6 +77,7 @@ cpu0: cpu@0 { ...@@ -78,6 +77,7 @@ cpu0: cpu@0 {
clock-frequency = <1300000000>; clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU0>; power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
...@@ -99,6 +99,7 @@ cpu1: cpu@1 { ...@@ -99,6 +99,7 @@ cpu1: cpu@1 {
clock-frequency = <1300000000>; clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU1>; power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
...@@ -120,6 +121,7 @@ cpu2: cpu@2 { ...@@ -120,6 +121,7 @@ cpu2: cpu@2 {
clock-frequency = <1300000000>; clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU2>; power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
...@@ -141,6 +143,7 @@ cpu3: cpu@3 { ...@@ -141,6 +143,7 @@ cpu3: cpu@3 {
clock-frequency = <1300000000>; clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU3>; power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>; capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
...@@ -162,6 +165,7 @@ cpu4: cpu@100 { ...@@ -162,6 +165,7 @@ cpu4: cpu@100 {
clock-frequency = <780000000>; clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU0>; power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>; capacity-dmips-mhz = <539>;
}; };
...@@ -173,6 +177,7 @@ cpu5: cpu@101 { ...@@ -173,6 +177,7 @@ cpu5: cpu@101 {
clock-frequency = <780000000>; clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU1>; power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>; capacity-dmips-mhz = <539>;
}; };
...@@ -184,6 +189,7 @@ cpu6: cpu@102 { ...@@ -184,6 +189,7 @@ cpu6: cpu@102 {
clock-frequency = <780000000>; clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU2>; power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>; capacity-dmips-mhz = <539>;
}; };
...@@ -195,6 +201,7 @@ cpu7: cpu@103 { ...@@ -195,6 +201,7 @@ cpu7: cpu@103 {
clock-frequency = <780000000>; clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU3>; power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>; capacity-dmips-mhz = <539>;
}; };
......
arch/arm/boot/dts/r8a7791.dtsi
View file @ a499e40a
...@@ -68,7 +68,6 @@ can_clk: can { ...@@ -68,7 +68,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -77,6 +76,7 @@ cpu0: cpu@0 { ...@@ -77,6 +76,7 @@ cpu0: cpu@0 {
clock-frequency = <1500000000>; clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU0>; power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
...@@ -97,6 +97,7 @@ cpu1: cpu@1 { ...@@ -97,6 +97,7 @@ cpu1: cpu@1 {
clock-frequency = <1500000000>; clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU1>; power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
......
arch/arm/boot/dts/r8a7792.dtsi
View file @ a499e40a
...@@ -45,7 +45,6 @@ can_clk: can { ...@@ -45,7 +45,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -54,6 +53,7 @@ cpu0: cpu@0 { ...@@ -54,6 +53,7 @@ cpu0: cpu@0 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>; power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
...@@ -64,6 +64,7 @@ cpu1: cpu@1 { ...@@ -64,6 +64,7 @@ cpu1: cpu@1 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU1>; power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>; next-level-cache = <&L2_CA15>;
}; };
......
arch/arm/boot/dts/r8a7793.dtsi
View file @ a499e40a
...@@ -60,7 +60,6 @@ can_clk: can { ...@@ -60,7 +60,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -69,6 +68,7 @@ cpu0: cpu@0 { ...@@ -69,6 +68,7 @@ cpu0: cpu@0 {
clock-frequency = <1500000000>; clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU0>; power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
...@@ -89,6 +89,7 @@ cpu1: cpu@1 { ...@@ -89,6 +89,7 @@ cpu1: cpu@1 {
clock-frequency = <1500000000>; clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU1>; power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */ voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */ clock-latency = <300000>; /* 300 us */
......
arch/arm/boot/dts/r8a7794.dtsi
View file @ a499e40a
...@@ -62,7 +62,6 @@ can_clk: can { ...@@ -62,7 +62,6 @@ can_clk: can {
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
enable-method = "renesas,apmu";
cpu0: cpu@0 { cpu0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
...@@ -71,6 +70,7 @@ cpu0: cpu@0 { ...@@ -71,6 +70,7 @@ cpu0: cpu@0 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
...@@ -81,6 +81,7 @@ cpu1: cpu@1 { ...@@ -81,6 +81,7 @@ cpu1: cpu@1 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU1>; power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>; next-level-cache = <&L2_CA7>;
}; };
......
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