Commit a4ab0d83 authored by Tony Lindgren's avatar Tony Lindgren

ARM: OMAP2/3: Remove OMAP2_32KSYNCT_BASE

Use processor specific defines instead.

As an extra bonus, this patch fixes the problem of CONFIG_DEBUG_SPINLOCK
calling sched_clock before we have things initialized:

http://patchwork.kernel.org/patch/15810/Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 59a3759d
...@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl: ...@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
prcm_mask_val: prcm_mask_val:
.word 0xFFFF3FFC .word 0xFFFF3FFC
omap242x_sdi_timer_32ksynct_cr: omap242x_sdi_timer_32ksynct_cr:
.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
ENTRY(omap242x_sram_ddr_init_sz) ENTRY(omap242x_sram_ddr_init_sz)
.word . - omap242x_sram_ddr_init .word . - omap242x_sram_ddr_init
...@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl: ...@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
ddr_prcm_mask_val: ddr_prcm_mask_val:
.word 0xFFFF3FFC .word 0xFFFF3FFC
omap242x_srs_timer_32ksynct: omap242x_srs_timer_32ksynct:
.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
ENTRY(omap242x_sram_reprogram_sdrc_sz) ENTRY(omap242x_sram_reprogram_sdrc_sz)
.word . - omap242x_sram_reprogram_sdrc .word . - omap242x_sram_reprogram_sdrc
......
...@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl: ...@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
prcm_mask_val: prcm_mask_val:
.word 0xFFFF3FFC .word 0xFFFF3FFC
omap243x_sdi_timer_32ksynct_cr: omap243x_sdi_timer_32ksynct_cr:
.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
ENTRY(omap243x_sram_ddr_init_sz) ENTRY(omap243x_sram_ddr_init_sz)
.word . - omap243x_sram_ddr_init .word . - omap243x_sram_ddr_init
...@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl: ...@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
ddr_prcm_mask_val: ddr_prcm_mask_val:
.word 0xFFFF3FFC .word 0xFFFF3FFC
omap243x_srs_timer_32ksynct: omap243x_srs_timer_32ksynct:
.word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
ENTRY(omap243x_sram_reprogram_sdrc_sz) ENTRY(omap243x_sram_reprogram_sdrc_sz)
.word . - omap243x_sram_reprogram_sdrc .word . - omap243x_sram_reprogram_sdrc
......
...@@ -175,25 +175,61 @@ console_initcall(omap_add_serial_console); ...@@ -175,25 +175,61 @@ console_initcall(omap_add_serial_console);
* but systems won't necessarily want to spend resources that way. * but systems won't necessarily want to spend resources that way.
*/ */
#if defined(CONFIG_ARCH_OMAP16XX) #define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
#define TIMER_32K_SYNCHRONIZED 0xfffbc410
#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10)
#endif
#ifdef TIMER_32K_SYNCHRONIZED #if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
#include <linux/clocksource.h> #include <linux/clocksource.h>
static cycle_t omap_32k_read(struct clocksource *cs) #ifdef CONFIG_ARCH_OMAP16XX
static cycle_t omap16xx_32k_read(struct clocksource *cs)
{
return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED);
}
#else
#define omap16xx_32k_read NULL
#endif
#ifdef CONFIG_ARCH_OMAP2420
static cycle_t omap2420_32k_read(struct clocksource *cs)
{
return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10);
}
#else
#define omap2420_32k_read NULL
#endif
#ifdef CONFIG_ARCH_OMAP2430
static cycle_t omap2430_32k_read(struct clocksource *cs)
{
return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10);
}
#else
#define omap2430_32k_read NULL
#endif
#ifdef CONFIG_ARCH_OMAP34XX
static cycle_t omap34xx_32k_read(struct clocksource *cs)
{ {
return omap_readl(TIMER_32K_SYNCHRONIZED); return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
}
#else
#define omap34xx_32k_read NULL
#endif
/*
* Kernel assumes that sched_clock can be called early but may not have
* things ready yet.
*/
static cycle_t omap_32k_read_dummy(struct clocksource *cs)
{
return 0;
} }
static struct clocksource clocksource_32k = { static struct clocksource clocksource_32k = {
.name = "32k_counter", .name = "32k_counter",
.rating = 250, .rating = 250,
.read = omap_32k_read, .read = omap_32k_read_dummy,
.mask = CLOCKSOURCE_MASK(32), .mask = CLOCKSOURCE_MASK(32),
.shift = 10, .shift = 10,
.flags = CLOCK_SOURCE_IS_CONTINUOUS, .flags = CLOCK_SOURCE_IS_CONTINUOUS,
...@@ -207,7 +243,7 @@ unsigned long long sched_clock(void) ...@@ -207,7 +243,7 @@ unsigned long long sched_clock(void)
{ {
unsigned long long ret; unsigned long long ret;
ret = (unsigned long long)omap_32k_read(&clocksource_32k); ret = (unsigned long long)clocksource_32k.read(&clocksource_32k);
ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift; ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
return ret; return ret;
} }
...@@ -220,6 +256,17 @@ static int __init omap_init_clocksource_32k(void) ...@@ -220,6 +256,17 @@ static int __init omap_init_clocksource_32k(void)
if (cpu_is_omap16xx() || cpu_class_is_omap2()) { if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
struct clk *sync_32k_ick; struct clk *sync_32k_ick;
if (cpu_is_omap16xx())
clocksource_32k.read = omap16xx_32k_read;
else if (cpu_is_omap2420())
clocksource_32k.read = omap2420_32k_read;
else if (cpu_is_omap2430())
clocksource_32k.read = omap2430_32k_read;
else if (cpu_is_omap34xx())
clocksource_32k.read = omap34xx_32k_read;
else
return -ENODEV;
sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
if (sync_32k_ick) if (sync_32k_ick)
clk_enable(sync_32k_ick); clk_enable(sync_32k_ick);
...@@ -234,7 +281,7 @@ static int __init omap_init_clocksource_32k(void) ...@@ -234,7 +281,7 @@ static int __init omap_init_clocksource_32k(void)
} }
arch_initcall(omap_init_clocksource_32k); arch_initcall(omap_init_clocksource_32k);
#endif /* TIMER_32K_SYNCHRONIZED */ #endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
/* Global address base setup code */ /* Global address base setup code */
......
...@@ -87,7 +87,6 @@ ...@@ -87,7 +87,6 @@
#if defined(CONFIG_ARCH_OMAP2420) #if defined(CONFIG_ARCH_OMAP2420)
#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE #define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
#define OMAP2_CM_BASE OMAP2420_CM_BASE #define OMAP2_CM_BASE OMAP2420_CM_BASE
#define OMAP2_PRM_BASE OMAP2420_PRM_BASE #define OMAP2_PRM_BASE OMAP2420_PRM_BASE
...@@ -95,7 +94,6 @@ ...@@ -95,7 +94,6 @@
#elif defined(CONFIG_ARCH_OMAP2430) #elif defined(CONFIG_ARCH_OMAP2430)
#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE #define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
#define OMAP2_CM_BASE OMAP2430_CM_BASE #define OMAP2_CM_BASE OMAP2430_CM_BASE
#define OMAP2_PRM_BASE OMAP2430_PRM_BASE #define OMAP2_PRM_BASE OMAP2430_PRM_BASE
......
...@@ -85,7 +85,6 @@ ...@@ -85,7 +85,6 @@
#if defined(CONFIG_ARCH_OMAP3430) #if defined(CONFIG_ARCH_OMAP3430)
#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
#define OMAP2_CM_BASE OMAP3430_CM_BASE #define OMAP2_CM_BASE OMAP3430_CM_BASE
#define OMAP2_PRM_BASE OMAP3430_PRM_BASE #define OMAP2_PRM_BASE OMAP3430_PRM_BASE
#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) #define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
......
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