Commit a5c6e87a authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Olof Johansson

arm: dts: socfpga: Change some clocks of gate-clk type to perip-clk

Some of the clocks that were designated gate-clk do not have a gate, so
change those clocks to be of periph-clk type.
Signed-off-by: default avatarDinh Nguyen <dinguyen@altera.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 725dd7eb
...@@ -245,14 +245,14 @@ h2f_usr2_clk: h2f_usr2_clk { ...@@ -245,14 +245,14 @@ h2f_usr2_clk: h2f_usr2_clk {
mpu_periph_clk: mpu_periph_clk { mpu_periph_clk: mpu_periph_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>; clocks = <&mpuclk>;
fixed-divider = <4>; fixed-divider = <4>;
}; };
mpu_l2_ram_clk: mpu_l2_ram_clk { mpu_l2_ram_clk: mpu_l2_ram_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>; clocks = <&mpuclk>;
fixed-divider = <2>; fixed-divider = <2>;
}; };
...@@ -266,8 +266,9 @@ l4_main_clk: l4_main_clk { ...@@ -266,8 +266,9 @@ l4_main_clk: l4_main_clk {
l3_main_clk: l3_main_clk { l3_main_clk: l3_main_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&mainclk>; clocks = <&mainclk>;
fixed-divider = <1>;
}; };
l3_mp_clk: l3_mp_clk { l3_mp_clk: l3_mp_clk {
......
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