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Commit a5e1d715 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC cleanups from Olof Johansson:
 "Again we have a sizable (but not huge) cleanup branch with a net delta
  of about -3k lines.

  Main contents here is:

   - A bunch of development/cleanup of a few PXA boards
   - Removal of bockw platforms on shmobile, since the platform has now
     gone completely multiplatform.  Whee!
   - move of the 32kHz timer on OMAP to a proper timesource
   - Misc cleanup of older OMAP material (incl removal of one board
     file)
   - Switch over to new common PWM lookup support for several platforms

  There's also a handful of other cleanups across the tree, but the
  above are the major pieces"

* tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (103 commits)
  ARM: OMAP3: hwmod data: Remove legacy mailbox data and addrs
  ARM: DRA7: hwmod data: Remove spinlock hwmod addrs
  ARM: OMAP4: hwmod data: Remove spinlock hwmod addrs
  ARM: DRA7/AM335x/AM437x: hwmod: Remove gpmc address space from hwmod data
  ARM: Remove __ref on hotplug cpu die path
  ARM: Remove open-coded version of IRQCHIP_DECLARE
  arm: omap2: board-generic: use omap4_local_timer_init for AM437x
  ARM: DRA7/AM335x/AM437x: hwmod: Remove elm address space from hwmod data
  ARM: OMAP: Remove duplicated operand in OR operation
  clocksource: ti-32k: make it depend on GENERIC_CLOCKSOURCE
  ARM: pxa: remove incorrect __init annotation on pxa27x_set_pwrmode
  ARM: pxa: raumfeld: make some variables static
  ARM: OMAP: Change all cpu_is_* occurences to soc_is_* for id.c
  ARM: OMAP2+: Rename cpu_is macros to soc_is
  arm: omap2: timer: limit hwmod usage to non-DT boots
  arm: omap2+: select 32k clocksource driver
  clocksource: add TI 32.768 Hz counter driver
  arm: omap2: timer: rename omap_sync32k_timer_init()
  arm: omap2: timer: always call clocksource_of_init() when DT
  arm: omap2: timer: move realtime_counter_init() around
  ...
parents 64fd8c8a d3dc3df6
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Showing with 1002 additions and 4433 deletions
Documentation/devicetree/bindings/arm/shmobile.txt
View file @ a5e1d715
......@@ -39,8 +39,6 @@ Boards:
compatible = "renesas,armadillo800eva"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- BOCK-W - Reference Device Tree Implementation
compatible = "renesas,bockw-reference", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)
compatible = "renesas,genmai", "renesas,r7s72100"
- Gose
......@@ -57,7 +55,3 @@ Boards:
compatible = "renesas,lager", "renesas,r8a7790"
- Marzen
compatible = "renesas,marzen", "renesas,r8a7779"
Note: Reference Device Tree Implementations are temporary implementations
to ease the migration from platform devices to Device Tree, and are
intended to be removed in the future.
Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt
View file @ a5e1d715
......@@ -24,9 +24,9 @@ Required properties:
Optional properties:
- interrupts: Must contain a list of interrupt specifiers for memory
controller interrupts, if available.
- interrupts-names: Must contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
Valid interrupt names are:
- interrupt-names: Must contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
Valid interrupt names are:
- "sec" (secure interrupt)
- "temp" (normal (temperature) interrupt)
- power-domains: Must contain a reference to the PM domain that the memory
......
Documentation/spi/pxa2xx
View file @ a5e1d715
......@@ -22,15 +22,10 @@ Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
found in include/linux/spi/pxa2xx_spi.h:
struct pxa2xx_spi_master {
u32 clock_enable;
u16 num_chipselect;
u8 enable_dma;
};
The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the
corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See
the "PXA2xx Developer Manual" section "Clocks and Power Management".
The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of
slave device (chips) attached to this SPI master.
......@@ -57,7 +52,6 @@ static struct resource pxa_spi_nssp_resources[] = {
};
static struct pxa2xx_spi_master pxa_nssp_master_info = {
.clock_enable = CKEN_NSSP, /* NSSP Peripheral clock */
.num_chipselect = 1, /* Matches the number of chips attached to NSSP */
.enable_dma = 1, /* Enables NSSP DMA */
};
......
MAINTAINERS
View file @ a5e1d715
......@@ -1516,8 +1516,6 @@ F: arch/arm/boot/dts/emev2*
F: arch/arm/boot/dts/r7s*
F: arch/arm/boot/dts/r8a*
F: arch/arm/boot/dts/sh*
F: arch/arm/configs/bockw_defconfig
F: arch/arm/configs/marzen_defconfig
F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
F: arch/arm/mach-shmobile/
......
arch/arm/Kconfig
View file @ a5e1d715
......@@ -621,28 +621,6 @@ config ARCH_PXA
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
config ARCH_SHMOBILE_LEGACY
bool "Renesas ARM SoCs (non-multiplatform)"
select ARCH_SHMOBILE
select ARM_PATCH_PHYS_VIRT if MMU
select CLKDEV_LOOKUP
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
select MULTI_IRQ_HANDLER
select NO_IOPORT_MAP
select PINCTRL
select PM_GENERIC_DOMAINS if PM
select SH_CLK_CPG
select SPARSE_IRQ
help
Support for Renesas ARM SoC platforms using a non-multiplatform
kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
and RZ families.
config ARCH_RPC
bool "RiscPC"
depends on MMU
......@@ -1537,7 +1515,6 @@ config HZ_FIXED
default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
ARCH_S5PV210 || ARCH_EXYNOS4
default 128 if SOC_AT91RM9200
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
default 0
choice
......@@ -1756,8 +1733,7 @@ config ARM_MODULE_PLTS
source "mm/Kconfig"
config FORCE_MAX_ZONEORDER
int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
range 11 64 if ARCH_SHMOBILE_LEGACY
int "Maximum zone order"
default "12" if SOC_AM33XX
default "9" if SA1111 || ARCH_EFM32
default "11"
......
arch/arm/Kconfig.debug
View file @ a5e1d715
......@@ -1621,8 +1621,7 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
PLAT_SAMSUNG || ARM_SINGLE_ARMV7M || \
ARCH_SHMOBILE_LEGACY
PLAT_SAMSUNG || ARM_SINGLE_ARMV7M
default "mach/uncompress.h"
config EARLY_PRINTK
......
arch/arm/boot/dts/Makefile
View file @ a5e1d715
......@@ -522,9 +522,6 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-smdkc110.dtb \
s5pv210-smdkv210.dtb \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
r8a7778-bockw.dtb \
r8a7778-bockw-reference.dtb
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
......
arch/arm/boot/dts/efm32gg-dk3750.dts
View file @ a5e1d715
......@@ -26,7 +26,7 @@ adc@40002000 {
};
i2c@4000a000 {
efm32,location = <3>;
energymicro,location = <3>;
status = "ok";
temp@48 {
......@@ -43,7 +43,7 @@ eeprom@50 {
spi0: spi@4000c000 { /* USART0 */
cs-gpios = <&gpio 68 1>; // E4
location = <1>;
energymicro,location = <1>;
status = "ok";
microsd@0 {
......@@ -57,7 +57,7 @@ microsd@0 {
spi1: spi@4000c400 { /* USART1 */
cs-gpios = <&gpio 51 1>; // D3
location = <1>;
energymicro,location = <1>;
status = "ok";
ks8851@0 {
......@@ -70,7 +70,7 @@ ks8851@0 {
};
uart4: uart@4000e400 { /* UART1 */
location = <2>;
energymicro,location = <2>;
status = "ok";
};
......
arch/arm/boot/dts/efm32gg.dtsi
View file @ a5e1d715
......@@ -23,7 +23,7 @@ aliases {
soc {
adc: adc@40002000 {
compatible = "efm32,adc";
compatible = "energymicro,efm32-adc";
reg = <0x40002000 0x400>;
interrupts = <7>;
clocks = <&cmu clk_HFPERCLKADC0>;
......@@ -31,7 +31,7 @@ adc: adc@40002000 {
};
gpio: gpio@40006000 {
compatible = "efm32,gpio";
compatible = "energymicro,efm32-gpio";
reg = <0x40006000 0x1000>;
interrupts = <1 11>;
gpio-controller;
......@@ -45,7 +45,7 @@ gpio: gpio@40006000 {
i2c0: i2c@4000a000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,i2c";
compatible = "energymicro,efm32-i2c";
reg = <0x4000a000 0x400>;
interrupts = <9>;
clocks = <&cmu clk_HFPERCLKI2C0>;
......@@ -56,7 +56,7 @@ i2c0: i2c@4000a000 {
i2c1: i2c@4000a400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,i2c";
compatible = "energymicro,efm32-i2c";
reg = <0x4000a400 0x400>;
interrupts = <10>;
clocks = <&cmu clk_HFPERCLKI2C1>;
......@@ -67,7 +67,7 @@ i2c1: i2c@4000a400 {
spi0: spi@4000c000 { /* USART0 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,spi";
compatible = "energymicro,efm32-spi";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
......@@ -77,7 +77,7 @@ spi0: spi@4000c000 { /* USART0 */
spi1: spi@4000c400 { /* USART1 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,spi";
compatible = "energymicro,efm32-spi";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
......@@ -87,7 +87,7 @@ spi1: spi@4000c400 { /* USART1 */
spi2: spi@4000c800 { /* USART2 */
#address-cells = <1>;
#size-cells = <0>;
compatible = "efm32,spi";
compatible = "energymicro,efm32-spi";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
......@@ -95,7 +95,7 @@ spi2: spi@4000c800 { /* USART2 */
};
uart0: uart@4000c000 { /* USART0 */
compatible = "efm32,uart";
compatible = "energymicro,efm32-uart";
reg = <0x4000c000 0x400>;
interrupts = <3 4>;
clocks = <&cmu clk_HFPERCLKUSART0>;
......@@ -103,7 +103,7 @@ uart0: uart@4000c000 { /* USART0 */
};
uart1: uart@4000c400 { /* USART1 */
compatible = "efm32,uart";
compatible = "energymicro,efm32-uart";
reg = <0x4000c400 0x400>;
interrupts = <15 16>;
clocks = <&cmu clk_HFPERCLKUSART1>;
......@@ -111,7 +111,7 @@ uart1: uart@4000c400 { /* USART1 */
};
uart2: uart@4000c800 { /* USART2 */
compatible = "efm32,uart";
compatible = "energymicro,efm32-uart";
reg = <0x4000c800 0x400>;
interrupts = <18 19>;
clocks = <&cmu clk_HFPERCLKUSART2>;
......@@ -119,7 +119,7 @@ uart2: uart@4000c800 { /* USART2 */
};
uart3: uart@4000e000 { /* UART0 */
compatible = "efm32,uart";
compatible = "energymicro,efm32-uart";
reg = <0x4000e000 0x400>;
interrupts = <20 21>;
clocks = <&cmu clk_HFPERCLKUART0>;
......@@ -127,7 +127,7 @@ uart3: uart@4000e000 { /* UART0 */
};
uart4: uart@4000e400 { /* UART1 */
compatible = "efm32,uart";
compatible = "energymicro,efm32-uart";
reg = <0x4000e400 0x400>;
interrupts = <22 23>;
clocks = <&cmu clk_HFPERCLKUART1>;
......@@ -135,28 +135,28 @@ uart4: uart@4000e400 { /* UART1 */
};
timer0: timer@40010000 {
compatible = "efm32,timer";
compatible = "energymicro,efm32-timer";
reg = <0x40010000 0x400>;
interrupts = <2>;
clocks = <&cmu clk_HFPERCLKTIMER0>;
};
timer1: timer@40010400 {
compatible = "efm32,timer";
compatible = "energymicro,efm32-timer";
reg = <0x40010400 0x400>;
interrupts = <12>;
clocks = <&cmu clk_HFPERCLKTIMER1>;
};
timer2: timer@40010800 {
compatible = "efm32,timer";
compatible = "energymicro,efm32-timer";
reg = <0x40010800 0x400>;
interrupts = <13>;
clocks = <&cmu clk_HFPERCLKTIMER2>;
};
timer3: timer@40010c00 {
compatible = "efm32,timer";
compatible = "energymicro,efm32-timer";
reg = <0x40010c00 0x400>;
interrupts = <14>;
clocks = <&cmu clk_HFPERCLKTIMER3>;
......
arch/arm/boot/dts/r8a7778-bockw-reference.dts deleted 100644 → 0
View file @ 64fd8c8a
/*
* Reference Device Tree Source for the Bock-W board
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* based on r8a7779
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7778.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "bockw";
compatible = "renesas,bockw-reference", "renesas,r8a7778";
aliases {
serial0 = &scif0;
};
chosen {
bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw";
stdout-path = &scif0;
};
memory {
device_type = "memory";
reg = <0x60000000 0x10000000>;
};
fixedregulator3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ethernet@18300000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x18300000 0x1000>;
phy-mode = "mii";
interrupt-parent = <&irqpin>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
reg-io-width = <4>;
vddvario-supply = <&fixedregulator3v3>;
vdd33a-supply = <&fixedregulator3v3>;
};
};
&mmcif {
pinctrl-0 = <&mmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>;
bus-width = <8>;
broken-cd;
status = "okay";
};
&irqpin {
status = "okay";
};
&tmu0 {
status = "okay";
};
&pfc {
scif0_pins: serial0 {
renesas,groups = "scif0_data_a", "scif0_ctrl";
renesas,function = "scif0";
};
mmc_pins: mmc {
renesas,groups = "mmc_data8", "mmc_ctrl";
renesas,function = "mmc";
};
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
"sdhi0_cd";
renesas,function = "sdhi0";
};
hspi0_pins: hspi0 {
renesas,groups = "hspi0_a";
renesas,function = "hspi0";
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&fixedregulator3v3>;
bus-width = <4>;
status = "okay";
wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
};
&hspi0 {
pinctrl-0 = <&hspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl008k", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
m25p,fast-read;
partition@0 {
label = "data(spi)";
reg = <0x00000000 0x00100000>;
};
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm/configs/bockw_defconfig deleted 100644 → 0
View file @ 64fd8c8a
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
CONFIG_KERNEL_LZMA=y
CONFIG_NO_HZ=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=16
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SHMOBILE_LEGACY=y
CONFIG_ARCH_R8A7778=y
CONFIG_MACH_BOCKW=y
CONFIG_MEMORY_START=0x60000000
CONFIG_MEMORY_SIZE=0x10000000
CONFIG_SHMOBILE_TIMER_HZ=1024
# CONFIG_SH_TIMER_CMT is not set
# CONFIG_EM_TIMER_STI is not set
CONFIG_ARM_ERRATA_430973=y
CONFIG_ARM_ERRATA_458693=y
CONFIG_ARM_ERRATA_460075=y
CONFIG_ARM_ERRATA_743622=y
CONFIG_ARM_ERRATA_754322=y
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_HIGHMEM=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_ARM_APPENDED_DTB=y
CONFIG_VFP=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SPI_NOR=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_CIRRUS is not set
# CONFIG_NET_VENDOR_FARADAY is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_SEEQ is not set
CONFIG_SMSC911X=y
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=6
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_I2C=y
CONFIG_I2C_RCAR=y
CONFIG_GPIO_RCAR=y
CONFIG_REGULATOR=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CAMERA_SUPPORT=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_SOC_CAMERA=y
CONFIG_VIDEO_RCAR_VIN=y
# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
CONFIG_VIDEO_ML86V7667=y
CONFIG_SPI=y
CONFIG_SPI_SH_HSPI=y
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_RCAR=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_RCAR_PHY=y
CONFIG_MMC=y
CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_RX8581=y
CONFIG_DMADEVICES=y
CONFIG_RCAR_HPB_DMAE=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
# CONFIG_IOMMU_SUPPORT is not set
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFS_SWAP=y
CONFIG_NFS_V4_1=y
CONFIG_ROOT_NFS=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_FTRACE is not set
# CONFIG_ARM_UNWIND is not set
CONFIG_AVERAGE=y
arch/arm/kernel/psci_smp.c
View file @ a5e1d715
......@@ -71,7 +71,7 @@ int psci_cpu_disable(unsigned int cpu)
return 0;
}
void __ref psci_cpu_die(unsigned int cpu)
void psci_cpu_die(unsigned int cpu)
{
u32 state = PSCI_POWER_STATE_TYPE_POWER_DOWN <<
PSCI_0_2_POWER_STATE_TYPE_SHIFT;
......@@ -83,7 +83,7 @@ void __ref psci_cpu_die(unsigned int cpu)
panic("psci: cpu %d failed to shutdown\n", cpu);
}
int __ref psci_cpu_kill(unsigned int cpu)
int psci_cpu_kill(unsigned int cpu)
{
int err, i;
......
arch/arm/mach-exynos/suspend.c
View file @ a5e1d715
......@@ -19,6 +19,7 @@
#include <linux/cpu_pm.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/err.h>
......@@ -265,7 +266,7 @@ static int __init exynos_pmu_irq_init(struct device_node *node,
return 0;
}
#define EXYNOS_PMU_IRQ(symbol, name) OF_DECLARE_2(irqchip, symbol, name, exynos_pmu_irq_init)
#define EXYNOS_PMU_IRQ(symbol, name) IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
......
arch/arm/mach-imx/gpc.c
View file @ a5e1d715
......@@ -14,6 +14,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
......@@ -271,12 +272,7 @@ static int __init imx_gpc_init(struct device_node *node,
return 0;
}
/*
* We cannot use the IRQCHIP_DECLARE macro that lives in
* drivers/irqchip, so we're forced to roll our own. Not very nice.
*/
OF_DECLARE_2(irqchip, imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
IRQCHIP_DECLARE(imx_gpc, "fsl,imx6q-gpc", imx_gpc_init);
void __init imx_gpc_check_dt(void)
{
......
arch/arm/mach-mvebu/board-v7.c
View file @ a5e1d715
......@@ -22,7 +22,6 @@
#include <linux/dma-mapping.h>
#include <linux/memblock.h>
#include <linux/mbus.h>
#include <linux/signal.h>
#include <linux/slab.h>
#include <linux/irqchip.h>
#include <asm/hardware/cache-l2x0.h>
......@@ -105,27 +104,6 @@ static void __init mvebu_memblock_reserve(void)
static void __init mvebu_memblock_reserve(void) {}
#endif
/*
* Early versions of Armada 375 SoC have a bug where the BootROM
* leaves an external data abort pending. The kernel is hit by this
* data abort as soon as it enters userspace, because it unmasks the
* data aborts at this moment. We register a custom abort handler
* below to ignore the first data abort to work around this
* problem.
*/
static int armada_375_external_abort_wa(unsigned long addr, unsigned int fsr,
struct pt_regs *regs)
{
static int ignore_first;
if (!ignore_first && fsr == 0x1406) {
ignore_first = 1;
return 0;
}
return 1;
}
static void __init mvebu_init_irq(void)
{
irqchip_init();
......@@ -134,17 +112,6 @@ static void __init mvebu_init_irq(void)
BUG_ON(mvebu_mbus_dt_init(coherency_available()));
}
static void __init external_abort_quirk(void)
{
u32 dev, rev;
if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
return;
hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
"imprecise external abort");
}
static void __init i2c_quirk(void)
{
struct device_node *np;
......@@ -177,8 +144,6 @@ static void __init mvebu_dt_init(void)
{
if (of_machine_is_compatible("marvell,armadaxp"))
i2c_quirk();
if (of_machine_is_compatible("marvell,a375-db"))
external_abort_quirk();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
......
arch/arm/mach-mvebu/pmsu.c
View file @ a5e1d715
......@@ -296,11 +296,11 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
/* Test the CR_C bit and set it if it was cleared */
asm volatile(
"mrc p15, 0, r0, c1, c0, 0 \n\t"
"tst r0, #(1 << 2) \n\t"
"tst r0, %0 \n\t"
"orreq r0, r0, #(1 << 2) \n\t"
"mcreq p15, 0, r0, c1, c0, 0 \n\t"
"isb "
: : : "r0");
: : "Ir" (CR_C) : "r0");
pr_debug("Failed to suspend the system\n");
......
arch/arm/mach-omap1/Kconfig
View file @ a5e1d715
......@@ -90,13 +90,6 @@ config MACH_OMAP_FSAMPLE
Support for TI OMAP 850 F-Sample board. Say Y here if you have such
a board.
config MACH_VOICEBLUE
bool "Voiceblue"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
help
Support for Voiceblue GSM/VoIP gateway. Say Y here if you have
such a board.
config MACH_OMAP_PALMTE
bool "Palm Tungsten E"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
......
arch/arm/mach-omap1/Makefile
View file @ a5e1d715
......@@ -37,7 +37,6 @@ obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o
obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \
board-nand.o
obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
......
arch/arm/mach-omap1/board-voiceblue.c deleted 100644 → 0
View file @ 64fd8c8a
/*
* linux/arch/arm/mach-omap1/board-voiceblue.c
*
* Modified from board-generic.c
*
* Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
*
* Code for OMAP5910 based VoiceBlue board (VoIP to GSM gateway).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mtd/physmap.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/smc91x.h>
#include <linux/export.h>
#include <linux/reboot.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/board-voiceblue.h>
#include <mach/flash.h>
#include <mach/mux.h>
#include <mach/tc.h>
#include <mach/hardware.h>
#include <mach/usb.h>
#include "common.h"
static struct plat_serial8250_port voiceblue_ports[] = {
{
.mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x40000),
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 1,
.uartclk = 3686400,
},
{
.mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x50000),
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 1,
.uartclk = 3686400,
},
{
.mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x60000),
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 1,
.uartclk = 3686400,
},
{
.mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x70000),
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
.iotype = UPIO_MEM,
.regshift = 1,
.uartclk = 3686400,
},
{ },
};
static struct platform_device serial_device = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
};
static int __init ext_uart_init(void)
{
if (!machine_is_voiceblue())
return -ENODEV;
voiceblue_ports[0].irq = gpio_to_irq(12);
voiceblue_ports[1].irq = gpio_to_irq(13);
voiceblue_ports[2].irq = gpio_to_irq(14);
voiceblue_ports[3].irq = gpio_to_irq(15);
serial_device.dev.platform_data = voiceblue_ports;
return platform_device_register(&serial_device);
}
arch_initcall(ext_uart_init);
static struct physmap_flash_data voiceblue_flash_data = {
.width = 2,
.set_vpp = omap1_set_vpp,
};
static struct resource voiceblue_flash_resource = {
.start = OMAP_CS0_PHYS,
.end = OMAP_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device voiceblue_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &voiceblue_flash_data,
},
.num_resources = 1,
.resource = &voiceblue_flash_resource,
};
static struct smc91x_platdata voiceblue_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource voiceblue_smc91x_resources[] = {
[0] = {
.start = OMAP_CS2_PHYS + 0x300,
.end = OMAP_CS2_PHYS + 0x300 + 16,
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
},
};
static struct platform_device voiceblue_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &voiceblue_smc91x_info,
},
.num_resources = ARRAY_SIZE(voiceblue_smc91x_resources),
.resource = voiceblue_smc91x_resources,
};
static struct platform_device *voiceblue_devices[] __initdata = {
&voiceblue_flash_device,
&voiceblue_smc91x_device,
};
static struct omap_usb_config voiceblue_usb_config __initdata = {
.hmc_mode = 3,
.register_host = 1,
.register_dev = 1,
.pins[0] = 2,
.pins[1] = 6,
.pins[2] = 6,
};
#define MACHINE_PANICED 1
#define MACHINE_REBOOTING 2
#define MACHINE_REBOOT 4
static unsigned long machine_state;
static int panic_event(struct notifier_block *this, unsigned long event,
void *ptr)
{
if (test_and_set_bit(MACHINE_PANICED, &machine_state))
return NOTIFY_DONE;
/* Flash power LED */
omap_writeb(0x78, OMAP_LPG1_LCR);
omap_writeb(0x01, OMAP_LPG1_PMR); /* Enable clock */
return NOTIFY_DONE;
}
static struct notifier_block panic_block = {
.notifier_call = panic_event,
};
static int __init voiceblue_setup(void)
{
if (!machine_is_voiceblue())
return -ENODEV;
/* Setup panic notifier */
atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
return 0;
}
postcore_initcall(voiceblue_setup);
static int wdt_gpio_state;
void voiceblue_wdt_enable(void)
{
gpio_direction_output(0, 0);
gpio_set_value(0, 1);
gpio_set_value(0, 0);
wdt_gpio_state = 0;
}
void voiceblue_wdt_disable(void)
{
gpio_set_value(0, 0);
gpio_set_value(0, 1);
gpio_set_value(0, 0);
gpio_direction_input(0);
}
void voiceblue_wdt_ping(void)
{
if (test_bit(MACHINE_REBOOT, &machine_state))
return;
wdt_gpio_state = !wdt_gpio_state;
gpio_set_value(0, wdt_gpio_state);
}
static void voiceblue_restart(enum reboot_mode mode, const char *cmd)
{
/*
* Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
* "Global Software Reset Affects Traffic Controller Frequency".
*/
if (cpu_is_omap5912()) {
omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL);
omap_writew(0x8, ARM_RSTCT1);
}
set_bit(MACHINE_REBOOT, &machine_state);
voiceblue_wdt_enable();
while (1) ;
}
EXPORT_SYMBOL(voiceblue_wdt_enable);
EXPORT_SYMBOL(voiceblue_wdt_disable);
EXPORT_SYMBOL(voiceblue_wdt_ping);
static void __init voiceblue_init(void)
{
/* mux pins for uarts */
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
omap_cfg_reg(UART2_TX);
omap_cfg_reg(UART2_RTS);
omap_cfg_reg(UART3_TX);
omap_cfg_reg(UART3_RX);
/* Watchdog */
gpio_request(0, "Watchdog");
/* smc91x reset */
gpio_request(7, "SMC91x reset");
gpio_direction_output(7, 1);
udelay(2); /* wait at least 100ns */
gpio_set_value(7, 0);
mdelay(50); /* 50ms until PHY ready */
/* smc91x interrupt pin */
gpio_request(8, "SMC91x irq");
/* 16C554 reset*/
gpio_request(6, "16C554 reset");
gpio_direction_output(6, 0);
/* 16C554 interrupt pins */
gpio_request(12, "16C554 irq");
gpio_request(13, "16C554 irq");
gpio_request(14, "16C554 irq");
gpio_request(15, "16C554 irq");
irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
voiceblue_smc91x_resources[1].start = gpio_to_irq(8);
voiceblue_smc91x_resources[1].end = gpio_to_irq(8);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_serial_init();
omap1_usb_init(&voiceblue_usb_config);
omap_register_i2c_bus(1, 100, NULL, 0);
/* There is a good chance board is going up, so enable power LED
* (it is connected through invertor) */
omap_writeb(0x00, OMAP_LPG1_LCR);
omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
}
MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
/* Maintainer: Ladislav Michl <michl@2n.cz> */
.atag_offset = 0x100,
.map_io = omap15xx_map_io,
.init_early = omap1_init_early,
.init_irq = omap1_init_irq,
.handle_irq = omap1_handle_irq,
.init_machine = voiceblue_init,
.init_late = omap1_init_late,
.init_time = omap1_timer_init,
.restart = voiceblue_restart,
MACHINE_END
arch/arm/mach-omap1/include/mach/board-voiceblue.h deleted 100644 → 0
View file @ 64fd8c8a
/*
* Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
*
* Hardware definitions for OMAP5910 based VoiceBlue board.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_VOICEBLUE_H
#define __ASM_ARCH_VOICEBLUE_H
extern void voiceblue_wdt_enable(void);
extern void voiceblue_wdt_disable(void);
extern void voiceblue_wdt_ping(void);
#endif /* __ASM_ARCH_VOICEBLUE_H */
arch/arm/mach-omap2/Kconfig
View file @ a5e1d715
......@@ -97,6 +97,7 @@ config ARCH_OMAP2PLUS
select PINCTRL
select SOC_BUS
select OMAP_IRQCHIP
select CLKSRC_TI_32K
help
Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
......
arch/arm/mach-omap2/Makefile
View file @ a5e1d715
......@@ -48,11 +48,9 @@ AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
# Functions loaded to SRAM
obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
AFLAGS_sram242x.o :=-Wa,-march=armv6
AFLAGS_sram243x.o :=-Wa,-march=armv6
AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
# Restart code (OMAP4/5 currently in omap4-common.c)
obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
......@@ -186,7 +184,6 @@ obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o
obj-$(CONFIG_ARCH_OMAP3) += $(clock-common)
obj-$(CONFIG_ARCH_OMAP3) += clkt34xx_dpll3m2.o
obj-$(CONFIG_ARCH_OMAP4) += $(clock-common)
obj-$(CONFIG_SOC_AM33XX) += $(clock-common)
obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
......
arch/arm/mach-omap2/board-generic.c
View file @ a5e1d715
......@@ -46,7 +46,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
.map_io = omap242x_map_io,
.init_early = omap2420_init_early,
.init_machine = omap_generic_init,
.init_time = omap2_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap242x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
......@@ -63,7 +63,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
.map_io = omap243x_map_io,
.init_early = omap2430_init_early,
.init_machine = omap_generic_init,
.init_time = omap2_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap243x_boards_compat,
.restart = omap2xxx_restart,
MACHINE_END
......@@ -82,7 +82,7 @@ DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = n900_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
......@@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.init_early = omap3430_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap3_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
......@@ -117,7 +117,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
.init_early = omap3630_init_early,
.init_machine = omap_generic_init,
.init_late = omap3_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.dt_compat = omap36xx_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
......@@ -276,7 +276,7 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
.init_late = am43xx_init_late,
.init_irq = omap_gic_of_init,
.init_machine = omap_generic_init,
.init_time = omap3_gptimer_timer_init,
.init_time = omap4_local_timer_init,
.dt_compat = am43_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
......
arch/arm/mach-omap2/board-ldp.c
View file @ a5e1d715
......@@ -424,6 +424,6 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
.init_irq = omap3_init_irq,
.init_machine = omap_ldp_init,
.init_late = omap3430_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.restart = omap3xxx_restart,
MACHINE_END
arch/arm/mach-omap2/board-rx51.c
View file @ a5e1d715
......@@ -136,6 +136,6 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
.init_irq = omap3_init_irq,
.init_machine = rx51_init,
.init_late = omap3430_init_late,
.init_time = omap3_sync32k_timer_init,
.init_time = omap_init_time,
.restart = omap3xxx_restart,
MACHINE_END
arch/arm/mach-omap2/clkt34xx_dpll3m2.c deleted 100644 → 0
View file @ 64fd8c8a
/*
* OMAP34xx M2 divider clock code
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation
*
* Paul Walmsley
* Jouni Högander
*
* Parts of this code are based on code written by
* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#undef DEBUG
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/clk.h>
#include <linux/io.h>
#include "clock.h"
#include "clock3xxx.h"
#include "sdrc.h"
#include "sram.h"
#define CYCLES_PER_MHZ 1000000
struct clk *sdrc_ick_p, *arm_fck_p;
/*
* CORE DPLL (DPLL3) M2 divider rate programming functions
*
* These call into SRAM code to do the actual CM writes, since the SDRAM
* is clocked from DPLL3.
*/
/**
* omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
* @clk: struct clk * of DPLL to set
* @rate: rounded target rate
*
* Program the DPLL M2 divider with the rounded target rate. Returns
* -EINVAL upon error, or 0 upon success.
*/
int omap3_core_dpll_m2_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
u32 new_div = 0;
u32 unlock_dll = 0;
u32 c;
unsigned long validrate, sdrcrate, _mpurate;
struct omap_sdrc_params *sdrc_cs0;
struct omap_sdrc_params *sdrc_cs1;
int ret;
unsigned long clkrate;
if (!clk || !rate)
return -EINVAL;
new_div = DIV_ROUND_UP(parent_rate, rate);
validrate = parent_rate / new_div;
if (validrate != rate)
return -EINVAL;
sdrcrate = clk_get_rate(sdrc_ick_p);
clkrate = clk_hw_get_rate(hw);
if (rate > clkrate)
sdrcrate <<= ((rate / clkrate) >> 1);
else
sdrcrate >>= ((clkrate / rate) >> 1);
ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
if (ret)
return -EINVAL;
if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
pr_debug("clock: will unlock SDRC DLL\n");
unlock_dll = 1;
}
/*
* XXX This only needs to be done when the CPU frequency changes
*/
_mpurate = clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
c += 1; /* for safety */
c *= SDRC_MPURATE_LOOPS;
c >>= SDRC_MPURATE_SCALE;
if (c == 0)
c = 1;
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
clkrate, validrate);
pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
if (sdrc_cs1)
pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
if (sdrc_cs1)
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
else
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clkrate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);
return 0;
}
arch/arm/mach-omap2/common.h
View file @ a5e1d715
......@@ -88,8 +88,7 @@ static inline int omap_mux_late_init(void)
extern void omap2_init_common_infrastructure(void);
extern void omap2_sync32k_timer_init(void);
extern void omap3_sync32k_timer_init(void);
extern void omap_init_time(void);
extern void omap3_secure_sync32k_timer_init(void);
extern void omap3_gptimer_timer_init(void);
extern void omap4_local_timer_init(void);
......
arch/arm/mach-omap2/devices.c
View file @ a5e1d715
......@@ -33,7 +33,6 @@
#include "common.h"
#include "mux.h"
#include "control.h"
#include "devices.h"
#include "display.h"
#define L3_MODULES_MAX_LEN 12
......@@ -67,58 +66,6 @@ static int __init omap3_l3_init(void)
}
omap_postcore_initcall(omap3_l3_init);
#if defined(CONFIG_IOMMU_API)
#include <linux/platform_data/iommu-omap.h>
static struct resource omap3isp_resources[] = {
{
.start = OMAP3430_ISP_BASE,
.end = OMAP3430_ISP_BASE + 0x12fc,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP3430_ISP_BASE2,
.end = OMAP3430_ISP_BASE2 + 0x0600,
.flags = IORESOURCE_MEM,
},
{
.start = 24 + OMAP_INTC_START,
.flags = IORESOURCE_IRQ,
}
};
static struct platform_device omap3isp_device = {
.name = "omap3isp",
.id = -1,
.num_resources = ARRAY_SIZE(omap3isp_resources),
.resource = omap3isp_resources,
};
static struct omap_iommu_arch_data omap3_isp_iommu = {
.name = "mmu_isp",
};
int omap3_init_camera(struct isp_platform_data *pdata)
{
if (of_have_populated_dt())
omap3_isp_iommu.name = "480bd400.mmu";
omap3isp_device.dev.platform_data = pdata;
omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu;
return platform_device_register(&omap3isp_device);
}
#else /* !CONFIG_IOMMU_API */
int omap3_init_camera(struct isp_platform_data *pdata)
{
return 0;
}
#endif
#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
static inline void __init omap_init_mbox(void)
{
......
arch/arm/mach-omap2/devices.h deleted 100644 → 0
View file @ 64fd8c8a
/*
* arch/arm/mach-omap2/devices.h
*
* OMAP2 platform device setup/initialization
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __ARCH_ARM_MACH_OMAP_DEVICES_H
#define __ARCH_ARM_MACH_OMAP_DEVICES_H
struct isp_platform_data;
int omap3_init_camera(struct isp_platform_data *pdata);
#endif
arch/arm/mach-omap2/id.c
View file @ a5e1d715
......@@ -57,15 +57,15 @@ int omap_type(void)
if (val < OMAP2_DEVICETYPE_MASK)
return val;
if (cpu_is_omap24xx()) {
if (soc_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
} else if (cpu_is_ti81xx()) {
} else if (soc_is_ti81xx()) {
val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
} else if (soc_is_am33xx() || soc_is_am43xx()) {
val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
} else if (cpu_is_omap34xx()) {
} else if (soc_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
} else if (soc_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
......@@ -122,7 +122,7 @@ static u16 tap_prod_id;
void omap_get_die_id(struct omap_die_id *odi)
{
if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
......@@ -218,17 +218,17 @@ static void __init omap3_cpuinfo(void)
* on available features. Upon detection, update the CPU id
* and CPU class bits.
*/
if (cpu_is_omap3630()) {
if (soc_is_omap3630()) {
cpu_name = "OMAP3630";
} else if (soc_is_am35xx()) {
cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
} else if (cpu_is_ti816x()) {
} else if (soc_is_ti816x()) {
cpu_name = "TI816X";
} else if (soc_is_am335x()) {
cpu_name = "AM335X";
} else if (soc_is_am437x()) {
cpu_name = "AM437x";
} else if (cpu_is_ti814x()) {
} else if (soc_is_ti814x()) {
cpu_name = "TI814X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
......@@ -275,11 +275,11 @@ void __init omap3xxx_check_features(void)
OMAP3_CHECK_FEATURE(status, SGX);
OMAP3_CHECK_FEATURE(status, NEON);
OMAP3_CHECK_FEATURE(status, ISP);
if (cpu_is_omap3630())
if (soc_is_omap3630())
omap_features |= OMAP3_HAS_192MHZ_CLK;
if (cpu_is_omap3430() || cpu_is_omap3630())
if (soc_is_omap3430() || soc_is_omap3630())
omap_features |= OMAP3_HAS_IO_WAKEUP;
if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
omap_rev() == OMAP3430_REV_ES3_1_2)
omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
......@@ -701,7 +701,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
tap_base = tap;
/* XXX What is this intended to do? */
if (cpu_is_omap34xx())
if (soc_is_omap34xx())
tap_prod_id = 0x0210;
else
tap_prod_id = 0x0208;
......@@ -719,11 +719,11 @@ static const char * const omap_types[] = {
static const char * __init omap_get_family(void)
{
if (cpu_is_omap24xx())
if (soc_is_omap24xx())
return kasprintf(GFP_KERNEL, "OMAP2");
else if (cpu_is_omap34xx())
else if (soc_is_omap34xx())
return kasprintf(GFP_KERNEL, "OMAP3");
else if (cpu_is_omap44xx())
else if (soc_is_omap44xx())
return kasprintf(GFP_KERNEL, "OMAP4");
else if (soc_is_omap54xx())
return kasprintf(GFP_KERNEL, "OMAP5");
......
arch/arm/mach-omap2/omap-hotplug.c
View file @ a5e1d715
......@@ -27,7 +27,7 @@
* platform-specific code to shutdown a CPU
* Called with IRQs disabled
*/
void __ref omap4_cpu_die(unsigned int cpu)
void omap4_cpu_die(unsigned int cpu)
{
unsigned int boot_cpu = 0;
void __iomem *base = omap_get_wakeupgen_base();
......
arch/arm/mach-omap2/omap-wakeupgen.c
View file @ a5e1d715
......@@ -20,6 +20,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
......@@ -330,7 +331,7 @@ static int irq_cpu_hotplug_notify(struct notifier_block *self,
return NOTIFY_OK;
}
static struct notifier_block __refdata irq_hotplug_notifier = {
static struct notifier_block irq_hotplug_notifier = {
.notifier_call = irq_cpu_hotplug_notify,
};
......@@ -540,9 +541,4 @@ static int __init wakeupgen_init(struct device_node *node,
return 0;
}
/*
* We cannot use the IRQCHIP_DECLARE macro that lives in
* drivers/irqchip, so we're forced to roll our own. Not very nice.
*/
OF_DECLARE_2(irqchip, ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c
View file @ a5e1d715
......@@ -152,20 +152,10 @@ struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
{
.pa_start = 0x48080000,
.pa_end = 0x48080000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
.master = &am33xx_l4_ls_hwmod,
.slave = &am33xx_elm_hwmod,
.clk = "l4ls_gclk",
.addr = am33xx_elm_addr_space,
.user = OCP_USER_MPU,
};
......@@ -285,20 +275,10 @@ struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
};
/* l3s cfg -> gpmc */
static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
{
.pa_start = 0x50000000,
.pa_end = 0x50000000 + SZ_8K - 1,
.flags = ADDR_TYPE_RT,
},
{ }
};
struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
.master = &am33xx_l3_s_hwmod,
.slave = &am33xx_gpmc_hwmod,
.clk = "l3s_gclk",
.addr = am33xx_gpmc_addr_space,
.user = OCP_USER_MPU,
};
......
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View file @ a5e1d715
......@@ -26,7 +26,6 @@
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/iommu-omap.h>
#include <linux/platform_data/mailbox-omap.h>
#include <plat/dmtimer.h>
#include "soc.h"
......@@ -1506,26 +1505,9 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
.sysc = &omap3xxx_mailbox_sysc,
};
static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
{ .name = "dsp", .tx_id = 0, .rx_id = 1 },
};
static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
.num_users = 2,
.num_fifos = 2,
.info_cnt = ARRAY_SIZE(omap3xxx_mailbox_info),
.info = omap3xxx_mailbox_info,
};
static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
{ .irq = 26 + OMAP_INTC_START, },
{ .irq = -1 },
};
static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap3xxx_mailbox_hwmod_class,
.mpu_irqs = omap3xxx_mailbox_irqs,
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
......@@ -1536,7 +1518,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
},
},
.dev_attr = &omap3xxx_mailbox_attrs,
};
/*
......@@ -3276,20 +3257,10 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
.user = OCP_USER_MPU,
};
static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
{
.pa_start = 0x48094000,
.pa_end = 0x480941ff,
.flags = ADDR_TYPE_RT,
},
{ }
};
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mailbox_hwmod,
.addr = omap3xxx_mailbox_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View file @ a5e1d715
......@@ -4471,21 +4471,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
{
.pa_start = 0x4a0f6000,
.pa_end = 0x4a0f6fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> spinlock */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_spinlock_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_spinlock_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
View file @ a5e1d715
......@@ -1844,8 +1844,7 @@ static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_RESET_STATUS),
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
......
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View file @ a5e1d715
......@@ -2566,21 +2566,11 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
{
.pa_start = 0x48078000,
.pa_end = 0x48078fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_per1 -> elm */
static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
.master = &dra7xx_l4_per1_hwmod,
.slave = &dra7xx_elm_hwmod,
.clk = "l3_iclk_div",
.addr = dra7xx_elm_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -2648,21 +2638,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
{
.pa_start = 0x50000000,
.pa_end = 0x500003ff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l3_main_1 -> gpmc */
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
.master = &dra7xx_l3_main_1_hwmod,
.slave = &dra7xx_gpmc_hwmod,
.clk = "l3_iclk_div",
.addr = dra7xx_gpmc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......@@ -3029,21 +3009,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
{
.pa_start = 0x4a0f6000,
.pa_end = 0x4a0f6fff,
.flags = ADDR_TYPE_RT
},
{ }
};
/* l4_cfg -> spinlock */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
.master = &dra7xx_l4_cfg_hwmod,
.slave = &dra7xx_spinlock_hwmod,
.clk = "l3_iclk_div",
.addr = dra7xx_spinlock_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
......
arch/arm/mach-omap2/pm44xx.c
View file @ a5e1d715
......@@ -210,7 +210,7 @@ static inline int omap4plus_init_static_deps(const struct static_dep_map *map)
}
map++;
};
}
return 0;
}
......
arch/arm/mach-omap2/powerdomains3xxx_data.c
View file @ a5e1d715
......@@ -582,7 +582,7 @@ void __init omap3xxx_powerdomains_init(void)
/* Only 81xx needs custom pwrdm_operations */
if (!cpu_is_ti81xx())
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);;
pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
rev = omap_rev();
......
arch/arm/mach-omap2/soc.h
View file @ a5e1d715
......@@ -129,9 +129,9 @@ int omap_type(void);
/*
* omap_rev bits:
* CPU id bits (0730, 1510, 1710, 2422...) [31:16]
* CPU revision (See _REV_ defined in cpu.h) [15:08]
* CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
* SoC id bits (0730, 1510, 1710, 2422...) [31:16]
* SoC revision (See _REV_ defined in cpu.h) [15:08]
* SoC class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
*/
unsigned int omap_rev(void);
......@@ -141,20 +141,20 @@ static inline int soc_is_omap(void)
}
/*
* Get the CPU revision for OMAP devices
* Get the SoC revision for OMAP devices
*/
#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
/*
* Macros to group OMAP into cpu classes.
* These can be used in most places.
* cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
* cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
* cpu_is_omap243x(): True for OMAP2430
* cpu_is_omap343x(): True for OMAP3430
* cpu_is_omap443x(): True for OMAP4430
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
* soc_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
* soc_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
* soc_is_omap243x(): True for OMAP2430
* soc_is_omap343x(): True for OMAP3430
* soc_is_omap443x(): True for OMAP4430
* soc_is_omap446x(): True for OMAP4460
* soc_is_omap447x(): True for OMAP4470
* soc_is_omap543x(): True for OMAP5430, OMAP5432
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
......@@ -225,23 +225,23 @@ IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
IS_AM_SUBCLASS(437x, 0x437)
#define cpu_is_omap24xx() 0
#define cpu_is_omap242x() 0
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
#define cpu_is_ti81xx() 0
#define cpu_is_ti816x() 0
#define cpu_is_ti814x() 0
#define soc_is_omap24xx() 0
#define soc_is_omap242x() 0
#define soc_is_omap243x() 0
#define soc_is_omap34xx() 0
#define soc_is_omap343x() 0
#define soc_is_ti81xx() 0
#define soc_is_ti816x() 0
#define soc_is_ti814x() 0
#define soc_is_am35xx() 0
#define soc_is_am33xx() 0
#define soc_is_am335x() 0
#define soc_is_am43xx() 0
#define soc_is_am437x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
#define cpu_is_omap446x() 0
#define cpu_is_omap447x() 0
#define soc_is_omap44xx() 0
#define soc_is_omap443x() 0
#define soc_is_omap446x() 0
#define soc_is_omap447x() 0
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
#define soc_is_dra7xx() 0
......@@ -250,54 +250,54 @@ IS_AM_SUBCLASS(437x, 0x437)
#if defined(MULTI_OMAP2)
# if defined(CONFIG_ARCH_OMAP2)
# undef cpu_is_omap24xx
# define cpu_is_omap24xx() is_omap24xx()
# undef soc_is_omap24xx
# define soc_is_omap24xx() is_omap24xx()
# endif
# if defined (CONFIG_SOC_OMAP2420)
# undef cpu_is_omap242x
# define cpu_is_omap242x() is_omap242x()
# undef soc_is_omap242x
# define soc_is_omap242x() is_omap242x()
# endif
# if defined (CONFIG_SOC_OMAP2430)
# undef cpu_is_omap243x
# define cpu_is_omap243x() is_omap243x()
# undef soc_is_omap243x
# define soc_is_omap243x() is_omap243x()
# endif
# if defined(CONFIG_ARCH_OMAP3)
# undef cpu_is_omap34xx
# undef cpu_is_omap343x
# define cpu_is_omap34xx() is_omap34xx()
# define cpu_is_omap343x() is_omap343x()
# undef soc_is_omap34xx
# undef soc_is_omap343x
# define soc_is_omap34xx() is_omap34xx()
# define soc_is_omap343x() is_omap343x()
# endif
#else
# if defined(CONFIG_ARCH_OMAP2)
# undef cpu_is_omap24xx
# define cpu_is_omap24xx() 1
# undef soc_is_omap24xx
# define soc_is_omap24xx() 1
# endif
# if defined(CONFIG_SOC_OMAP2420)
# undef cpu_is_omap242x
# define cpu_is_omap242x() 1
# undef soc_is_omap242x
# define soc_is_omap242x() 1
# endif
# if defined(CONFIG_SOC_OMAP2430)
# undef cpu_is_omap243x
# define cpu_is_omap243x() 1
# undef soc_is_omap243x
# define soc_is_omap243x() 1
# endif
# if defined(CONFIG_ARCH_OMAP3)
# undef cpu_is_omap34xx
# define cpu_is_omap34xx() 1
# undef soc_is_omap34xx
# define soc_is_omap34xx() 1
# endif
# if defined(CONFIG_SOC_OMAP3430)
# undef cpu_is_omap343x
# define cpu_is_omap343x() 1
# undef soc_is_omap343x
# define soc_is_omap343x() 1
# endif
#endif
/*
* Macros to detect individual cpu types.
* These are only rarely needed.
* cpu_is_omap2420(): True for OMAP2420
* cpu_is_omap2422(): True for OMAP2422
* cpu_is_omap2423(): True for OMAP2423
* cpu_is_omap2430(): True for OMAP2430
* cpu_is_omap3430(): True for OMAP3430
* soc_is_omap2420(): True for OMAP2420
* soc_is_omap2422(): True for OMAP2422
* soc_is_omap2423(): True for OMAP2423
* soc_is_omap2430(): True for OMAP2430
* soc_is_omap3430(): True for OMAP3430
*/
#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
......@@ -313,51 +313,51 @@ IS_OMAP_TYPE(2423, 0x2423)
IS_OMAP_TYPE(2430, 0x2430)
IS_OMAP_TYPE(3430, 0x3430)
#define cpu_is_omap2420() 0
#define cpu_is_omap2422() 0
#define cpu_is_omap2423() 0
#define cpu_is_omap2430() 0
#define cpu_is_omap3430() 0
#define cpu_is_omap3630() 0
#define soc_is_omap2420() 0
#define soc_is_omap2422() 0
#define soc_is_omap2423() 0
#define soc_is_omap2430() 0
#define soc_is_omap3430() 0
#define soc_is_omap3630() 0
#define soc_is_omap5430() 0
/* These are needed for the common code */
#ifdef CONFIG_ARCH_OMAP2PLUS
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
#define cpu_is_omap16xx() 0
#define cpu_is_omap1510() 0
#define cpu_is_omap1610() 0
#define cpu_is_omap1611() 0
#define cpu_is_omap1621() 0
#define cpu_is_omap1710() 0
#define soc_is_omap7xx() 0
#define soc_is_omap15xx() 0
#define soc_is_omap16xx() 0
#define soc_is_omap1510() 0
#define soc_is_omap1610() 0
#define soc_is_omap1611() 0
#define soc_is_omap1621() 0
#define soc_is_omap1710() 0
#define cpu_class_is_omap1() 0
#define cpu_class_is_omap2() 1
#endif
#if defined(CONFIG_ARCH_OMAP2)
# undef cpu_is_omap2420
# undef cpu_is_omap2422
# undef cpu_is_omap2423
# undef cpu_is_omap2430
# define cpu_is_omap2420() is_omap2420()
# define cpu_is_omap2422() is_omap2422()
# define cpu_is_omap2423() is_omap2423()
# define cpu_is_omap2430() is_omap2430()
# undef soc_is_omap2420
# undef soc_is_omap2422
# undef soc_is_omap2423
# undef soc_is_omap2430
# define soc_is_omap2420() is_omap2420()
# define soc_is_omap2422() is_omap2422()
# define soc_is_omap2423() is_omap2423()
# define soc_is_omap2430() is_omap2430()
#endif
#if defined(CONFIG_ARCH_OMAP3)
# undef cpu_is_omap3430
# undef cpu_is_ti81xx
# undef cpu_is_ti816x
# undef cpu_is_ti814x
# undef soc_is_omap3430
# undef soc_is_ti81xx
# undef soc_is_ti816x
# undef soc_is_ti814x
# undef soc_is_am35xx
# define cpu_is_omap3430() is_omap3430()
# undef cpu_is_omap3630
# define cpu_is_omap3630() is_omap363x()
# define cpu_is_ti81xx() is_ti81xx()
# define cpu_is_ti816x() is_ti816x()
# define cpu_is_ti814x() is_ti814x()
# define soc_is_omap3430() is_omap3430()
# undef soc_is_omap3630
# define soc_is_omap3630() is_omap363x()
# define soc_is_ti81xx() is_ti81xx()
# define soc_is_ti816x() is_ti816x()
# define soc_is_ti814x() is_ti814x()
# define soc_is_am35xx() is_am35xx()
#endif
......@@ -376,14 +376,14 @@ IS_OMAP_TYPE(3430, 0x3430)
#endif
# if defined(CONFIG_ARCH_OMAP4)
# undef cpu_is_omap44xx
# undef cpu_is_omap443x
# undef cpu_is_omap446x
# undef cpu_is_omap447x
# define cpu_is_omap44xx() is_omap44xx()
# define cpu_is_omap443x() is_omap443x()
# define cpu_is_omap446x() is_omap446x()
# define cpu_is_omap447x() is_omap447x()
# undef soc_is_omap44xx
# undef soc_is_omap443x
# undef soc_is_omap446x
# undef soc_is_omap447x
# define soc_is_omap44xx() is_omap44xx()
# define soc_is_omap443x() is_omap443x()
# define soc_is_omap446x() is_omap446x()
# define soc_is_omap447x() is_omap447x()
# endif
# if defined(CONFIG_SOC_OMAP5)
......@@ -556,5 +556,22 @@ level(__##fn);
#define omap_late_initcall(fn) omap_initcall(late_initcall, fn)
#define omap_late_initcall_sync(fn) omap_initcall(late_initcall_sync, fn)
#endif /* __ASSEMBLY__ */
/* Legacy defines, these can be removed when users are removed */
#define cpu_is_omap2420() soc_is_omap2420()
#define cpu_is_omap2422() soc_is_omap2422()
#define cpu_is_omap242x() soc_is_omap242x()
#define cpu_is_omap2430() soc_is_omap2430()
#define cpu_is_omap243x() soc_is_omap243x()
#define cpu_is_omap24xx() soc_is_omap24xx()
#define cpu_is_omap3430() soc_is_omap3430()
#define cpu_is_omap343x() soc_is_omap343x()
#define cpu_is_omap34xx() soc_is_omap34xx()
#define cpu_is_omap3630() soc_is_omap3630()
#define cpu_is_omap443x() soc_is_omap443x()
#define cpu_is_omap446x() soc_is_omap446x()
#define cpu_is_omap44xx() soc_is_omap44xx()
#define cpu_is_ti814x() soc_is_ti814x()
#define cpu_is_ti816x() soc_is_ti816x()
#define cpu_is_ti81xx() soc_is_ti81xx()
#endif /* __ASSEMBLY__ */
arch/arm/mach-omap2/sram.c
View file @ a5e1d715
......@@ -211,35 +211,10 @@ static inline int omap243x_sram_init(void)
#ifdef CONFIG_ARCH_OMAP3
static u32 (*_omap3_sram_configure_core_dpll)(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
{
BUG_ON(!_omap3_sram_configure_core_dpll);
return _omap3_sram_configure_core_dpll(
m2, unlock_dll, f, inc,
sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
sdrc_actim_ctrl_b_0, sdrc_mr_0,
sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
sdrc_actim_ctrl_b_1, sdrc_mr_1);
}
void omap3_sram_restore_context(void)
{
omap_sram_reset();
_omap3_sram_configure_core_dpll =
omap_sram_push(omap3_sram_configure_core_dpll,
omap3_sram_configure_core_dpll_sz);
omap_push_sram_idle();
}
......
arch/arm/mach-omap2/sram.h
View file @ a5e1d715
......@@ -15,12 +15,6 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
extern void omap3_sram_restore_context(void);
/* Do not use these */
......@@ -52,14 +46,6 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#ifdef CONFIG_PM
extern void omap_push_sram_idle(void);
#else
......
arch/arm/mach-omap2/sram34xx.S deleted 100644 → 0
View file @ 64fd8c8a
This diff is collapsed.
arch/arm/mach-omap2/timer.c
View file @ a5e1d715
......@@ -183,7 +183,8 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *
of_get_property(np, "ti,timer-secure", NULL)))
continue;
of_add_property(np, &device_disabled);
if (!of_device_is_compatible(np, "ti,omap-counter32k"))
of_add_property(np, &device_disabled);
return np;
}
......@@ -394,7 +395,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
int ret;
struct device_node *np = NULL;
struct omap_hwmod *oh;
void __iomem *vbase;
const char *oh_name = "counter_32k";
/*
......@@ -420,18 +420,6 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
omap_hwmod_setup_one(oh_name);
if (np) {
vbase = of_iomap(np, 0);
of_node_put(np);
} else {
vbase = omap_hwmod_get_mpu_rt_va(oh);
}
if (!vbase) {
pr_warn("%s: failed to get counter_32k resource\n", __func__);
return -ENXIO;
}
ret = omap_hwmod_enable(oh);
if (ret) {
pr_warn("%s: failed to enable counter_32k module (%d)\n",
......@@ -439,13 +427,18 @@ static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
return ret;
}
ret = omap_init_clocksource_32k(vbase);
if (ret) {
pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
__func__, ret);
omap_hwmod_idle(oh);
}
if (!of_have_populated_dt()) {
void __iomem *vbase;
vbase = omap_hwmod_get_mpu_rt_va(oh);
ret = omap_init_clocksource_32k(vbase);
if (ret) {
pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
__func__, ret);
omap_hwmod_idle(oh);
}
}
return ret;
}
......@@ -476,7 +469,64 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
clocksource_gpt.name, clksrc.rate);
}
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
const char *clksrc_prop, bool gptimer)
{
omap_clk_init();
omap_dmtimer_init();
omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
/* Enable the use of clocksource="gp_timer" kernel parameter */
if (use_gptimer_clksrc || gptimer)
omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
clksrc_prop);
else
omap2_sync32k_clocksource_init();
}
void __init omap_init_time(void)
{
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL, false);
if (of_have_populated_dt())
clocksource_probe();
}
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
void __init omap3_secure_sync32k_timer_init(void)
{
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
2, "timer_sys_ck", NULL, false);
}
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
void __init omap3_gptimer_timer_init(void)
{
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon", true);
}
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
static void __init omap4_sync32k_timer_init(void)
{
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "sys_clkin_ck", NULL, false);
}
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
clocksource_probe();
}
#endif
#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
/*
* The realtime counter also called master counter, is a free-running
* counter, which is related to real time. It produces the count used
......@@ -488,6 +538,7 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
*/
static void __init realtime_counter_init(void)
{
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void __iomem *base;
static struct clk *sys_clk;
unsigned long rate;
......@@ -586,78 +637,9 @@ static void __init realtime_counter_init(void)
set_cntfreq();
iounmap(base);
}
#else
static inline void __init realtime_counter_init(void)
{}
#endif
#define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
clksrc_nr, clksrc_src, clksrc_prop) \
void __init omap##name##_gptimer_timer_init(void) \
{ \
omap_clk_init(); \
omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
clksrc_prop); \
}
#define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
clksrc_nr, clksrc_src, clksrc_prop) \
void __init omap##name##_sync32k_timer_init(void) \
{ \
omap_clk_init(); \
omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
/* Enable the use of clocksource="gp_timer" kernel parameter */ \
if (use_gptimer_clksrc) \
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
clksrc_prop); \
else \
omap2_sync32k_clocksource_init(); \
}
#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL);
#endif /* CONFIG_ARCH_OMAP2 */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL);
OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
2, "timer_sys_ck", NULL);
#endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
defined(CONFIG_SOC_AM43XX)
OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon");
#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX)
static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
2, "sys_clkin_ck", NULL);
#endif
#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_HAVE_ARM_TWD
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
clocksource_probe();
}
#else
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
}
#endif /* CONFIG_HAVE_ARM_TWD */
#endif /* CONFIG_ARCH_OMAP4 */
#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
void __init omap5_realtime_timer_init(void)
{
omap4_sync32k_timer_init();
......
arch/arm/mach-omap2/vc.c
View file @ a5e1d715
......@@ -280,10 +280,6 @@ void omap3_vc_set_pmic_signaling(int core_next_state)
}
}
#define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \
OMAP3430_PRM_POLCTRL_CLKREQ_POL)
#define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL
/*
* Configure signal polarity for sys_clkreq and sys_off_mode pins
* as the default values are wrong and can cause the system to hang
......
arch/arm/mach-prima2/hotplug.c
View file @ a5e1d715
......@@ -32,7 +32,7 @@ static inline void platform_do_lowpower(unsigned int cpu)
*
* Called with IRQs disabled
*/
void __ref sirfsoc_cpu_die(unsigned int cpu)
void sirfsoc_cpu_die(unsigned int cpu)
{
platform_do_lowpower(cpu);
}
arch/arm/mach-pxa/cm-x300.c
View file @ a5e1d715
......@@ -26,6 +26,7 @@
#include <linux/dm9000.h>
#include <linux/leds.h>
#include <linux/rtc-v3020.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/i2c.h>
......@@ -305,11 +306,14 @@ static inline void cm_x300_init_lcd(void) {}
#endif
#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
static struct pwm_lookup cm_x300_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 1, "pwm-backlight.0", NULL, 10000,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data cm_x300_backlight_data = {
.pwm_id = 2,
.max_brightness = 100,
.dft_brightness = 100,
.pwm_period_ns = 10000,
.enable_gpio = -1,
};
......@@ -323,6 +327,7 @@ static struct platform_device cm_x300_backlight_device = {
static void cm_x300_init_bl(void)
{
pwm_add_table(cm_x300_pwm_lookup, ARRAY_SIZE(cm_x300_pwm_lookup));
platform_device_register(&cm_x300_backlight_device);
}
#else
......
arch/arm/mach-pxa/colibri-pxa270-income.c
View file @ a5e1d715
......@@ -20,6 +20,7 @@
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/i2c/pxa-i2c.h>
......@@ -184,11 +185,14 @@ static inline void income_lcd_init(void) {}
* Backlight
******************************************************************************/
#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
static struct pwm_lookup income_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 1000000,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data income_backlight_data = {
.pwm_id = 0,
.max_brightness = 0x3ff,
.dft_brightness = 0x1ff,
.pwm_period_ns = 1000000,
.enable_gpio = -1,
};
......@@ -202,6 +206,7 @@ static struct platform_device income_backlight = {
static void __init income_pwm_init(void)
{
pwm_add_table(income_pwm_lookup, ARRAY_SIZE(income_pwm_lookup));
platform_device_register(&income_backlight);
}
#else
......
arch/arm/mach-pxa/devices.c
View file @ a5e1d715
......@@ -395,6 +395,26 @@ static struct resource pxa_ir_resources[] = {
.end = IRQ_ICP,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = 0x40800000,
.end = 0x4080001b,
.flags = IORESOURCE_MEM,
},
[4] = {
.start = 0x40700000,
.end = 0x40700023,
.flags = IORESOURCE_MEM,
},
[5] = {
.start = 17,
.end = 17,
.flags = IORESOURCE_DMA,
},
[6] = {
.start = 18,
.end = 18,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa_device_ficp = {
......
arch/arm/mach-pxa/ezx.c
View file @ a5e1d715
......@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/input.h>
#include <linux/gpio.h>
......@@ -49,11 +50,14 @@
#define GPIO19_GEN1_CAM_RST 19
#define GPIO28_GEN2_CAM_RST 28
static struct pwm_lookup ezx_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78700,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data ezx_backlight_data = {
.pwm_id = 0,
.max_brightness = 1023,
.dft_brightness = 1023,
.pwm_period_ns = 78770,
.enable_gpio = -1,
};
......@@ -817,6 +821,7 @@ static void __init a780_init(void)
platform_device_register(&a780_camera);
}
pwm_add_table(ezx_pwm_lookup, ARRAY_SIZE(ezx_pwm_lookup));
platform_add_devices(ARRAY_AND_SIZE(ezx_devices));
platform_add_devices(ARRAY_AND_SIZE(a780_devices));
}
......
arch/arm/mach-pxa/hx4700.c
View file @ a5e1d715
......@@ -557,10 +557,8 @@ static struct platform_device hx4700_lcd = {
*/
static struct platform_pwm_backlight_data backlight_data = {
.pwm_id = -1, /* Superseded by pwm_lookup */
.max_brightness = 200,
.dft_brightness = 100,
.pwm_period_ns = 30923,
.enable_gpio = -1,
};
......@@ -630,7 +628,6 @@ static struct spi_board_info tsc2046_board_info[] __initdata = {
static struct pxa2xx_spi_master pxa_ssp2_master_info = {
.num_chipselect = 1,
.clock_enable = CKEN_SSP2,
.enable_dma = 1,
};
......
arch/arm/mach-pxa/icontrol.c
View file @ a5e1d715
......@@ -116,13 +116,11 @@ static struct spi_board_info mcp251x_board_info[] = {
};
static struct pxa2xx_spi_master pxa_ssp3_spi_master_info = {
.clock_enable = CKEN_SSP3,
.num_chipselect = 2,
.enable_dma = 1
};
static struct pxa2xx_spi_master pxa_ssp4_spi_master_info = {
.clock_enable = CKEN_SSP4,
.num_chipselect = 2,
.enable_dma = 1
};
......
arch/arm/mach-pxa/include/mach/magician.h
View file @ a5e1d715
......@@ -52,9 +52,9 @@
#define GPIO101_MAGICIAN_KEY_VOL_DOWN 101
#define GPIO102_MAGICIAN_KEY_PHONE 102
#define GPIO103_MAGICIAN_LED_KP 103
#define GPIO104_MAGICIAN_LCD_POWER_1 104
#define GPIO105_MAGICIAN_LCD_POWER_2 105
#define GPIO106_MAGICIAN_LCD_POWER_3 106
#define GPIO104_MAGICIAN_LCD_VOFF_EN 104
#define GPIO105_MAGICIAN_LCD_VON_EN 105
#define GPIO106_MAGICIAN_LCD_DCDC_NRESET 106
#define GPIO107_MAGICIAN_DS1WM_IRQ 107
#define GPIO108_MAGICIAN_GSM_READY 108
#define GPIO114_MAGICIAN_UNKNOWN 114
......@@ -78,43 +78,51 @@
* CPLD EGPIOs
*/
#define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO
#define MAGICIAN_EGPIO_BASE PXA_NR_BUILTIN_GPIO
#define MAGICIAN_EGPIO(reg,bit) \
(MAGICIAN_EGPIO_BASE + 8*reg + bit)
/* output */
#define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2)
#define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5)
#define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6)
#define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7)
#define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0)
#define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1)
#define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2)
#define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3)
#define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4)
#define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5)
#define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6)
#define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7)
#define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0)
#define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1)
#define EGPIO_MAGICIAN_UNKNOWN_WAVEDEV_DLL MAGICIAN_EGPIO(2, 2)
#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3)
#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4)
#define EGPIO_MAGICIAN_BQ24022_ISET2 MAGICIAN_EGPIO(2, 5)
#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7)
#define EGPIO_MAGICIAN_TOPPOLY_POWER MAGICIAN_EGPIO(0, 2)
#define EGPIO_MAGICIAN_LED_POWER MAGICIAN_EGPIO(0, 5)
#define EGPIO_MAGICIAN_GSM_RESET MAGICIAN_EGPIO(0, 6)
#define EGPIO_MAGICIAN_LCD_POWER MAGICIAN_EGPIO(0, 7)
#define EGPIO_MAGICIAN_SPK_POWER MAGICIAN_EGPIO(1, 0)
#define EGPIO_MAGICIAN_EP_POWER MAGICIAN_EGPIO(1, 1)
#define EGPIO_MAGICIAN_IN_SEL0 MAGICIAN_EGPIO(1, 2)
#define EGPIO_MAGICIAN_IN_SEL1 MAGICIAN_EGPIO(1, 3)
#define EGPIO_MAGICIAN_MIC_POWER MAGICIAN_EGPIO(1, 4)
#define EGPIO_MAGICIAN_CODEC_RESET MAGICIAN_EGPIO(1, 5)
#define EGPIO_MAGICIAN_CODEC_POWER MAGICIAN_EGPIO(1, 6)
#define EGPIO_MAGICIAN_BL_POWER MAGICIAN_EGPIO(1, 7)
#define EGPIO_MAGICIAN_SD_POWER MAGICIAN_EGPIO(2, 0)
#define EGPIO_MAGICIAN_CARKIT_MIC MAGICIAN_EGPIO(2, 1)
#define EGPIO_MAGICIAN_IR_RX_SHUTDOWN MAGICIAN_EGPIO(2, 2)
#define EGPIO_MAGICIAN_FLASH_VPP MAGICIAN_EGPIO(2, 3)
#define EGPIO_MAGICIAN_BL_POWER2 MAGICIAN_EGPIO(2, 4)
#define EGPIO_MAGICIAN_BQ24022_ISET2 MAGICIAN_EGPIO(2, 5)
#define EGPIO_MAGICIAN_NICD_CHARGE MAGICIAN_EGPIO(2, 6)
#define EGPIO_MAGICIAN_GSM_POWER MAGICIAN_EGPIO(2, 7)
/* input */
#define EGPIO_MAGICIAN_CABLE_STATE_AC MAGICIAN_EGPIO(4, 0)
#define EGPIO_MAGICIAN_CABLE_STATE_USB MAGICIAN_EGPIO(4, 1)
/* USB or AC charger type */
#define EGPIO_MAGICIAN_CABLE_TYPE MAGICIAN_EGPIO(4, 0)
/*
* Vbus is detected
* FIXME behaves like (6,3), may differ for host/device
*/
#define EGPIO_MAGICIAN_CABLE_VBUS MAGICIAN_EGPIO(4, 1)
#define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0)
#define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1)
#define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2)
#define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3)
#define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4)
#define EGPIO_MAGICIAN_BOARD_ID0 MAGICIAN_EGPIO(5, 0)
#define EGPIO_MAGICIAN_BOARD_ID1 MAGICIAN_EGPIO(5, 1)
#define EGPIO_MAGICIAN_BOARD_ID2 MAGICIAN_EGPIO(5, 2)
#define EGPIO_MAGICIAN_LCD_SELECT MAGICIAN_EGPIO(5, 3)
#define EGPIO_MAGICIAN_nSD_READONLY MAGICIAN_EGPIO(5, 4)
#define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1)
#define EGPIO_MAGICIAN_EP_INSERT MAGICIAN_EGPIO(6, 1)
/* FIXME behaves like (4,1), may differ for host/device */
#define EGPIO_MAGICIAN_CABLE_INSERTED MAGICIAN_EGPIO(6, 3)
#endif /* _MAGICIAN_H_ */
arch/arm/mach-pxa/include/mach/pxa27x.h
View file @ a5e1d715
......@@ -19,7 +19,7 @@
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
extern int __init pxa27x_set_pwrmode(unsigned int mode);
extern int pxa27x_set_pwrmode(unsigned int mode);
extern void pxa27x_cpu_pm_enter(suspend_state_t state);
#endif /* __MACH_PXA27x_H */
arch/arm/mach-pxa/lpd270.c
View file @ a5e1d715
......@@ -23,6 +23,7 @@
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>
......@@ -271,11 +272,14 @@ static struct platform_device lpd270_flash_device[2] = {
},
};
static struct pwm_lookup lpd270_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data lpd270_backlight_data = {
.pwm_id = 0,
.max_brightness = 1,
.dft_brightness = 1,
.pwm_period_ns = 78770,
.enable_gpio = -1,
};
......@@ -474,6 +478,7 @@ static void __init lpd270_init(void)
*/
ARB_CNTRL = ARB_CORE_PARK | 0x234;
pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
pxa_set_ac97_info(NULL);
......
arch/arm/mach-pxa/magician.c
View file @ a5e1d715
This diff is collapsed.
arch/arm/mach-pxa/mainstone.c
View file @ a5e1d715
......@@ -26,6 +26,7 @@
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>
#include <linux/i2c/pxa-i2c.h>
......@@ -248,11 +249,14 @@ static struct platform_device mst_flash_device[2] = {
};
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct pwm_lookup mainstone_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data mainstone_backlight_data = {
.pwm_id = 0,
.max_brightness = 1023,
.dft_brightness = 1023,
.pwm_period_ns = 78770,
.enable_gpio = -1,
};
......@@ -266,9 +270,16 @@ static struct platform_device mainstone_backlight_device = {
static void __init mainstone_backlight_register(void)
{
int ret = platform_device_register(&mainstone_backlight_device);
if (ret)
int ret;
pwm_add_table(mainstone_pwm_lookup, ARRAY_SIZE(mainstone_pwm_lookup));
ret = platform_device_register(&mainstone_backlight_device);
if (ret) {
printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
pwm_remove_table(mainstone_pwm_lookup,
ARRAY_SIZE(mainstone_pwm_lookup));
}
}
#else
#define mainstone_backlight_register() do { } while (0)
......
arch/arm/mach-pxa/mioa701.c
View file @ a5e1d715
......@@ -26,6 +26,7 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/gpio_keys.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/rtc.h>
#include <linux/leds.h>
......@@ -181,12 +182,15 @@ static unsigned long mioa701_pin_config[] = {
MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH),
};
static struct pwm_lookup mioa701_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight", NULL, 4000 * 1024,
PWM_POLARITY_NORMAL),
};
/* LCD Screen and Backlight */
static struct platform_pwm_backlight_data mioa701_backlight_data = {
.pwm_id = 0,
.max_brightness = 100,
.dft_brightness = 50,
.pwm_period_ns = 4000 * 1024, /* Fl = 250kHz */
.enable_gpio = -1,
};
......@@ -678,6 +682,7 @@ MIO_SIMPLE_DEV(mioa701_led, "leds-gpio", &gpio_led_info)
MIO_SIMPLE_DEV(pxa2xx_pcm, "pxa2xx-pcm", NULL)
MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL)
MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL)
MIO_SIMPLE_DEV(wm9713_acodec, "wm9713-codec", NULL);
MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data);
MIO_SIMPLE_DEV(mioa701_camera, "soc-camera-pdrv",&iclink);
......@@ -685,6 +690,7 @@ static struct platform_device *devices[] __initdata = {
&mioa701_gpio_keys,
&mioa701_backlight,
&mioa701_led,
&wm9713_acodec,
&pxa2xx_pcm,
&mioa701_sound,
&power_dev,
......@@ -751,6 +757,7 @@ static void __init mioa701_machine_init(void)
pxa_set_udc_info(&mioa701_udc_info);
pxa_set_ac97_info(&mioa701_ac97_info);
pm_power_off = mioa701_poweroff;
pwm_add_table(mioa701_pwm_lookup, ARRAY_SIZE(mioa701_pwm_lookup));
platform_add_devices(devices, ARRAY_SIZE(devices));
gsm_init();
......
arch/arm/mach-pxa/palm27x.c
View file @ a5e1d715
......@@ -15,6 +15,7 @@
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/pda_power.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio.h>
#include <linux/wm97xx.h>
......@@ -270,6 +271,11 @@ void __init palm27x_ac97_init(int minv, int maxv, int jack, int reset)
* Backlight
******************************************************************************/
#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
static struct pwm_lookup palm27x_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 3500 * 1024,
PWM_POLARITY_NORMAL),
};
static int palm_bl_power;
static int palm_lcd_power;
......@@ -318,10 +324,8 @@ static void palm27x_backlight_exit(struct device *dev)
}
static struct platform_pwm_backlight_data palm27x_backlight_data = {
.pwm_id = 0,
.max_brightness = 0xfe,
.dft_brightness = 0x7e,
.pwm_period_ns = 3500 * 1024,
.enable_gpio = -1,
.init = palm27x_backlight_init,
.notify = palm27x_backlight_notify,
......@@ -340,6 +344,7 @@ void __init palm27x_pwm_init(int bl, int lcd)
{
palm_bl_power = bl;
palm_lcd_power = lcd;
pwm_add_lookup(palm27x_pwm_lookup, ARRAY_SIZE(palm27x_pwm_lookup));
platform_device_register(&palm27x_backlight);
}
#endif
......
arch/arm/mach-pxa/palmtc.c
View file @ a5e1d715
......@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/input.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio.h>
#include <linux/input/matrix_keypad.h>
......@@ -166,11 +167,14 @@ static inline void palmtc_keys_init(void) {}
* Backlight
******************************************************************************/
#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
static struct pwm_lookup palmtc_pwm_lookup[] = {
PWM_LOOKUP("pxa25x-pwm.1", 0, "pwm-backlight.0", NULL, PALMTC_PERIOD_NS,
PWM_PERIOD_NORMAL),
};
static struct platform_pwm_backlight_data palmtc_backlight_data = {
.pwm_id = 1,
.max_brightness = PALMTC_MAX_INTENSITY,
.dft_brightness = PALMTC_MAX_INTENSITY,
.pwm_period_ns = PALMTC_PERIOD_NS,
.enable_gpio = GPIO_NR_PALMTC_BL_POWER,
};
......@@ -184,6 +188,7 @@ static struct platform_device palmtc_backlight = {
static void __init palmtc_pwm_init(void)
{
pwm_add_table(palmtc_pwm_lookup, ARRAY_SIZE(palmtc_pwm_lookup));
platform_device_register(&palmtc_backlight);
}
#else
......
arch/arm/mach-pxa/palmte2.c
View file @ a5e1d715
......@@ -21,6 +21,7 @@
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/pda_power.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/gpio.h>
#include <linux/wm97xx.h>
......@@ -138,6 +139,11 @@ static struct platform_device palmte2_pxa_keys = {
/******************************************************************************
* Backlight
******************************************************************************/
static struct pwm_lookup palmte2_pwm_lookup[] = {
PWM_LOOKUP("pxa25x-pwm.0", 0, "pwm-backlight.0", NULL,
PALMTE2_PERIOD_NS, PWM_POLARITY_NORMAL),
};
static struct gpio palmte_bl_gpios[] = {
{ GPIO_NR_PALMTE2_BL_POWER, GPIOF_INIT_LOW, "Backlight power" },
{ GPIO_NR_PALMTE2_LCD_POWER, GPIOF_INIT_LOW, "LCD power" },
......@@ -161,10 +167,8 @@ static void palmte2_backlight_exit(struct device *dev)
}
static struct platform_pwm_backlight_data palmte2_backlight_data = {
.pwm_id = 0,
.max_brightness = PALMTE2_MAX_INTENSITY,
.dft_brightness = PALMTE2_MAX_INTENSITY,
.pwm_period_ns = PALMTE2_PERIOD_NS,
.enable_gpio = -1,
.init = palmte2_backlight_init,
.notify = palmte2_backlight_notify,
......@@ -355,6 +359,7 @@ static void __init palmte2_init(void)
pxa_set_ac97_info(&palmte2_ac97_pdata);
pxa_set_ficp_info(&palmte2_ficp_platform_data);
pwm_add_table(palmte2_pwm_lookup, ARRAY_SIZE(palmte2_pwm_lookup));
platform_add_devices(devices, ARRAY_SIZE(devices));
}
......
arch/arm/mach-pxa/pcm990-baseboard.c
View file @ a5e1d715
......@@ -24,6 +24,7 @@
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <media/mt9v022.h>
......@@ -148,11 +149,14 @@ static struct pxafb_mach_info pcm990_fbinfo __initdata = {
};
#endif
static struct pwm_lookup pcm990_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data pcm990_backlight_data = {
.pwm_id = 0,
.max_brightness = 1023,
.dft_brightness = 1023,
.pwm_period_ns = 78770,
.enable_gpio = -1,
};
......@@ -542,6 +546,7 @@ void __init pcm990_baseboard_init(void)
#ifndef CONFIG_PCM990_DISPLAY_NONE
pxa_set_fb_info(NULL, &pcm990_fbinfo);
#endif
pwm_add_table(pcm990_pwm_lookup, ARRAY_SIZE(pcm990_pwm_lookup));
platform_device_register(&pcm990_backlight_device);
/* MMC */
......
arch/arm/mach-pxa/pxa27x.c
View file @ a5e1d715
......@@ -84,7 +84,7 @@ EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
*/
static unsigned int pwrmode = PWRMODE_SLEEP;
int __init pxa27x_set_pwrmode(unsigned int mode)
int pxa27x_set_pwrmode(unsigned int mode)
{
switch (mode) {
case PWRMODE_SLEEP:
......
arch/arm/mach-pxa/raumfeld.c
View file @ a5e1d715
......@@ -29,6 +29,7 @@
#include <linux/leds.h>
#include <linux/w1-gpio.h>
#include <linux/sched.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/i2c.h>
#include <linux/i2c/pxa-i2c.h>
......@@ -507,7 +508,7 @@ static struct w1_gpio_platform_data w1_gpio_platform_data = {
.ext_pullup_enable_pin = -EINVAL,
};
struct platform_device raumfeld_w1_gpio_device = {
static struct platform_device raumfeld_w1_gpio_device = {
.name = "w1-gpio",
.dev = {
.platform_data = &w1_gpio_platform_data
......@@ -531,13 +532,15 @@ static void __init raumfeld_w1_init(void)
* Framebuffer device
*/
static struct pwm_lookup raumfeld_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight", NULL, 10000,
PWM_POLARITY_NORMAL),
};
/* PWM controlled backlight */
static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = {
.pwm_id = 0,
.max_brightness = 100,
.dft_brightness = 100,
/* 10000 ns = 10 ms ^= 100 kHz */
.pwm_period_ns = 10000,
.enable_gpio = -1,
};
......@@ -618,6 +621,8 @@ static void __init raumfeld_lcd_init(void)
} else {
mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT;
pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1);
pwm_add_table(raumfeld_pwm_lookup,
ARRAY_SIZE(raumfeld_pwm_lookup));
platform_device_register(&raumfeld_pwm_backlight_device);
}
......@@ -629,7 +634,7 @@ static void __init raumfeld_lcd_init(void)
* SPI devices
*/
struct spi_gpio_platform_data raumfeld_spi_platform_data = {
static struct spi_gpio_platform_data raumfeld_spi_platform_data = {
.sck = GPIO_SPI_CLK,
.mosi = GPIO_SPI_MOSI,
.miso = GPIO_SPI_MISO,
......@@ -848,7 +853,7 @@ static void __init raumfeld_power_init(void)
static struct regulator_consumer_supply audio_va_consumer_supply =
REGULATOR_SUPPLY("va", "0-0048");
struct regulator_init_data audio_va_initdata = {
static struct regulator_init_data audio_va_initdata = {
.consumer_supplies = &audio_va_consumer_supply,
.num_consumer_supplies = 1,
.constraints = {
......@@ -880,7 +885,7 @@ static struct regulator_consumer_supply audio_dummy_supplies[] = {
REGULATOR_SUPPLY("vlc", "0-0048"),
};
struct regulator_init_data audio_dummy_initdata = {
static struct regulator_init_data audio_dummy_initdata = {
.consumer_supplies = audio_dummy_supplies,
.num_consumer_supplies = ARRAY_SIZE(audio_dummy_supplies),
.constraints = {
......@@ -928,7 +933,7 @@ static struct regulator_init_data vcc_mmc_init_data = {
.num_consumer_supplies = 1,
};
struct max8660_subdev_data max8660_v6_subdev_data = {
static struct max8660_subdev_data max8660_v6_subdev_data = {
.id = MAX8660_V6,
.name = "vmmc",
.platform_data = &vcc_mmc_init_data,
......
arch/arm/mach-pxa/tavorevb.c
View file @ a5e1d715
......@@ -18,6 +18,7 @@
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/smc91x.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <asm/mach-types.h>
......@@ -168,21 +169,24 @@ static inline void tavorevb_init_keypad(void) {}
#endif /* CONFIG_KEYBOARD_PXA27x || CONFIG_KEYBOARD_PXA27x_MODULE */
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct pwm_lookup tavorevb_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.0", 1, "pwm-backlight.0", NULL, 100000,
PWM_POLARITY_NORMAL),
PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.1", NULL, 100000,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data tavorevb_backlight_data[] = {
[0] = {
/* primary backlight */
.pwm_id = 2,
.max_brightness = 100,
.dft_brightness = 100,
.pwm_period_ns = 100000,
.enable_gpio = -1,
},
[1] = {
/* secondary backlight */
.pwm_id = 0,
.max_brightness = 100,
.dft_brightness = 100,
.pwm_period_ns = 100000,
.enable_gpio = -1,
},
};
......@@ -470,6 +474,7 @@ static struct pxafb_mach_info tavorevb_lcd_info = {
static void __init tavorevb_init_lcd(void)
{
pwm_add_table(tavorevb_pwm_lookup, ARRAY_SIZE(tavorevb_pwm_lookup));
platform_device_register(&tavorevb_backlight_devices[0]);
platform_device_register(&tavorevb_backlight_devices[1]);
pxa_set_fb_info(NULL, &tavorevb_lcd_info);
......
arch/arm/mach-pxa/viper.c
View file @ a5e1d715
......@@ -39,6 +39,7 @@
#include <linux/i2c/pxa-i2c.h>
#include <linux/serial_8250.h>
#include <linux/smc91x.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/usb/isp116x.h>
#include <linux/mtd/mtd.h>
......@@ -350,6 +351,11 @@ static struct pxafb_mach_info fb_info = {
.lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
};
static struct pwm_lookup viper_pwm_lookup[] = {
PWM_LOOKUP("pxa25x-pwm.0", 0, "pwm-backlight.0", NULL, 1000000,
PWM_POLARITY_NORMAL),
};
static int viper_backlight_init(struct device *dev)
{
int ret;
......@@ -398,10 +404,8 @@ static void viper_backlight_exit(struct device *dev)
}
static struct platform_pwm_backlight_data viper_backlight_data = {
.pwm_id = 0,
.max_brightness = 100,
.dft_brightness = 100,
.pwm_period_ns = 1000000,
.enable_gpio = -1,
.init = viper_backlight_init,
.notify = viper_backlight_notify,
......@@ -939,6 +943,7 @@ static void __init viper_init(void)
smc91x_device.num_resources--;
pxa_set_i2c_info(NULL);
pwm_add_table(viper_pwm_lookup, ARRAY_SIZE(viper_pwm_lookup));
platform_add_devices(viper_devs, ARRAY_SIZE(viper_devs));
viper_init_vcore_gpios();
......
arch/arm/mach-pxa/z2.c
View file @ a5e1d715
......@@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/z2_battery.h>
#include <linux/dma-mapping.h>
......@@ -199,21 +200,24 @@ static inline void z2_nor_init(void) {}
* Backlight
******************************************************************************/
#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
static struct pwm_lookup z2_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.1", 0, "pwm-backlight.0", NULL, 1260320,
PWM_POLARITY_NORMAL),
PWM_LOOKUP("pxa27x-pwm.0", 1, "pwm-backlight.1", NULL, 1260320,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data z2_backlight_data[] = {
[0] = {
/* Keypad Backlight */
.pwm_id = 1,
.max_brightness = 1023,
.dft_brightness = 0,
.pwm_period_ns = 1260320,
.enable_gpio = -1,
},
[1] = {
/* LCD Backlight */
.pwm_id = 2,
.max_brightness = 1023,
.dft_brightness = 512,
.pwm_period_ns = 1260320,
.enable_gpio = -1,
},
};
......@@ -236,6 +240,7 @@ static struct platform_device z2_backlight_devices[2] = {
};
static void __init z2_pwm_init(void)
{
pwm_add_table(z2_pwm_lookup, ARRAY_SIZE(z2_pwm_lookup));
platform_device_register(&z2_backlight_devices[0]);
platform_device_register(&z2_backlight_devices[1]);
}
......@@ -595,13 +600,11 @@ static struct spi_board_info spi_board_info[] __initdata = {
};
static struct pxa2xx_spi_master pxa_ssp1_master_info = {
.clock_enable = CKEN_SSP,
.num_chipselect = 1,
.enable_dma = 1,
};
static struct pxa2xx_spi_master pxa_ssp2_master_info = {
.clock_enable = CKEN_SSP2,
.num_chipselect = 1,
};
......
arch/arm/mach-pxa/zylonite.c
View file @ a5e1d715
......@@ -19,6 +19,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/pwm.h>
#include <linux/pwm_backlight.h>
#include <linux/smc91x.h>
......@@ -120,11 +121,14 @@ static inline void zylonite_init_leds(void) {}
#endif
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static struct pwm_lookup zylonite_pwm_lookup[] = {
PWM_LOOKUP("pxa27x-pwm.1", 1, "pwm-backlight.0", NULL, 10000,
PWM_POLARITY_NORMAL),
};
static struct platform_pwm_backlight_data zylonite_backlight_data = {
.pwm_id = 3,
.max_brightness = 100,
.dft_brightness = 100,
.pwm_period_ns = 10000,
.enable_gpio = -1,
};
......@@ -206,6 +210,7 @@ static struct pxafb_mach_info zylonite_sharp_lcd_info = {
static void __init zylonite_init_lcd(void)
{
pwm_add_table(zylonite_pwm_lookup, ARRAY_SIZE(zylonite_pwm_lookup));
platform_device_register(&zylonite_backlight_device);
if (lcd_id & 0x20) {
......
arch/arm/mach-qcom/platsmp.c
View file @ a5e1d715
......@@ -49,7 +49,7 @@ extern void secondary_startup_arm(void);
static DEFINE_SPINLOCK(boot_lock);
#ifdef CONFIG_HOTPLUG_CPU
static void __ref qcom_cpu_die(unsigned int cpu)
static void qcom_cpu_die(unsigned int cpu)
{
wfi();
}
......
arch/arm/mach-realview/hotplug.c
View file @ a5e1d715
......@@ -90,7 +90,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
*
* Called with IRQs disabled
*/
void __ref realview_cpu_die(unsigned int cpu)
void realview_cpu_die(unsigned int cpu)
{
int spurious = 0;
......
arch/arm/mach-shmobile/Kconfig
View file @ a5e1d715
......@@ -98,76 +98,3 @@ config ARCH_SH73A0
comment "Renesas ARM SoCs System Configuration"
endif
if ARCH_SHMOBILE_LEGACY
comment "Renesas ARM SoCs System Type"
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select ARCH_RCAR_GEN1
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
config ARCH_R8A7779
bool "R-Car H1 (R8A77790)"
select ARCH_RCAR_GEN1
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
comment "Renesas ARM SoCs Board Type"
config MACH_BOCKW
bool "BOCK-W platform"
depends on ARCH_R8A7778
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select SND_SOC_AK4554 if SND_SIMPLE_CARD
select SND_SOC_AK4642 if SND_SIMPLE_CARD && I2C
select USE_OF
config MACH_BOCKW_REFERENCE
bool "BOCK-W - Reference Device Tree Implementation"
depends on ARCH_R8A7778
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select USE_OF
---help---
Use reference implementation of BockW board support
which makes use of device tree at the expense
of not supporting a number of devices.
This is intended to aid developers
comment "Renesas ARM SoCs System Configuration"
config CPU_HAS_INTEVT
bool
default y
config SH_CLK_CPG
bool
source "drivers/sh/Kconfig"
endif
if ARCH_SHMOBILE
menu "Timer and clock configuration"
config SHMOBILE_TIMER_HZ
int "Kernel HZ (jiffies per second)"
range 32 1024
default "128"
help
Allows the configuration of the timer frequency. It is customary
to have the timer interrupt run at 1000 Hz or 100 Hz, but in the
case of low timer frequencies other values may be more suitable.
Renesas ARM SoC systems using a 32768 Hz RCLK for clock events may
want to select a HZ value such as 128 that can evenly divide RCLK.
A HZ value that does not divide evenly may cause timer drift.
endmenu
endif
arch/arm/mach-shmobile/Makefile
View file @ a5e1d715
......@@ -3,7 +3,7 @@
#
# Common objects
obj-y := timer.o console.o
obj-y := timer.o
# CPU objects
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o
......@@ -18,12 +18,6 @@ obj-$(CONFIG_ARCH_R8A7794) += setup-r8a7794.o
obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
# Clock objects
ifndef CONFIG_COMMON_CLK
obj-y += clock.o
obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
endif
# CPU reset vector handling objects
cpu-y := platsmp.o headsmp.o
......@@ -49,11 +43,5 @@ obj-$(CONFIG_PM_RCAR) += pm-rcar.o
obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
# Board objects
ifndef CONFIG_ARCH_SHMOBILE_MULTI
obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
endif
# Framework support
obj-$(CONFIG_SMP) += $(smp-y)
arch/arm/mach-shmobile/Makefile.boot deleted 100644 → 0
View file @ 64fd8c8a
# per-board load address for uImage
loadaddr-y :=
loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
__ZRELADDR := $(sort $(loadaddr-y))
zreladdr-y += $(__ZRELADDR)
# Unsupported legacy stuff
#
#params_phys-y (Instead: Pass atags pointer in r2)
#initrd_phys-y (Instead: Use compiled-in initramfs)
arch/arm/mach-shmobile/board-bockw-reference.c deleted 100644 → 0
View file @ 64fd8c8a
/*
* Bock-W board support
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
#include "r8a7778.h"
/*
* see board-bock.c for checking detail of dip-switch
*/
#define FPGA 0x18200000
#define IRQ0MR 0x30
#define COMCTLR 0x101c
#define PFC 0xfffc0000
#define PUPR4 0x110
static void __init bockw_init(void)
{
void __iomem *fpga;
void __iomem *pfc;
#ifndef CONFIG_COMMON_CLK
r8a7778_clock_init();
#endif
r8a7778_init_irq_extpin_dt(1);
r8a7778_add_dt_devices();
fpga = ioremap_nocache(FPGA, SZ_1M);
if (fpga) {
/*
* CAUTION
*
* IRQ0/1 is cascaded interrupt from FPGA.
* it should be cared in the future
* Now, it is assuming IRQ0 was used only from SMSC.
*/
u16 val = ioread16(fpga + IRQ0MR);
val &= ~(1 << 4); /* enable SMSC911x */
iowrite16(val, fpga + IRQ0MR);
iounmap(fpga);
}
pfc = ioremap_nocache(PFC, 0x200);
if (pfc) {
/*
* FIXME
*
* SDHI CD/WP pin needs pull-up
*/
iowrite32(ioread32(pfc + PUPR4) | (3 << 26), pfc + PUPR4);
iounmap(pfc);
}
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char *const bockw_boards_compat_dt[] __initconst = {
"renesas,bockw-reference",
NULL,
};
DT_MACHINE_START(BOCKW_DT, "bockw")
.init_early = shmobile_init_delay,
.init_irq = r8a7778_init_irq_dt,
.init_machine = bockw_init,
.init_late = shmobile_init_late,
.dt_compat = bockw_boards_compat_dt,
MACHINE_END
arch/arm/mach-shmobile/board-bockw.c deleted 100644 → 0
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arch/arm/mach-shmobile/clock.c deleted 100644 → 0
View file @ 64fd8c8a
/*
* SH-Mobile Clock Framework
*
* Copyright (C) 2010 Magnus Damm
*
* Used together with arch/arm/common/clkdev.c and drivers/sh/clk.c.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sh_clk.h>
#include "clock.h"
#include "common.h"
unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
{
struct clk_ratio *p = clk->priv;
return clk->parent->rate / p->div * p->mul;
};
struct sh_clk_ops shmobile_fixed_ratio_clk_ops = {
.recalc = shmobile_fixed_ratio_clk_recalc,
};
int __init shmobile_clk_init(void)
{
/* Kick the child clocks.. */
recalculate_root_clocks();
/* Enable the necessary init clocks */
clk_enable_init_clocks();
return 0;
}
arch/arm/mach-shmobile/clock.h deleted 100644 → 0
View file @ 64fd8c8a
#ifndef CLOCK_H
#define CLOCK_H
/* legacy clock implementation */
struct clk;
unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
/* clock ratio */
struct clk_ratio {
int mul;
int div;
};
#define SH_CLK_RATIO(name, m, d) \
static struct clk_ratio name ##_ratio = { \
.mul = m, \
.div = d, \
}
#define SH_FIXED_RATIO_CLKg(name, p, r) \
struct clk name = { \
.parent = &p, \
.ops = &shmobile_fixed_ratio_clk_ops,\
.priv = &r ## _ratio, \
}
#define SH_FIXED_RATIO_CLK(name, p, r) \
static SH_FIXED_RATIO_CLKg(name, p, r)
#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
SH_CLK_RATIO(name, m, d); \
SH_FIXED_RATIO_CLK(name, p, name)
#define SH_CLK_SET_RATIO(p, m, d) \
do { \
(p)->mul = m; \
(p)->div = d; \
} while (0)
#endif
arch/arm/mach-shmobile/common.h
View file @ a5e1d715
#ifndef __ARCH_MACH_COMMON_H
#define __ARCH_MACH_COMMON_H
extern void shmobile_earlytimer_init(void);
extern void shmobile_init_delay(void);
struct twd_local_timer;
extern void shmobile_setup_console(void);
extern void shmobile_boot_vector(void);
extern unsigned long shmobile_boot_fn;
extern unsigned long shmobile_boot_arg;
......@@ -18,8 +15,6 @@ extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
struct clk;
extern int shmobile_clk_init(void);
extern struct platform_suspend_ops shmobile_suspend_ops;
#ifdef CONFIG_SUSPEND
......
arch/arm/mach-shmobile/console.c deleted 100644 → 0
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arch/arm/mach-shmobile/platsmp-apmu.c
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arch/arm/mach-shmobile/pm-r8a7779.c
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arch/arm/mach-shmobile/pm-rmobile.c
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arch/arm/mach-shmobile/pm-rmobile.h
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arch/arm/mach-shmobile/r8a7779.h
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arch/arm/mach-shmobile/setup-r8a7778.c
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arch/arm/mach-shmobile/timer.c
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arch/arm/mach-spear/hotplug.c
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arch/arm/mach-tegra/hotplug.c
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arch/arm/mach-ux500/hotplug.c
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arch/arm/mach-vexpress/hotplug.c
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drivers/clocksource/Kconfig
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drivers/clocksource/Makefile
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include/linux/spi/pxa2xx_spi.h
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