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Commit a68aa48d authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Stuff SAGV watermark into a sub-structure 

We'll want a SAGV transition watermark as well. Prepare
for that by collecting SAGV wm0 into a sub-strcture.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210226153204.1270-5-ville.syrjala@linux.intel.comReviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
parent f11449d2
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Inline Side-by-side
Showing with 20 additions and 18 deletions
drivers/gpu/drm/i915/display/intel_display.c
View file @ a68aa48d
......@@ -9400,7 +9400,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
&sw_plane_wm->wm[level]) ||
(level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
&sw_plane_wm->sagv_wm0)))
&sw_plane_wm->sagv.wm0)))
continue;
drm_err(&dev_priv->drm,
......@@ -9457,7 +9457,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
&sw_plane_wm->wm[level]) ||
(level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
&sw_plane_wm->sagv_wm0)))
&sw_plane_wm->sagv.wm0)))
continue;
drm_err(&dev_priv->drm,
......
drivers/gpu/drm/i915/display/intel_display_types.h
View file @ a68aa48d
......@@ -732,7 +732,9 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
struct skl_wm_level sagv_wm0;
struct {
struct skl_wm_level wm0;
} sagv;
bool is_planar;
};
......
drivers/gpu/drm/i915/intel_pm.c
View file @ a68aa48d
......@@ -3924,7 +3924,7 @@ static bool tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
if (wm->wm[0].plane_en && !wm->sagv_wm0.plane_en)
if (wm->wm[0].plane_en && !wm->sagv.wm0.plane_en)
return false;
}
......@@ -4753,7 +4753,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
if (level == 0 && pipe_wm->use_sagv_wm)
return &wm->sagv_wm0;
return &wm->sagv.wm0;
return &wm->wm[level];
}
......@@ -4965,8 +4965,8 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
if (wm->trans_wm.plane_res_b >= total[plane_id])
memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
if (wm->sagv_wm0.plane_res_b >= total[plane_id])
memset(&wm->sagv_wm0, 0, sizeof(wm->sagv_wm0));
if (wm->sagv.wm0.plane_res_b >= total[plane_id])
memset(&wm->sagv.wm0, 0, sizeof(wm->sagv.wm0));
}
return 0;
......@@ -5316,7 +5316,7 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
struct skl_plane_wm *plane_wm)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct skl_wm_level *sagv_wm = &plane_wm->sagv_wm0;
struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
......@@ -5648,7 +5648,7 @@ static bool skl_plane_wm_equals(struct drm_i915_private *dev_priv,
}
return skl_wm_level_equals(&wm1->trans_wm, &wm2->trans_wm) &&
skl_wm_level_equals(&wm1->sagv_wm0, &wm2->sagv_wm0);
skl_wm_level_equals(&wm1->sagv.wm0, &wm2->sagv.wm0);
}
static bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
......@@ -5886,13 +5886,13 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
enast(old_wm->trans_wm.plane_en),
enast(old_wm->sagv_wm0.plane_en),
enast(old_wm->sagv.wm0.plane_en),
enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
enast(new_wm->trans_wm.plane_en),
enast(new_wm->sagv_wm0.plane_en));
enast(new_wm->sagv.wm0.plane_en));
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d"
......@@ -5907,7 +5907,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
enast(old_wm->trans_wm.ignore_lines), old_wm->trans_wm.plane_res_l,
enast(old_wm->sagv_wm0.ignore_lines), old_wm->sagv_wm0.plane_res_l,
enast(old_wm->sagv.wm0.ignore_lines), old_wm->sagv.wm0.plane_res_l,
enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
......@@ -5918,7 +5918,7 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l,
enast(new_wm->sagv_wm0.ignore_lines), new_wm->sagv_wm0.plane_res_l);
enast(new_wm->sagv.wm0.ignore_lines), new_wm->sagv.wm0.plane_res_l);
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
......@@ -5929,13 +5929,13 @@ skl_print_wm_changes(struct intel_atomic_state *state)
old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
old_wm->trans_wm.plane_res_b,
old_wm->sagv_wm0.plane_res_b,
old_wm->sagv.wm0.plane_res_b,
new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
new_wm->trans_wm.plane_res_b,
new_wm->sagv_wm0.plane_res_b);
new_wm->sagv.wm0.plane_res_b);
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
......@@ -5946,13 +5946,13 @@ skl_print_wm_changes(struct intel_atomic_state *state)
old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
old_wm->trans_wm.min_ddb_alloc,
old_wm->sagv_wm0.min_ddb_alloc,
old_wm->sagv.wm0.min_ddb_alloc,
new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc,
new_wm->sagv_wm0.min_ddb_alloc);
new_wm->sagv.wm0.min_ddb_alloc);
}
}
}
......@@ -6189,7 +6189,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
}
if (INTEL_GEN(dev_priv) >= 12)
wm->sagv_wm0 = wm->wm[0];
wm->sagv.wm0 = wm->wm[0];
if (plane_id != PLANE_CURSOR)
val = intel_uncore_read(&dev_priv->uncore, PLANE_WM_TRANS(pipe, plane_id));
......
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