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Commit a813833d authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lwfinger/r8192E into staging-next 

* git://git.kernel.org/pub/scm/linux/kernel/git/lwfinger/r8192E: (61 commits)
  staging: rtl8192e: Fix compilation warnings
  staging: rtl8192e: Fix unload/reload problem
  staging: rtl8192e: Remove dead code associated with CONFIG_RTL_RFKILL
  staging: rtl8192e: Remove conditional code associated with EEPROM_OLD_FORMAT_SUPPORT
  staging: rtl8192e: Remove dead code associated with EFUSE_REPG_WORKAROUND
  staging: rtl8192e: Remove LOOP_TEST as parameter
  staging: rtl8192e: Remove dead code associated with CONFIG_FW_SETCHAN
  staging: rtl8192e: Remove dead code associated with CONFIG_RTLWIFI_DEBUGFS
  staging: rtl8192e: Remove dead code associated with _RTL8192_EXT_PATCH_
  staging: rtl8192e: Remove ifdefs for CONFIG_RTLLIB_DEBUG
  staging: rtl8192e: Remove dead code associated with RTL819x_DEBUG
  staging: rtl8192e: Remove dead code associated with _ENABLE_SW_BEACON
  staging: rtl8192e: Remove dead code associated with CONFIG_CRYPTO_HMAC
  staging: rtl8192e: Remove dead code associated with CONFIG_BT_30
  staging: rtl8192e: Remove dead code associated with ENABLE_NULL_PT_DEBUG
  staging: rtl8192e: Remove dead code associated with CONFIG_64BIT_DMA
  staging: rtl8192e: Remove dead code associated with CONFIG_RTLLIB_CRYPT_TKIP
  staging: rtl8192e: Remove dead code associated with IRQF_SHARED
  staging: rtl8192e: Remove dead code associated with CONFIG_CFG_80211
  staging: rtl8192e: Remove dead code associated with BUILT_IN_CRYPTO
  ...
parents ac657d58 bca54c01
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drivers/staging/rtl8192e/Makefile
View file @ a813833d
NIC_SELECT = RTL8192E
ccflags-y := -DRTL8192E
ccflags-y += -std=gnu89
ccflags-y += -O2
ccflags-y += -DTHOMAS_TURBO
ccflags-y += -DUSE_FW_SOURCE_IMG_FILE
ccflags-y += -DCONFIG_PM_RTL
ccflags-y += -DCONFIG_PM
ccflags-y += -DHAVE_NET_DEVICE_OPS
ccflags-y += -DENABLE_DOT11D
ccflags-y += -DENABLE_IPS
ccflags-y += -DENABLE_LPS
r8192e_pci-objs := \
r8192E_core.o \
r8180_93cx6.o \
r8192E_wx.o \
r8190_rtl8256.o \
r819xE_phy.o \
r819xE_firmware.o \
r819xE_cmdpkt.o \
r8192E_dm.o \
r8192_pm.o \
ieee80211/ieee80211_rx.o \
ieee80211/ieee80211_softmac.o \
ieee80211/ieee80211_tx.o \
ieee80211/ieee80211_wx.o \
ieee80211/ieee80211_module.o \
ieee80211/ieee80211_softmac_wx.o \
ieee80211/rtl819x_HTProc.o \
ieee80211/rtl819x_TSProc.o \
ieee80211/rtl819x_BAProc.o \
ieee80211/dot11d.o \
ieee80211/ieee80211_crypt.o \
ieee80211/ieee80211_crypt_tkip.o \
ieee80211/ieee80211_crypt_ccmp.o \
ieee80211/ieee80211_crypt_wep.o
rtl_core.o \
rtl_eeprom.o \
rtl_ps.o \
rtl_wx.o \
rtl_cam.o \
rtl_dm.o \
rtl_pm.o \
rtl_pci.o \
rtl_debug.o \
rtl_ethtool.o \
r8192E_dev.o \
r8192E_phy.o \
r8192E_firmware.o \
r8192E_cmdpkt.o \
r8192E_hwimg.o \
r8190P_rtl8256.o \
rtllib_rx.o \
rtllib_softmac.o \
rtllib_tx.o \
rtllib_wx.o \
rtllib_module.o \
rtllib_softmac_wx.o \
rtl819x_HTProc.o \
rtl819x_TSProc.o \
rtl819x_BAProc.o \
dot11d.o \
rtllib_crypt.o \
rtllib_crypt_tkip.o \
rtllib_crypt_ccmp.o \
rtllib_crypt_wep.o
obj-$(CONFIG_RTL8192E) += r8192e_pci.o
drivers/staging/rtl8192e/TODO 0 → 100644
View file @ a813833d
* merge into drivers/net/wireless/rtllib/rtl8192e
* clean up function naming
drivers/staging/rtl8192e/dot11d.c 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#include "dot11d.h"
struct channel_list {
u8 Channel[32];
u8 Len;
};
static struct channel_list ChannelPlan[] = {
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64,
149, 153, 157, 161, 165}, 24},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56,
60, 64}, 21},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52,
56, 60, 64}, 22},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52,
56, 60, 64}, 22},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52,
56, 60, 64}, 22},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52,
56, 60, 64}, 22},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13},
{{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52,
56, 60, 64}, 21}
};
void Dot11d_Init(struct rtllib_device *ieee)
{
struct rt_dot11d_info *pDot11dInfo = GET_DOT11D_INFO(ieee);
pDot11dInfo->bEnabled = false;
pDot11dInfo->State = DOT11D_STATE_NONE;
pDot11dInfo->CountryIeLen = 0;
memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
RESET_CIE_WATCHDOG(ieee);
}
void Dot11d_Channelmap(u8 channel_plan, struct rtllib_device *ieee)
{
int i, max_chan = 14, min_chan = 1;
ieee->bGlobalDomain = false;
if (ChannelPlan[channel_plan].Len != 0) {
memset(GET_DOT11D_INFO(ieee)->channel_map, 0,
sizeof(GET_DOT11D_INFO(ieee)->channel_map));
for (i = 0; i < ChannelPlan[channel_plan].Len; i++) {
if (ChannelPlan[channel_plan].Channel[i] < min_chan ||
ChannelPlan[channel_plan].Channel[i] > max_chan)
break;
GET_DOT11D_INFO(ieee)->channel_map[ChannelPlan
[channel_plan].Channel[i]] = 1;
}
}
switch (channel_plan) {
case COUNTRY_CODE_GLOBAL_DOMAIN:
ieee->bGlobalDomain = true;
for (i = 12; i <= 14; i++)
GET_DOT11D_INFO(ieee)->channel_map[i] = 2;
ieee->IbssStartChnl = 10;
ieee->ibss_maxjoin_chal = 11;
break;
case COUNTRY_CODE_WORLD_WIDE_13:
for (i = 12; i <= 13; i++)
GET_DOT11D_INFO(ieee)->channel_map[i] = 2;
ieee->IbssStartChnl = 10;
ieee->ibss_maxjoin_chal = 11;
break;
default:
ieee->IbssStartChnl = 1;
ieee->ibss_maxjoin_chal = 14;
break;
}
}
void Dot11d_Reset(struct rtllib_device *ieee)
{
struct rt_dot11d_info *pDot11dInfo = GET_DOT11D_INFO(ieee);
u32 i;
memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
for (i = 1; i <= 11; i++)
(pDot11dInfo->channel_map)[i] = 1;
for (i = 12; i <= 14; i++)
(pDot11dInfo->channel_map)[i] = 2;
pDot11dInfo->State = DOT11D_STATE_NONE;
pDot11dInfo->CountryIeLen = 0;
RESET_CIE_WATCHDOG(ieee);
}
void Dot11d_UpdateCountryIe(struct rtllib_device *dev, u8 *pTaddr,
u16 CoutryIeLen, u8 *pCoutryIe)
{
struct rt_dot11d_info *pDot11dInfo = GET_DOT11D_INFO(dev);
u8 i, j, NumTriples, MaxChnlNum;
struct chnl_txpow_triple *pTriple;
memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
MaxChnlNum = 0;
NumTriples = (CoutryIeLen - 3) / 3;
pTriple = (struct chnl_txpow_triple *)(pCoutryIe + 3);
for (i = 0; i < NumTriples; i++) {
if (MaxChnlNum >= pTriple->FirstChnl) {
printk(KERN_INFO "Dot11d_UpdateCountryIe(): Invalid"
" country IE, skip it........1\n");
return;
}
if (MAX_CHANNEL_NUMBER < (pTriple->FirstChnl +
pTriple->NumChnls)) {
printk(KERN_INFO "Dot11d_UpdateCountryIe(): Invalid "
"country IE, skip it........2\n");
return;
}
for (j = 0 ; j < pTriple->NumChnls; j++) {
pDot11dInfo->channel_map[pTriple->FirstChnl + j] = 1;
pDot11dInfo->MaxTxPwrDbmList[pTriple->FirstChnl + j] =
pTriple->MaxTxPowerInDbm;
MaxChnlNum = pTriple->FirstChnl + j;
}
pTriple = (struct chnl_txpow_triple *)((u8*)pTriple + 3);
}
UPDATE_CIE_SRC(dev, pTaddr);
pDot11dInfo->CountryIeLen = CoutryIeLen;
memcpy(pDot11dInfo->CountryIeBuf, pCoutryIe, CoutryIeLen);
pDot11dInfo->State = DOT11D_STATE_LEARNED;
}
u8 DOT11D_GetMaxTxPwrInDbm(struct rtllib_device *dev, u8 Channel)
{
struct rt_dot11d_info *pDot11dInfo = GET_DOT11D_INFO(dev);
u8 MaxTxPwrInDbm = 255;
if (MAX_CHANNEL_NUMBER < Channel) {
printk(KERN_INFO "DOT11D_GetMaxTxPwrInDbm(): Invalid "
"Channel\n");
return MaxTxPwrInDbm;
}
if (pDot11dInfo->channel_map[Channel])
MaxTxPwrInDbm = pDot11dInfo->MaxTxPwrDbmList[Channel];
return MaxTxPwrInDbm;
}
void DOT11D_ScanComplete(struct rtllib_device *dev)
{
struct rt_dot11d_info *pDot11dInfo = GET_DOT11D_INFO(dev);
switch (pDot11dInfo->State) {
case DOT11D_STATE_LEARNED:
pDot11dInfo->State = DOT11D_STATE_DONE;
break;
case DOT11D_STATE_DONE:
Dot11d_Reset(dev);
break;
case DOT11D_STATE_NONE:
break;
}
}
int ToLegalChannel(struct rtllib_device *dev, u8 channel)
{
struct rt_dot11d_info *pDot11dInfo = GET_DOT11D_INFO(dev);
u8 default_chn = 0;
u32 i;
for (i = 1; i <= MAX_CHANNEL_NUMBER; i++) {
if (pDot11dInfo->channel_map[i] > 0) {
default_chn = i;
break;
}
}
if (MAX_CHANNEL_NUMBER < channel) {
printk(KERN_ERR "%s(): Invalid Channel\n", __func__);
return default_chn;
}
if (pDot11dInfo->channel_map[channel] > 0)
return channel;
return default_chn;
}
drivers/staging/rtl8192e/dot11d.h
View file @ a813833d
#ifndef INC_DOT11D_H
#define INC_DOT11D_H
#ifdef ENABLE_DOT11D
#include "ieee80211.h"
struct _CHNL_TXPOWER_TRIPLE {
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef __INC_DOT11D_H
#define __INC_DOT11D_H
#include "rtllib.h"
struct chnl_txpow_triple {
u8 FirstChnl;
u8 NumChnls;
u8 MaxTxPowerInDbm;
};
enum _DOT11D_STATE {
enum dot11d_state {
DOT11D_STATE_NONE = 0,
DOT11D_STATE_LEARNED,
DOT11D_STATE_DONE,
};
/**
* struct _RT_DOT11D_INFO
* @CountryIeLen: value greater than 0 if @CountryIeBuf contains
* struct rt_dot11d_info * @CountryIeLen: value greater than 0 if @CountryIeBuf contains
* valid country information element.
* @chanell_map: holds channel values
* 0 - invalid,
......@@ -27,18 +45,19 @@ enum _DOT11D_STATE {
* @CountryIeSrcAddr - Source AP of the country IE
*/
struct _RT_DOT11D_INFO {
struct rt_dot11d_info {
bool bEnabled;
u16 CountryIeLen;
u8 CountryIeBuf[MAX_IE_LEN];
u8 CountryIeSrcAddr[6];
u8 CountryIeWatchdog;
u8 CountryIeBuf[MAX_IE_LEN];
u8 CountryIeSrcAddr[6];
u8 CountryIeWatchdog;
u8 channel_map[MAX_CHANNEL_NUMBER+1];
u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1];
u8 channel_map[MAX_CHANNEL_NUMBER+1];
u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1];
DOT11D_STATE State;
enum dot11d_state State;
};
static inline void cpMacAddr(unsigned char *des, unsigned char *src)
......@@ -46,49 +65,41 @@ static inline void cpMacAddr(unsigned char *des, unsigned char *src)
memcpy(des, src, 6);
}
#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO) \
((__pIeeeDev)->pDot11dInfo))
#define GET_DOT11D_INFO(__pIeeeDev) \
((struct rt_dot11d_info *)((__pIeeeDev)->pDot11dInfo))
#define IS_DOT11D_ENABLE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->bEnabled)
#define IS_COUNTRY_IE_VALID(__pIeeeDev) \
(GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0)
#define IS_DOT11D_ENABLE(__pIeeeDev) \
(GET_DOT11D_INFO(__pIeeeDev)->bEnabled)
#define IS_COUNTRY_IE_VALID(__pIeeeDev) \
(GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0)
#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) \
eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) \
cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) \
eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) \
cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \
(((__Ie).Length == 0 || (__Ie).Length != \
GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? FALSE : \
(!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, \
(((__Ie).Length == 0 || (__Ie).Length != \
GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \
false : (!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, \
(__Ie).Octet, (__Ie).Length)))
#define CIE_WATCHDOG_TH 1
#define GET_CIE_WATCHDOG(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)-> \
CountryIeWatchdog)
#define GET_CIE_WATCHDOG(__pIeeeDev) \
(GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog)
#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0
#define UPDATE_CIE_WATCHDOG(__pIeeeDev) (++GET_CIE_WATCHDOG(__pIeeeDev))
#define IS_DOT11D_STATE_DONE(__pIeeeDev) \
(GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE)
void Dot11d_Init(struct ieee80211_device *dev);
void Dot11d_Reset(struct ieee80211_device *dev);
void Dot11d_UpdateCountryIe(struct ieee80211_device *dev, u8 *pTaddr,
u16 CoutryIeLen, u8 *pCoutryIe);
u8 DOT11D_GetMaxTxPwrInDbm(struct ieee80211_device *dev, u8 channel);
void DOT11D_ScanComplete(struct ieee80211_device *dev);
int IsLegalChannel(struct ieee80211_device *dev, u8 channel);
#define IS_DOT11D_STATE_DONE(__pIeeeDev) \
(GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE)
int ToLegalChannel(struct ieee80211_device *dev, u8 channel);
void Dot11d_Init(struct rtllib_device *dev);
void Dot11d_Channelmap(u8 channel_plan, struct rtllib_device *ieee);
void Dot11d_Reset(struct rtllib_device *dev);
void Dot11d_UpdateCountryIe(struct rtllib_device *dev, u8 *pTaddr,
u16 CoutryIeLen, u8 *pCoutryIe);
u8 DOT11D_GetMaxTxPwrInDbm(struct rtllib_device *dev, u8 Channel);
void DOT11D_ScanComplete(struct rtllib_device *dev);
int ToLegalChannel(struct rtllib_device *dev, u8 channel);
#endif /* ENABLE_DOT11D */
#endif /* INC_DOT11D_H */
#endif
drivers/staging/rtl8192e/ieee80211/dot11d.c deleted 100644 → 0
View file @ ac657d58
#ifdef ENABLE_DOT11D
//-----------------------------------------------------------------------------
// File:
// Dot11d.c
//
// Description:
// Implement 802.11d.
//
//-----------------------------------------------------------------------------
#include "dot11d.h"
void
Dot11d_Init(struct ieee80211_device *ieee)
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee);
pDot11dInfo->bEnabled = 0;
pDot11dInfo->State = DOT11D_STATE_NONE;
pDot11dInfo->CountryIeLen = 0;
memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
RESET_CIE_WATCHDOG(ieee);
printk("Dot11d_Init()\n");
}
//
// Description:
// Reset to the state as we are just entering a regulatory domain.
//
void
Dot11d_Reset(struct ieee80211_device *ieee)
{
u32 i;
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(ieee);
#if 0
if(!pDot11dInfo->bEnabled)
return;
#endif
// Clear old channel map
memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
// Set new channel map
for (i=1; i<=11; i++) {
(pDot11dInfo->channel_map)[i] = 1;
}
for (i=12; i<=14; i++) {
(pDot11dInfo->channel_map)[i] = 2;
}
pDot11dInfo->State = DOT11D_STATE_NONE;
pDot11dInfo->CountryIeLen = 0;
RESET_CIE_WATCHDOG(ieee);
}
//
// Description:
// Update country IE from Beacon or Probe Resopnse
// and configure PHY for operation in the regulatory domain.
//
// TODO:
// Configure Tx power.
//
// Assumption:
// 1. IS_DOT11D_ENABLE() is TRUE.
// 2. Input IE is an valid one.
//
void
Dot11d_UpdateCountryIe(
struct ieee80211_device *dev,
u8 * pTaddr,
u16 CoutryIeLen,
u8 * pCoutryIe
)
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
u8 i, j, NumTriples, MaxChnlNum;
PCHNL_TXPOWER_TRIPLE pTriple;
memset(pDot11dInfo->channel_map, 0, MAX_CHANNEL_NUMBER+1);
memset(pDot11dInfo->MaxTxPwrDbmList, 0xFF, MAX_CHANNEL_NUMBER+1);
MaxChnlNum = 0;
NumTriples = (CoutryIeLen - 3) / 3; // skip 3-byte country string.
pTriple = (PCHNL_TXPOWER_TRIPLE)(pCoutryIe + 3);
for(i = 0; i < NumTriples; i++)
{
if(MaxChnlNum >= pTriple->FirstChnl)
{ // It is not in a monotonically increasing order, so stop processing.
printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........1\n");
return;
}
if(MAX_CHANNEL_NUMBER < (pTriple->FirstChnl + pTriple->NumChnls))
{ // It is not a valid set of channel id, so stop processing.
printk("Dot11d_UpdateCountryIe(): Invalid country IE, skip it........2\n");
return;
}
for(j = 0 ; j < pTriple->NumChnls; j++)
{
pDot11dInfo->channel_map[pTriple->FirstChnl + j] = 1;
pDot11dInfo->MaxTxPwrDbmList[pTriple->FirstChnl + j] = pTriple->MaxTxPowerInDbm;
MaxChnlNum = pTriple->FirstChnl + j;
}
pTriple = (PCHNL_TXPOWER_TRIPLE)((u8*)pTriple + 3);
}
#if 1
printk("Channel List:");
for(i=1; i<= MAX_CHANNEL_NUMBER; i++)
if(pDot11dInfo->channel_map[i] > 0)
printk(" %d", i);
printk("\n");
#endif
UPDATE_CIE_SRC(dev, pTaddr);
pDot11dInfo->CountryIeLen = CoutryIeLen;
memcpy(pDot11dInfo->CountryIeBuf, pCoutryIe,CoutryIeLen);
pDot11dInfo->State = DOT11D_STATE_LEARNED;
}
u8
DOT11D_GetMaxTxPwrInDbm(
struct ieee80211_device *dev,
u8 Channel
)
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
u8 MaxTxPwrInDbm = 255;
if(MAX_CHANNEL_NUMBER < Channel)
{
printk("DOT11D_GetMaxTxPwrInDbm(): Invalid Channel\n");
return MaxTxPwrInDbm;
}
if(pDot11dInfo->channel_map[Channel])
{
MaxTxPwrInDbm = pDot11dInfo->MaxTxPwrDbmList[Channel];
}
return MaxTxPwrInDbm;
}
void
DOT11D_ScanComplete(
struct ieee80211_device * dev
)
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
switch(pDot11dInfo->State)
{
case DOT11D_STATE_LEARNED:
pDot11dInfo->State = DOT11D_STATE_DONE;
break;
case DOT11D_STATE_DONE:
if( GET_CIE_WATCHDOG(dev) == 0 )
{ // Reset country IE if previous one is gone.
Dot11d_Reset(dev);
}
break;
case DOT11D_STATE_NONE:
break;
}
}
int IsLegalChannel(
struct ieee80211_device * dev,
u8 channel
)
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
if(MAX_CHANNEL_NUMBER < channel)
{
printk("IsLegalChannel(): Invalid Channel\n");
return 0;
}
if(pDot11dInfo->channel_map[channel] > 0)
return 1;
return 0;
}
int ToLegalChannel(
struct ieee80211_device * dev,
u8 channel
)
{
PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(dev);
u8 default_chn = 0;
u32 i = 0;
for (i=1; i<= MAX_CHANNEL_NUMBER; i++)
{
if(pDot11dInfo->channel_map[i] > 0)
{
default_chn = i;
break;
}
}
if(MAX_CHANNEL_NUMBER < channel)
{
printk("IsLegalChannel(): Invalid Channel\n");
return default_chn;
}
if(pDot11dInfo->channel_map[channel] > 0)
return channel;
return default_chn;
}
#endif
drivers/staging/rtl8192e/ieee80211/dot11d.h deleted 100644 → 0
View file @ ac657d58
#ifndef __INC_DOT11D_H
#define __INC_DOT11D_H
#ifdef ENABLE_DOT11D
#include "ieee80211.h"
//#define ENABLE_DOT11D
//#define DOT11D_MAX_CHNL_NUM 83
typedef struct _CHNL_TXPOWER_TRIPLE {
u8 FirstChnl;
u8 NumChnls;
u8 MaxTxPowerInDbm;
}CHNL_TXPOWER_TRIPLE, *PCHNL_TXPOWER_TRIPLE;
typedef enum _DOT11D_STATE {
DOT11D_STATE_NONE = 0,
DOT11D_STATE_LEARNED,
DOT11D_STATE_DONE,
}DOT11D_STATE;
typedef struct _RT_DOT11D_INFO {
//DECLARE_RT_OBJECT(RT_DOT11D_INFO);
bool bEnabled; // dot11MultiDomainCapabilityEnabled
u16 CountryIeLen; // > 0 if CountryIeBuf[] contains valid country information element.
u8 CountryIeBuf[MAX_IE_LEN];
u8 CountryIeSrcAddr[6]; // Source AP of the country IE.
u8 CountryIeWatchdog;
u8 channel_map[MAX_CHANNEL_NUMBER+1]; //!!!Value 0: Invalid, 1: Valid (active scan), 2: Valid (passive scan)
//u8 ChnlListLen; // #Bytes valid in ChnlList[].
//u8 ChnlList[DOT11D_MAX_CHNL_NUM];
u8 MaxTxPwrDbmList[MAX_CHANNEL_NUMBER+1];
DOT11D_STATE State;
}RT_DOT11D_INFO, *PRT_DOT11D_INFO;
#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
#define GET_DOT11D_INFO(__pIeeeDev) ((PRT_DOT11D_INFO)((__pIeeeDev)->pDot11dInfo))
#define IS_DOT11D_ENABLE(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->bEnabled
#define IS_COUNTRY_IE_VALID(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen > 0)
#define IS_EQUAL_CIE_SRC(__pIeeeDev, __pTa) eqMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
#define UPDATE_CIE_SRC(__pIeeeDev, __pTa) cpMacAddr(GET_DOT11D_INFO(__pIeeeDev)->CountryIeSrcAddr, __pTa)
#define IS_COUNTRY_IE_CHANGED(__pIeeeDev, __Ie) \
(((__Ie).Length == 0 || (__Ie).Length != GET_DOT11D_INFO(__pIeeeDev)->CountryIeLen) ? \
FALSE : \
(!memcmp(GET_DOT11D_INFO(__pIeeeDev)->CountryIeBuf, (__Ie).Octet, (__Ie).Length)))
#define CIE_WATCHDOG_TH 1
#define GET_CIE_WATCHDOG(__pIeeeDev) GET_DOT11D_INFO(__pIeeeDev)->CountryIeWatchdog
#define RESET_CIE_WATCHDOG(__pIeeeDev) GET_CIE_WATCHDOG(__pIeeeDev) = 0
#define UPDATE_CIE_WATCHDOG(__pIeeeDev) ++GET_CIE_WATCHDOG(__pIeeeDev)
#define IS_DOT11D_STATE_DONE(__pIeeeDev) (GET_DOT11D_INFO(__pIeeeDev)->State == DOT11D_STATE_DONE)
void
Dot11d_Init(
struct ieee80211_device *dev
);
void
Dot11d_Reset(
struct ieee80211_device *dev
);
void
Dot11d_UpdateCountryIe(
struct ieee80211_device *dev,
u8 * pTaddr,
u16 CoutryIeLen,
u8 * pCoutryIe
);
u8
DOT11D_GetMaxTxPwrInDbm(
struct ieee80211_device *dev,
u8 Channel
);
void
DOT11D_ScanComplete(
struct ieee80211_device * dev
);
int IsLegalChannel(
struct ieee80211_device * dev,
u8 channel
);
int ToLegalChannel(
struct ieee80211_device * dev,
u8 channel
);
#endif //ENABLE_DOT11D
#endif // #ifndef __INC_DOT11D_H
drivers/staging/rtl8192e/ieee80211/rtl819x_HTProc.c deleted 100644 → 0
View file @ ac657d58
This diff is collapsed.
drivers/staging/rtl8192e/internal.h 0 → 100644
View file @ a813833d
/*
* Cryptographic API.
*
* Copyright (c) 2002 James Morris <jmorris@intercode.com.au>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
*/
#ifndef _CRYPTO_INTERNAL_H
#define _CRYPTO_INTERNAL_H
#include <linux/version.h>
#include "rtl_crypto.h"
#include <linux/mm.h>
#include <linux/highmem.h>
#include <linux/init.h>
#include <linux/hardirq.h>
#include <linux/sched.h>
#include <asm/kmap_types.h>
extern enum km_type crypto_km_types[];
static inline enum km_type crypto_kmap_type(int out)
{
return crypto_km_types[(in_softirq() ? 2 : 0) + out];
}
static inline void *crypto_kmap(struct page *page, int out)
{
return kmap_atomic(page, crypto_kmap_type(out));
}
static inline void crypto_kunmap(void *vaddr, int out)
{
kunmap_atomic(vaddr, crypto_kmap_type(out));
}
static inline void crypto_yield(struct crypto_tfm *tfm)
{
if (!in_softirq())
cond_resched();
}
static inline void *crypto_tfm_ctx(struct crypto_tfm *tfm)
{
return (void *)&tfm[1];
}
struct crypto_alg *crypto_alg_lookup(const char *name);
#ifdef CONFIG_KMOD
void crypto_alg_autoload(const char *name);
struct crypto_alg *crypto_alg_mod_lookup(const char *name);
#else
static inline struct crypto_alg *crypto_alg_mod_lookup(const char *name)
{
return crypto_alg_lookup(name);
}
#endif
static inline int crypto_alloc_hmac_block(struct crypto_tfm *tfm)
{
return 0;
}
static inline void crypto_free_hmac_block(struct crypto_tfm *tfm)
{ }
#ifdef CONFIG_PROC_FS
void __init crypto_init_proc(void);
#else
static inline void crypto_init_proc(void)
{ }
#endif
int crypto_init_digest_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_cipher_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_compress_flags(struct crypto_tfm *tfm, u32 flags);
int crypto_init_digest_ops(struct crypto_tfm *tfm);
int crypto_init_cipher_ops(struct crypto_tfm *tfm);
int crypto_init_compress_ops(struct crypto_tfm *tfm);
void crypto_exit_digest_ops(struct crypto_tfm *tfm);
void crypto_exit_cipher_ops(struct crypto_tfm *tfm);
void crypto_exit_compress_ops(struct crypto_tfm *tfm);
#endif /* _CRYPTO_INTERNAL_H */
drivers/staging/rtl8192e/kmap_types.h 0 → 100644
View file @ a813833d
#ifndef __KMAP_TYPES_H
#define __KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
KM_SKB_SUNRPC_DATA,
KM_SKB_DATA_SOFTIRQ,
KM_USER0,
KM_USER1,
KM_BH_IRQ,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
KM_TYPE_NR
};
#define _ASM_KMAP_TYPES_H
#endif
drivers/staging/rtl8192e/license 0 → 100644
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This diff is collapsed.
drivers/staging/rtl8192e/r8190P_def.h 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef R8190P_DEF_H
#define R8190P_DEF_H
#include <linux/types.h>
#define MAX_SILENT_RESET_RX_SLOT_NUM 10
#define RX_MPDU_QUEUE 0
#define RX_CMD_QUEUE 1
typedef enum _rtl819x_loopback{
RTL819X_NO_LOOPBACK = 0,
RTL819X_MAC_LOOPBACK = 1,
RTL819X_DMA_LOOPBACK = 2,
RTL819X_CCK_LOOPBACK = 3,
}rtl819x_loopback_e;
#define RESET_DELAY_8185 20
#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
#define DESC90_RATE1M 0x00
#define DESC90_RATE2M 0x01
#define DESC90_RATE5_5M 0x02
#define DESC90_RATE11M 0x03
#define DESC90_RATE6M 0x04
#define DESC90_RATE9M 0x05
#define DESC90_RATE12M 0x06
#define DESC90_RATE18M 0x07
#define DESC90_RATE24M 0x08
#define DESC90_RATE36M 0x09
#define DESC90_RATE48M 0x0a
#define DESC90_RATE54M 0x0b
#define DESC90_RATEMCS0 0x00
#define DESC90_RATEMCS1 0x01
#define DESC90_RATEMCS2 0x02
#define DESC90_RATEMCS3 0x03
#define DESC90_RATEMCS4 0x04
#define DESC90_RATEMCS5 0x05
#define DESC90_RATEMCS6 0x06
#define DESC90_RATEMCS7 0x07
#define DESC90_RATEMCS8 0x08
#define DESC90_RATEMCS9 0x09
#define DESC90_RATEMCS10 0x0a
#define DESC90_RATEMCS11 0x0b
#define DESC90_RATEMCS12 0x0c
#define DESC90_RATEMCS13 0x0d
#define DESC90_RATEMCS14 0x0e
#define DESC90_RATEMCS15 0x0f
#define DESC90_RATEMCS32 0x20
#define SHORT_SLOT_TIME 9
#define NON_SHORT_SLOT_TIME 20
#define MAX_LINES_HWCONFIG_TXT 1000
#define MAX_BYTES_LINE_HWCONFIG_TXT 128
#define SW_THREE_WIRE 0
#define HW_THREE_WIRE 2
#define BT_DEMO_BOARD 0
#define BT_QA_BOARD 1
#define BT_FPGA 2
#define Rx_Smooth_Factor 20
#define QSLT_BK 0x1
#define QSLT_BE 0x0
#define QSLT_VI 0x4
#define QSLT_VO 0x6
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
#define NUM_OF_FIRMWARE_QUEUE 10
#define NUM_OF_PAGES_IN_FW 0x100
#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2
#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
#define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
#define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
#define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
#define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
#define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
typedef enum _VERSION_8190{
VERSION_8190_BD=0x3,
VERSION_8190_BE
}VERSION_8190,*PVERSION_8190;
#define IC_VersionCut_C 0x2
#define IC_VersionCut_D 0x3
#define IC_VersionCut_E 0x4
typedef enum tag_Rf_OpType
{
RF_OP_By_SW_3wire = 0,
RF_OP_By_FW,
RF_OP_MAX
}RF_OpType_E;
typedef enum _POWER_SAVE_MODE
{
POWER_SAVE_MODE_ACTIVE,
POWER_SAVE_MODE_SAVE,
}POWER_SAVE_MODE;
typedef enum _INTERFACE_SELECT_8190PCI{
INTF_SEL1_MINICARD = 0,
INTF_SEL0_PCIE = 1,
INTF_SEL2_RSV = 2,
INTF_SEL3_RSV = 3,
} INTERFACE_SELECT_8190PCI, *PINTERFACE_SELECT_8190PCI;
typedef struct _BB_REGISTER_DEFINITION{
u32 rfintfs;
u32 rfintfi;
u32 rfintfo;
u32 rfintfe;
u32 rf3wireOffset;
u32 rfLSSI_Select;
u32 rfTxGainStage;
u32 rfHSSIPara1;
u32 rfHSSIPara2;
u32 rfSwitchControl;
u32 rfAGCControl1;
u32 rfAGCControl2;
u32 rfRxIQImbalance;
u32 rfRxAFE;
u32 rfTxIQImbalance;
u32 rfTxAFE;
u32 rfLSSIReadBack;
u32 rfLSSIReadBackPi;
}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
typedef struct _TX_FWINFO_STRUCUTRE{
u8 TxRate:7;
u8 CtsEnable:1;
u8 RtsRate:7;
u8 RtsEnable:1;
u8 TxHT:1;
u8 Short:1;
u8 TxBandwidth:1;
u8 TxSubCarrier:2;
u8 STBC:2;
u8 AllowAggregation:1;
u8 RtsHT:1;
u8 RtsShort:1;
u8 RtsBandwidth:1;
u8 RtsSubcarrier:2;
u8 RtsSTBC:2;
u8 EnableCPUDur:1;
u32 RxMF:2;
u32 RxAMD:3;
u32 Reserved1:3;
u32 TxAGCOffset:4;
u32 TxAGCSign:1;
u32 Tx_INFO_RSVD:6;
u32 PacketID:13;
}TX_FWINFO_T;
typedef struct _TX_FWINFO_8190PCI{
u8 TxRate:7;
u8 CtsEnable:1;
u8 RtsRate:7;
u8 RtsEnable:1;
u8 TxHT:1;
u8 Short:1;
u8 TxBandwidth:1;
u8 TxSubCarrier:2;
u8 STBC:2;
u8 AllowAggregation:1;
u8 RtsHT:1;
u8 RtsShort:1;
u8 RtsBandwidth:1;
u8 RtsSubcarrier:2;
u8 RtsSTBC:2;
u8 EnableCPUDur:1;
u32 RxMF:2;
u32 RxAMD:3;
u32 TxPerPktInfoFeedback:1;
u32 Reserved1:2;
u32 TxAGCOffset:4;
u32 TxAGCSign:1;
u32 RAW_TXD:1;
u32 Retry_Limit:4;
u32 Reserved2:1;
u32 PacketID:13;
}TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
#define TX_DESC_SIZE 32
#define TX_DESC_CMD_SIZE 32
#define TX_STATUS_DESC_SIZE 32
#define TX_FWINFO_SIZE 8
#define RX_DESC_SIZE 16
#define RX_STATUS_DESC_SIZE 16
#define RX_DRIVER_INFO_SIZE 8
typedef struct _LOG_INTERRUPT_8190
{
u32 nIMR_COMDOK;
u32 nIMR_MGNTDOK;
u32 nIMR_HIGH;
u32 nIMR_VODOK;
u32 nIMR_VIDOK;
u32 nIMR_BEDOK;
u32 nIMR_BKDOK;
u32 nIMR_ROK;
u32 nIMR_RCOK;
u32 nIMR_TBDOK;
u32 nIMR_BDOK;
u32 nIMR_RXFOVW;
} LOG_INTERRUPT_8190_T, *PLOG_INTERRUPT_8190_T;
typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
u8 reserved:4;
u8 rxsc:2;
u8 sgi_en:1;
u8 ex_intf_flag:1;
}phy_ofdm_rx_status_rxsc_sgien_exintfflag;
typedef struct _phy_ofdm_rx_status_report_819xpci
{
u8 trsw_gain_X[4];
u8 pwdb_all;
u8 cfosho_X[4];
u8 cfotail_X[4];
u8 rxevm_X[2];
u8 rxsnr_X[4];
u8 pdsnr_X[2];
u8 csi_current_X[2];
u8 csi_target_X[2];
u8 sigevm;
u8 max_ex_pwr;
u8 sgi_en;
u8 rxsc_sgien_exflg;
}phy_sts_ofdm_819xpci_t;
typedef struct _phy_cck_rx_status_report_819xpci
{
u8 adc_pwdb_X[4];
u8 sq_rpt;
u8 cck_agc_rpt;
}phy_sts_cck_819xpci_t, phy_sts_cck_8192s_t;
#define PHY_RSSI_SLID_WIN_MAX 100
#define PHY_Beacon_RSSI_SLID_WIN_MAX 10
typedef struct _tx_desc_819x_pci {
u16 PktSize;
u8 Offset;
u8 Reserved1:3;
u8 CmdInit:1;
u8 LastSeg:1;
u8 FirstSeg:1;
u8 LINIP:1;
u8 OWN:1;
u8 TxFWInfoSize;
u8 RATid:3;
u8 DISFB:1;
u8 USERATE:1;
u8 MOREFRAG:1;
u8 NoEnc:1;
u8 PIFS:1;
u8 QueueSelect:5;
u8 NoACM:1;
u8 Resv:2;
u8 SecCAMID:5;
u8 SecDescAssign:1;
u8 SecType:2;
u16 TxBufferSize;
u8 PktId:7;
u8 Resv1:1;
u8 Reserved2;
u32 TxBuffAddr;
u32 NextDescAddress;
u32 Reserved5;
u32 Reserved6;
u32 Reserved7;
}tx_desc, *ptx_desc;
typedef struct _tx_desc_cmd_819x_pci {
u16 PktSize;
u8 Reserved1;
u8 CmdType:3;
u8 CmdInit:1;
u8 LastSeg:1;
u8 FirstSeg:1;
u8 LINIP:1;
u8 OWN:1;
u16 ElementReport;
u16 Reserved2;
u16 TxBufferSize;
u16 Reserved3;
u32 TxBuffAddr;
u32 NextDescAddress;
u32 Reserved4;
u32 Reserved5;
u32 Reserved6;
}tx_desc_cmd, *ptx_desc_cmd;
typedef struct _rx_desc_819x_pci{
u16 Length:14;
u16 CRC32:1;
u16 ICV:1;
u8 RxDrvInfoSize;
u8 Shift:2;
u8 PHYStatus:1;
u8 SWDec:1;
u8 LastSeg:1;
u8 FirstSeg:1;
u8 EOR:1;
u8 OWN:1;
u32 Reserved2;
u32 Reserved3;
u32 BufferAddress;
}rx_desc, *prx_desc;
typedef struct _rx_fwinfo_819x_pci{
u16 Reserved1:12;
u16 PartAggr:1;
u16 FirstAGGR:1;
u16 Reserved2:2;
u8 RxRate:7;
u8 RxHT:1;
u8 BW:1;
u8 SPLCP:1;
u8 Reserved3:2;
u8 PAM:1;
u8 Mcast:1;
u8 Bcast:1;
u8 Reserved4:1;
u32 TSFL;
}rx_fwinfo, *prx_fwinfo;
#endif
drivers/staging/rtl8192e/r8190P_hwimg.c 0 → 100644
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drivers/staging/rtl8192e/r8190P_hwimg.h 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef __INC_HAL8190Pci_FW_IMG_H
#define __INC_HAL8190Pci_FW_IMG_H
/*Created on 2008/12/ 3, 3:26*/
#include <linux/types.h>
#define BootArrayLengthPci 344
extern u8 Rtl8190PciFwBootArray[BootArrayLengthPci];
#define MainArrayLengthPci 55388
extern u8 Rtl8190PciFwMainArray[MainArrayLengthPci];
#define DataArrayLengthPci 2960
extern u8 Rtl8190PciFwDataArray[DataArrayLengthPci];
#define PHY_REGArrayLengthPci 280
extern u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLengthPci];
#define PHY_REG_1T2RArrayLengthPci 280
extern u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPci];
#define RadioA_ArrayLengthPci 246
extern u32 Rtl8190PciRadioA_Array[RadioA_ArrayLengthPci] ;
#define RadioB_ArrayLengthPci 78
extern u32 Rtl8190PciRadioB_Array[RadioB_ArrayLengthPci] ;
#define RadioC_ArrayLengthPci 246
extern u32 Rtl8190PciRadioC_Array[RadioC_ArrayLengthPci] ;
#define RadioD_ArrayLengthPci 78
extern u32 Rtl8190PciRadioD_Array[RadioD_ArrayLengthPci] ;
#define MACPHY_ArrayLengthPci 18
extern u32 Rtl8190PciMACPHY_Array[MACPHY_ArrayLengthPci] ;
#define MACPHY_Array_PGLengthPci 21
extern u32 Rtl8190PciMACPHY_Array_PG[MACPHY_Array_PGLengthPci] ;
#define AGCTAB_ArrayLengthPci 384
extern u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLengthPci] ;
#endif
drivers/staging/rtl8192e/r8190P_rtl8256.c 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#include "rtl_core.h"
#include "r8192E_phyreg.h"
#include "r8192E_phy.h"
#include "r8190P_rtl8256.h"
void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth)
{
u8 eRFPath;
struct r8192_priv *priv = rtllib_priv(dev);
for (eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) {
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
switch (Bandwidth) {
case HT_CHANNEL_WIDTH_20:
if (priv->card_8192_version == VERSION_8190_BD || priv->card_8192_version == VERSION_8190_BE) {
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
} else {
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
case HT_CHANNEL_WIDTH_20_40:
if (priv->card_8192_version == VERSION_8190_BD ||priv->card_8192_version == VERSION_8190_BE) {
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3ff);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0e1);
} else {
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
}
break;
default:
RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
return;
}
bool PHY_RF8256_Config(struct net_device* dev)
{
struct r8192_priv *priv = rtllib_priv(dev);
bool rtStatus = true;
priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
rtStatus = phy_RF8256_Config_ParaFile(dev);
return rtStatus;
}
bool phy_RF8256_Config_ParaFile(struct net_device* dev)
{
u32 u4RegValue = 0;
u8 eRFPath;
bool rtStatus = true;
BB_REGISTER_DEFINITION_T *pPhyReg;
struct r8192_priv *priv = rtllib_priv(dev);
u32 RegOffSetToBeCheck = 0x3;
u32 RegValueToBeCheck = 0x7f1;
u32 RF3_Final_Value = 0;
u8 ConstRetryTimes = 5, RetryTimes = 5;
u8 ret = 0;
for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++) {
if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
continue;
pPhyReg = &priv->PHYRegDef[eRFPath];
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);
rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
rtStatus = rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath);
if (rtStatus!= true) {
RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
RetryTimes = ConstRetryTimes;
RF3_Final_Value = 0;
switch (eRFPath) {
case RF90_PATH_A:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_B:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_C:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
case RF90_PATH_D:
while (RF3_Final_Value!=RegValueToBeCheck && RetryTimes != 0) {
ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
RetryTimes--;
}
break;
}
switch (eRFPath) {
case RF90_PATH_A:
case RF90_PATH_C:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if (ret) {
RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
goto phy_RF8256_Config_ParaFile_Fail;
}
}
RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
return true;
phy_RF8256_Config_ParaFile_Fail:
RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
return false;
}
void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
{
u32 TxAGC=0;
struct r8192_priv *priv = rtllib_priv(dev);
TxAGC = powerlevel;
if (priv->bDynamicTxLowPower == true)
{
if (priv->CustomerID == RT_CID_819x_Netcore)
TxAGC = 0x22;
else
TxAGC += priv->CckPwEnl;
}
if (TxAGC > 0x24)
TxAGC = 0x24;
rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
}
void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
{
struct r8192_priv *priv = rtllib_priv(dev);
u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
u8 index = 0;
u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
u8 byte0, byte1, byte2, byte3;
powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
powerBase1 = powerlevel;
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
for (index=0; index<6; index++)
{
writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1));
byte0 = (u8)(writeVal & 0x7f);
byte1 = (u8)((writeVal & 0x7f00)>>8);
byte2 = (u8)((writeVal & 0x7f0000)>>16);
byte3 = (u8)((writeVal & 0x7f000000)>>24);
if (byte0 > 0x24)
byte0 = 0x24;
if (byte1 > 0x24)
byte1 = 0x24;
if (byte2 > 0x24)
byte2 = 0x24;
if (byte3 > 0x24)
byte3 = 0x24;
if (index == 3)
{
writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
priv->Pwr_Track = writeVal_tmp;
}
if (priv->bDynamicTxHighPower == true)
{
writeVal = 0x03030303;
}
else
{
writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
}
rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
}
return;
}
drivers/staging/rtl8192e/r8190P_rtl8256.h 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef RTL8225H
#define RTL8225H
#define RTL819X_TOTAL_RF_PATH 2
extern void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth);
extern bool PHY_RF8256_Config(struct net_device* dev);
extern bool phy_RF8256_Config_ParaFile(struct net_device* dev);
extern void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel);
extern void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel);
#endif
drivers/staging/rtl8192e/r8192E_cmdpkt.c 0 → 100644
View file @ a813833d
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_cmdpkt.h 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef R819XUSB_CMDPKT_H
#define R819XUSB_CMDPKT_H
#define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t)
#define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t)
#define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t)
#define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)
#define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)
#define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t)
#define ISR_TxBcnOk BIT27
#define ISR_TxBcnErr BIT26
#define ISR_BcnTimerIntr BIT13
typedef struct tag_cmd_pkt_tx_feedback
{
u8 element_id;
u8 length;
u8 TID:4; /* */
u8 fail_reason:3; /* */
u8 tok:1;
u8 reserve1:4; /* */
u8 pkt_type:2; /* */
u8 bandwidth:1; /* */
u8 qos_pkt:1; /* */
u8 reserve2; /* */
u8 retry_cnt; /* */
u16 pkt_id; /* */
u16 seq_num; /* */
u8 s_rate;
u8 f_rate;
u8 s_rts_rate; /* */
u8 f_rts_rate; /* */
u16 pkt_length; /* */
u16 reserve3; /* */
u16 duration; /* */
}cmpk_txfb_t;
typedef struct tag_cmd_pkt_interrupt_status
{
u8 element_id;
u8 length;
u16 reserve;
u32 interrupt_status;
}cmpk_intr_sta_t;
typedef struct tag_cmd_pkt_set_configuration
{
u8 element_id;
u8 length;
u16 reserve1;
u8 cfg_reserve1:3;
u8 cfg_size:2;
u8 cfg_type:2;
u8 cfg_action:1;
u8 cfg_reserve2;
u8 cfg_page:4;
u8 cfg_reserve3:4;
u8 cfg_offset;
u32 value;
u32 mask;
}cmpk_set_cfg_t;
#define cmpk_query_cfg_t cmpk_set_cfg_t
typedef struct tag_tx_stats_feedback
{
u16 reserve1;
u8 length;
u8 element_id;
u16 txfail;
u16 txok;
u16 txmcok;
u16 txretry;
u16 txucok;
u16 txbcok;
u16 txbcfail;
u16 txmcfail;
u16 reserve2;
u16 txucfail;
u32 txmclength;
u32 txbclength;
u32 txuclength;
u16 reserve3_23;
u8 reserve3_1;
u8 rate;
}__attribute__((packed)) cmpk_tx_status_t;
typedef struct tag_rx_debug_message_feedback
{
u16 reserve1;
u8 length;
u8 element_id;
}cmpk_rx_dbginfo_t;
typedef struct tag_tx_rate_history
{
u8 element_id;
u8 length;
u16 reserved1;
u16 cck[4];
u16 ofdm[8];
u16 ht_mcs[4][16];
}__attribute__((packed)) cmpk_tx_rahis_t;
typedef enum tag_command_packet_directories
{
RX_TX_FEEDBACK = 0,
RX_INTERRUPT_STATUS = 1,
TX_SET_CONFIG = 2,
BOTH_QUERY_CONFIG = 3,
RX_TX_STATUS = 4,
RX_DBGINFO_FEEDBACK = 5,
RX_TX_PER_PKT_FEEDBACK = 6,
RX_TX_RATE_HISTORY = 7,
RX_CMD_ELE_MAX
}cmpk_element_e;
extern u32 cmpk_message_handle_rx(struct net_device *dev, struct rtllib_rx_stats * pstats);
extern bool cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
#endif
drivers/staging/rtl8192e/r8192E_core.c.porig 0 → 100644
View file @ a813833d
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_core.c.rej 0 → 100644
View file @ a813833d
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drivers/staging/rtl8192e/r8192E_dev.c 0 → 100644
View file @ a813833d
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_dev.h 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* Based on the r8180 driver, which is:
* Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef _RTL8192E_H
#define _RTL8192E_H
#include "r8190P_def.h"
u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, cb_desc *tcb_desc);
bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device* dev);
bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev);
bool rtl8192_HalTxCheckStuck(struct net_device *dev);
bool rtl8192_HalRxCheckStuck(struct net_device *dev);
void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta, u32 *p_intb);
void rtl8192_enable_rx(struct net_device *dev);
void rtl8192_enable_tx(struct net_device *dev);
void rtl8192_EnableInterrupt(struct net_device *dev);
void rtl8192_DisableInterrupt(struct net_device *dev);
void rtl8192_ClearInterrupt(struct net_device *dev);
void rtl8192_InitializeVariables(struct net_device *dev);
void rtl8192e_start_beacon(struct net_device *dev);
void rtl8192e_SetHwReg(struct net_device *dev,u8 variable,u8* val);
void rtl8192_get_eeprom_size(struct net_device* dev);
bool rtl8192_adapter_start(struct net_device *dev);
void rtl8192_link_change(struct net_device *dev);
void rtl8192_AllowAllDestAddr(struct net_device* dev, bool bAllowAllDA, bool WriteIntoReg);
void rtl8192_tx_fill_desc(struct net_device* dev, tx_desc * pdesc, cb_desc * cb_desc,
struct sk_buff* skb);
void rtl8192_tx_fill_cmd_desc(struct net_device* dev, tx_desc_cmd * entry,
cb_desc * cb_desc, struct sk_buff* skb);
bool rtl8192_rx_query_status_desc(struct net_device* dev, struct rtllib_rx_stats *stats,
rx_desc *pdesc, struct sk_buff* skb);
void rtl8192_halt_adapter(struct net_device *dev, bool reset);
void rtl8192_update_ratr_table(struct net_device* dev);
#endif
drivers/staging/rtl8192e/r8192E_firmware.c 0 → 100644
View file @ a813833d
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_firmware.h 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef __INC_FIRMWARE_H
#define __INC_FIRMWARE_H
#define RTL8190_CPU_START_OFFSET 0x80
#define GET_COMMAND_PACKET_FRAG_THRESHOLD(v) (4*(v/4) - 8 )
typedef enum _firmware_init_step{
FW_INIT_STEP0_BOOT = 0,
FW_INIT_STEP1_MAIN = 1,
FW_INIT_STEP2_DATA = 2,
}firmware_init_step_e;
typedef enum _opt_rst_type{
OPT_SYSTEM_RESET = 0,
OPT_FIRMWARE_RESET = 1,
}opt_rst_type_e;
typedef enum _desc_packet_type_e{
DESC_PACKET_TYPE_INIT = 0,
DESC_PACKET_TYPE_NORMAL = 1,
}desc_packet_type_e;
typedef enum _firmware_source{
FW_SOURCE_IMG_FILE = 0,
FW_SOURCE_HEADER_FILE = 1,
}firmware_source_e, *pfirmware_source_e;
typedef enum _firmware_status{
FW_STATUS_0_INIT = 0,
FW_STATUS_1_MOVE_BOOT_CODE = 1,
FW_STATUS_2_MOVE_MAIN_CODE = 2,
FW_STATUS_3_TURNON_CPU = 3,
FW_STATUS_4_MOVE_DATA_CODE = 4,
FW_STATUS_5_READY = 5,
}firmware_status_e;
typedef struct _rt_firmare_seg_container {
u16 seg_size;
u8 *seg_ptr;
}fw_seg_container, *pfw_seg_container;
typedef struct _rt_firmware{
firmware_status_e firmware_status;
u16 cmdpacket_frag_thresold;
#define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000
#define MAX_FW_INIT_STEP 3
u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
u16 firmware_buf_size[MAX_FW_INIT_STEP];
} rt_firmware, *prt_firmware;
bool init_firmware(struct net_device *dev);
extern void firmware_init_param(struct net_device *dev);
#endif
drivers/staging/rtl8192e/r8192E_hw.h
View file @ a813833d
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_hwimg.c 0 → 100644
View file @ a813833d
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drivers/staging/rtl8192e/r8192E_hwimg.h 0 → 100644
View file @ a813833d
/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef __INC_HAL8192PciE_FW_IMG_H
#define __INC_HAL8192PciE_FW_IMG_H
/*Created on 2008/11/18, 3: 7*/
#include <linux/types.h>
#define BootArrayLengthPciE 344
extern u8 Rtl8192PciEFwBootArray[BootArrayLengthPciE];
#define MainArrayLengthPciE 43012
extern u8 Rtl8192PciEFwMainArray[MainArrayLengthPciE];
#define DataArrayLengthPciE 848
extern u8 Rtl8192PciEFwDataArray[DataArrayLengthPciE];
#define PHY_REGArrayLengthPciE 1
extern u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLengthPciE];
#define PHY_REG_1T2RArrayLengthPciE 296
extern u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLengthPciE];
#define RadioA_ArrayLengthPciE 246
extern u32 Rtl8192PciERadioA_Array[RadioA_ArrayLengthPciE] ;
#define RadioB_ArrayLengthPciE 78
extern u32 Rtl8192PciERadioB_Array[RadioB_ArrayLengthPciE] ;
#define RadioC_ArrayLengthPciE 2
extern u32 Rtl8192PciERadioC_Array[RadioC_ArrayLengthPciE] ;
#define RadioD_ArrayLengthPciE 2
extern u32 Rtl8192PciERadioD_Array[RadioD_ArrayLengthPciE] ;
#define MACPHY_ArrayLengthPciE 18
extern u32 Rtl8192PciEMACPHY_Array[MACPHY_ArrayLengthPciE] ;
#define MACPHY_Array_PGLengthPciE 30
extern u32 Rtl8192PciEMACPHY_Array_PG[MACPHY_Array_PGLengthPciE] ;
#define AGCTAB_ArrayLengthPciE 384
extern u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLengthPciE] ;
#endif
drivers/staging/rtl8192e/r8192E_phy.c 0 → 100644
View file @ a813833d
This diff is collapsed.
drivers/staging/rtl8192e/r8192E_phy.h 0 → 100644
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/******************************************************************************
* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
******************************************************************************/
#ifndef _R819XU_PHY_H
#define _R819XU_PHY_H
#define MAX_DOZE_WAITING_TIMES_9x 64
#define MAX_PRECMD_CNT 16
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
#define RadioA_ArrayLength RadioA_ArrayLengthPciE
#define RadioB_ArrayLength RadioB_ArrayLengthPciE
#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
#define RadioC_ArrayLength RadioC_ArrayLengthPciE
#define RadioD_ArrayLength RadioD_ArrayLengthPciE
#define PHY_REGArrayLength PHY_REGArrayLengthPciE
#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
typedef enum _SwChnlCmdID {
CmdID_End,
CmdID_SetTxPowerLevel,
CmdID_BBRegWrite10,
CmdID_WritePortUlong,
CmdID_WritePortUshort,
CmdID_WritePortUchar,
CmdID_RF_WriteReg,
} SwChnlCmdID;
/*--------------------------------Define structure--------------------------------*/
typedef struct _SwChnlCmd {
SwChnlCmdID CmdID;
u32 Para1;
u32 Para2;
u32 msDelay;
} __attribute__ ((packed)) SwChnlCmd;
extern u32 rtl819XMACPHY_Array_PG[];
extern u32 rtl819XPHY_REG_1T2RArray[];
extern u32 rtl819XAGCTAB_Array[];
extern u32 rtl819XRadioA_Array[];
extern u32 rtl819XRadioB_Array[];
extern u32 rtl819XRadioC_Array[];
extern u32 rtl819XRadioD_Array[];
typedef enum _HW90_BLOCK {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4,
} HW90_BLOCK_E, *PHW90_BLOCK_E;
typedef enum _RF90_RADIO_PATH{
RF90_PATH_A = 0,
RF90_PATH_B = 1,
RF90_PATH_C = 2,
RF90_PATH_D = 3,
RF90_PATH_MAX
}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
#define bMaskByte0 0xff
#define bMaskByte1 0xff00
#define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000
#define bMaskHWord 0xffff0000
#define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff
extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
extern void rtl8192_phy_configmac(struct net_device* dev);
extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
extern bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
extern bool rtl8192_BBConfig(struct net_device* dev);
extern void rtl8192_phy_getTxPower(struct net_device* dev);
extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
extern bool rtl8192_phy_RFConfig(struct net_device* dev);
extern void rtl8192_phy_updateInitGain(struct net_device* dev);
extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath);
extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
extern void PHY_SetRtl8192eRfOff(struct net_device *dev);
bool
SetRFPowerState(
struct net_device* dev,
RT_RF_POWER_STATE eRFPowerState
);
#define PHY_SetRFPowerState SetRFPowerState
extern void PHY_ScanOperationBackup8192(struct net_device* dev,u8 Operation);
#endif
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drivers/staging/usbip/userspace/src/utils.h
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......@@ -22,3 +22,4 @@
int modify_match_busid(char *busid, int add);
#endif /* __UTILS_H */
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