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Commit a8d9a13d authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915/dvo: Parametrize DVO/DVO_SRCDIM registers 

Get rid of the dvo_reg/dvo_srcdim_reg stuff by parametrizing
the DVO port registers.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221122120825.26338-5-ville.syrjala@linux.intel.comReviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent bf590368
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Showing with 37 additions and 54 deletions
drivers/gpu/drm/i915/display/intel_dvo.c
View file @ a8d9a13d
...@@ -56,48 +56,42 @@ static const struct intel_dvo_device intel_dvo_devices[] = { ...@@ -56,48 +56,42 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
{ {
.type = INTEL_DVO_CHIP_TMDS, .type = INTEL_DVO_CHIP_TMDS,
.name = "sil164", .name = "sil164",
.dvo_reg = DVOC, .port = PORT_C,
.dvo_srcdim_reg = DVOC_SRCDIM,
.slave_addr = SIL164_ADDR, .slave_addr = SIL164_ADDR,
.dev_ops = &sil164_ops, .dev_ops = &sil164_ops,
}, },
{ {
.type = INTEL_DVO_CHIP_TMDS, .type = INTEL_DVO_CHIP_TMDS,
.name = "ch7xxx", .name = "ch7xxx",
.dvo_reg = DVOC, .port = PORT_C,
.dvo_srcdim_reg = DVOC_SRCDIM,
.slave_addr = CH7xxx_ADDR, .slave_addr = CH7xxx_ADDR,
.dev_ops = &ch7xxx_ops, .dev_ops = &ch7xxx_ops,
}, },
{ {
.type = INTEL_DVO_CHIP_TMDS, .type = INTEL_DVO_CHIP_TMDS,
.name = "ch7xxx", .name = "ch7xxx",
.dvo_reg = DVOC, .port = PORT_C,
.dvo_srcdim_reg = DVOC_SRCDIM,
.slave_addr = 0x75, /* For some ch7010 */ .slave_addr = 0x75, /* For some ch7010 */
.dev_ops = &ch7xxx_ops, .dev_ops = &ch7xxx_ops,
}, },
{ {
.type = INTEL_DVO_CHIP_LVDS, .type = INTEL_DVO_CHIP_LVDS,
.name = "ivch", .name = "ivch",
.dvo_reg = DVOA, .port = PORT_A,
.dvo_srcdim_reg = DVOA_SRCDIM,
.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
.dev_ops = &ivch_ops, .dev_ops = &ivch_ops,
}, },
{ {
.type = INTEL_DVO_CHIP_TMDS, .type = INTEL_DVO_CHIP_TMDS,
.name = "tfp410", .name = "tfp410",
.dvo_reg = DVOC, .port = PORT_C,
.dvo_srcdim_reg = DVOC_SRCDIM,
.slave_addr = TFP410_ADDR, .slave_addr = TFP410_ADDR,
.dev_ops = &tfp410_ops, .dev_ops = &tfp410_ops,
}, },
{ {
.type = INTEL_DVO_CHIP_LVDS, .type = INTEL_DVO_CHIP_LVDS,
.name = "ch7017", .name = "ch7017",
.dvo_reg = DVOC, .port = PORT_C,
.dvo_srcdim_reg = DVOC_SRCDIM,
.slave_addr = 0x75, .slave_addr = 0x75,
.gpio = GMBUS_PIN_DPB, .gpio = GMBUS_PIN_DPB,
.dev_ops = &ch7017_ops, .dev_ops = &ch7017_ops,
...@@ -105,8 +99,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = { ...@@ -105,8 +99,7 @@ static const struct intel_dvo_device intel_dvo_devices[] = {
{ {
.type = INTEL_DVO_CHIP_LVDS_NO_FIXED, .type = INTEL_DVO_CHIP_LVDS_NO_FIXED,
.name = "ns2501", .name = "ns2501",
.dvo_reg = DVOB, .port = PORT_B,
.dvo_srcdim_reg = DVOB_SRCDIM,
.slave_addr = NS2501_ADDR, .slave_addr = NS2501_ADDR,
.dev_ops = &ns2501_ops, .dev_ops = &ns2501_ops,
}, },
...@@ -133,10 +126,12 @@ static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector) ...@@ -133,10 +126,12 @@ static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector)
static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{ {
struct drm_i915_private *i915 = to_i915(connector->base.dev); struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_dvo *intel_dvo = intel_attached_dvo(connector); struct intel_encoder *encoder = intel_attached_encoder(connector);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
enum port port = encoder->port;
u32 tmp; u32 tmp;
tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg); tmp = intel_de_read(i915, DVO(port));
if (!(tmp & DVO_ENABLE)) if (!(tmp & DVO_ENABLE))
return false; return false;
...@@ -148,10 +143,10 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, ...@@ -148,10 +143,10 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe) enum pipe *pipe)
{ {
struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder); enum port port = encoder->port;
u32 tmp; u32 tmp;
tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg); tmp = intel_de_read(i915, DVO(port));
*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT; *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
...@@ -162,12 +157,12 @@ static void intel_dvo_get_config(struct intel_encoder *encoder, ...@@ -162,12 +157,12 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config) struct intel_crtc_state *pipe_config)
{ {
struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder); enum port port = encoder->port;
u32 tmp, flags = 0; u32 tmp, flags = 0;
pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);
tmp = intel_de_read(i915, intel_dvo->dev.dvo_reg); tmp = intel_de_read(i915, DVO(port));
if (tmp & DVO_HSYNC_ACTIVE_HIGH) if (tmp & DVO_HSYNC_ACTIVE_HIGH)
flags |= DRM_MODE_FLAG_PHSYNC; flags |= DRM_MODE_FLAG_PHSYNC;
else else
...@@ -189,12 +184,12 @@ static void intel_disable_dvo(struct intel_atomic_state *state, ...@@ -189,12 +184,12 @@ static void intel_disable_dvo(struct intel_atomic_state *state,
{ {
struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder); struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; enum port port = encoder->port;
u32 temp = intel_de_read(i915, dvo_reg); u32 temp = intel_de_read(i915, DVO(port));
intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
intel_de_write(i915, dvo_reg, temp & ~DVO_ENABLE); intel_de_write(i915, DVO(port), temp & ~DVO_ENABLE);
intel_de_read(i915, dvo_reg); intel_de_read(i915, DVO(port));
} }
static void intel_enable_dvo(struct intel_atomic_state *state, static void intel_enable_dvo(struct intel_atomic_state *state,
...@@ -204,15 +199,15 @@ static void intel_enable_dvo(struct intel_atomic_state *state, ...@@ -204,15 +199,15 @@ static void intel_enable_dvo(struct intel_atomic_state *state,
{ {
struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dvo *intel_dvo = enc_to_dvo(encoder); struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; enum port port = encoder->port;
u32 temp = intel_de_read(i915, dvo_reg); u32 temp = intel_de_read(i915, DVO(port));
intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
&pipe_config->hw.mode, &pipe_config->hw.mode,
&pipe_config->hw.adjusted_mode); &pipe_config->hw.adjusted_mode);
intel_de_write(i915, dvo_reg, temp | DVO_ENABLE); intel_de_write(i915, DVO(port), temp | DVO_ENABLE);
intel_de_read(i915, dvo_reg); intel_de_read(i915, DVO(port));
intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
} }
...@@ -289,14 +284,12 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state, ...@@ -289,14 +284,12 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct intel_dvo *intel_dvo = enc_to_dvo(encoder); enum port port = encoder->port;
enum pipe pipe = crtc->pipe; enum pipe pipe = crtc->pipe;
u32 dvo_val; u32 dvo_val;
i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
/* Save the data order, since I don't know what it should be set to. */ /* Save the data order, since I don't know what it should be set to. */
dvo_val = intel_de_read(i915, dvo_reg) & dvo_val = intel_de_read(i915, DVO(port)) &
(DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
DVO_BLANK_ACTIVE_HIGH; DVO_BLANK_ACTIVE_HIGH;
...@@ -308,9 +301,9 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state, ...@@ -308,9 +301,9 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
dvo_val |= DVO_VSYNC_ACTIVE_HIGH; dvo_val |= DVO_VSYNC_ACTIVE_HIGH;
intel_de_write(i915, dvo_srcdim_reg, intel_de_write(i915, DVO_SRCDIM(port),
(adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
intel_de_write(i915, dvo_reg, dvo_val); intel_de_write(i915, DVO(port), dvo_val);
} }
static enum drm_connector_status static enum drm_connector_status
...@@ -378,16 +371,6 @@ static const struct drm_encoder_funcs intel_dvo_enc_funcs = { ...@@ -378,16 +371,6 @@ static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
.destroy = intel_dvo_enc_destroy, .destroy = intel_dvo_enc_destroy,
}; };
static enum port intel_dvo_port(i915_reg_t dvo_reg)
{
if (i915_mmio_reg_equal(dvo_reg, DVOA))
return PORT_A;
else if (i915_mmio_reg_equal(dvo_reg, DVOB))
return PORT_B;
else
return PORT_C;
}
static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo) static int intel_dvo_encoder_type(const struct intel_dvo_device *dvo)
{ {
switch (dvo->type) { switch (dvo->type) {
...@@ -528,7 +511,7 @@ void intel_dvo_init(struct drm_i915_private *i915) ...@@ -528,7 +511,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
encoder->type = INTEL_OUTPUT_DVO; encoder->type = INTEL_OUTPUT_DVO;
encoder->power_domain = POWER_DOMAIN_PORT_OTHER; encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
encoder->port = intel_dvo_port(intel_dvo->dev.dvo_reg); encoder->port = intel_dvo->dev.port;
encoder->pipe_mask = ~0; encoder->pipe_mask = ~0;
if (intel_dvo->dev.type != INTEL_DVO_CHIP_LVDS) if (intel_dvo->dev.type != INTEL_DVO_CHIP_LVDS)
......
drivers/gpu/drm/i915/display/intel_dvo_dev.h
View file @ a8d9a13d
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
#include "i915_reg_defs.h" #include "i915_reg_defs.h"
#include "intel_display.h"
enum drm_connector_status; enum drm_connector_status;
struct drm_display_mode; struct drm_display_mode;
struct i2c_adapter; struct i2c_adapter;
...@@ -32,9 +34,8 @@ struct i2c_adapter; ...@@ -32,9 +34,8 @@ struct i2c_adapter;
struct intel_dvo_device { struct intel_dvo_device {
const char *name; const char *name;
int type; int type;
/* DVOA/B/C output register */ /* DVOA/B/C */
i915_reg_t dvo_reg; enum port port;
i915_reg_t dvo_srcdim_reg;
/* GPIO register used for i2c bus to control this device */ /* GPIO register used for i2c bus to control this device */
u32 gpio; u32 gpio;
int slave_addr; int slave_addr;
......
drivers/gpu/drm/i915/i915_reg.h
View file @ a8d9a13d
...@@ -2591,11 +2591,9 @@ ...@@ -2591,11 +2591,9 @@
/* DVO port control */ /* DVO port control */
#define _DVOA 0x61120 #define _DVOA 0x61120
#define DVOA _MMIO(_DVOA)
#define _DVOB 0x61140 #define _DVOB 0x61140
#define DVOB _MMIO(_DVOB)
#define _DVOC 0x61160 #define _DVOC 0x61160
#define DVOC _MMIO(_DVOC) #define DVO(port) _MMIO_PORT((port), _DVOA, _DVOB)
#define DVO_ENABLE (1 << 31) #define DVO_ENABLE (1 << 31)
#define DVO_PIPE_SEL_SHIFT 30 #define DVO_PIPE_SEL_SHIFT 30
#define DVO_PIPE_SEL_MASK (1 << 30) #define DVO_PIPE_SEL_MASK (1 << 30)
...@@ -2622,9 +2620,10 @@ ...@@ -2622,9 +2620,10 @@
#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */ #define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */ #define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
#define DVO_PRESERVE_MASK (0x7 << 24) #define DVO_PRESERVE_MASK (0x7 << 24)
#define DVOA_SRCDIM _MMIO(0x61124) #define _DVOA_SRCDIM 0x61124
#define DVOB_SRCDIM _MMIO(0x61144) #define _DVOB_SRCDIM 0x61144
#define DVOC_SRCDIM _MMIO(0x61164) #define _DVOC_SRCDIM 0x61164
#define DVO_SRCDIM(port) _MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM)
#define DVO_SRCDIM_HORIZONTAL_SHIFT 12 #define DVO_SRCDIM_HORIZONTAL_SHIFT 12
#define DVO_SRCDIM_VERTICAL_SHIFT 0 #define DVO_SRCDIM_VERTICAL_SHIFT 0
......
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