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Commit a8e8e491 authored by Mike Frysinger's avatar Mike Frysinger
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Blackfin: unify duplicated power masks 

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 761ec44a
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Showing with 104 additions and 459 deletions
arch/blackfin/include/asm/dpmc.h
View file @ a8e8e491
/*
* Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
*
* Copyright (C) 2004-2008 Analog Device Inc.
* Copyright (C) 2004-2009 Analog Device Inc.
*
* Licensed under the GPL-2
*/
......@@ -9,7 +9,109 @@
#ifndef _BLACKFIN_DPMC_H_
#define _BLACKFIN_DPMC_H_
#ifdef __KERNEL__
/* PLL_CTL Masks */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* PLL Not Powered */
#define STOPCK 0x0008 /* Core Clock Off */
#define PDWN 0x0020 /* Enter Deep Sleep Mode */
#ifdef __ADSPBF539__
# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
#else
# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
#endif
#define BYPASS 0x0100 /* Bypass the PLL */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
#define CCLK_DIV1 CSEL_DIV1
#define CCLK_DIV2 CSEL_DIV2
#define CCLK_DIV4 CSEL_DIV4
#define CCLK_DIV8 CSEL_DIV8
#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
#define CANWS 0x0800 /* CAN Wake-Up Status */
#define USBWS 0x2000 /* USB Wake-Up Status */
#define KPADWS 0x4000 /* Keypad Wake-Up Status */
#define ROTWS 0x8000 /* Rotary Wake-Up Status */
#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
/* VR_CTL Masks */
#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
#else
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#endif
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5 */
#define GAIN_10 0x0004 /* GAIN = 1 */
#define GAIN_20 0x0008 /* GAIN = 2 */
#define GAIN_50 0x000C /* GAIN = 5 */
#define VLEV 0x00F0 /* Internal Voltage Level */
#ifdef __ADSPBF52x__
#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#else
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#endif
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
#else
#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
#endif
#ifndef __ASSEMBLY__
void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
......@@ -54,6 +156,5 @@ struct bfin_dpmc_platform_data {
w[P0 + (x - PLL_CTL)] = R0;\
#endif
#endif /* __KERNEL__ */
#endif /*_BLACKFIN_DPMC_H_*/
arch/blackfin/mach-bf518/include/mach/blackfin.h
View file @ a8e8e491
......@@ -58,10 +58,4 @@
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
#endif
arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
View file @ a8e8e491
......@@ -585,58 +585,6 @@
** modifier UNLESS the lower order bits are saved and ORed back in when
** the macro is used.
*************************************************************************************/
/*
** ********************* PLL AND RESET MASKS ****************************************/
/* PLL_CTL Masks */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* PLL Not Powered */
#define STOPCK 0x0008 /* Core Clock Off */
#define PDWN 0x0020 /* Enter Deep Sleep Mode */
#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
#define BYPASS 0x0100 /* Bypass the PLL */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
/* VR_CTL Masks */
#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* CHIPID Masks */
#define CHIPID_VERSION 0xF0000000
......
arch/blackfin/mach-bf527/include/mach/blackfin.h
View file @ a8e8e491
......@@ -46,10 +46,4 @@
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
#endif
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View file @ a8e8e491
......@@ -586,58 +586,6 @@
** modifier UNLESS the lower order bits are saved and ORed back in when
** the macro is used.
*************************************************************************************/
/*
** ********************* PLL AND RESET MASKS ****************************************/
/* PLL_CTL Masks */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* PLL Not Powered */
#define STOPCK 0x0008 /* Core Clock Off */
#define PDWN 0x0020 /* Enter Deep Sleep Mode */
#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
#define BYPASS 0x0100 /* Bypass the PLL */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
/* VR_CTL Masks */
#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* CHIPID Masks */
#define CHIPID_VERSION 0xF0000000
......
arch/blackfin/mach-bf533/include/mach/defBF532.h
View file @ a8e8e491
......@@ -370,72 +370,6 @@
/* System MMR Register Bits */
/******************************************************************************* */
/* ********************* PLL AND RESET MASKS ************************ */
/* PLL_CTL Masks */
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
#define STOPCK_OFF 0x0008 /* Core clock off */
#define STOPCK 0x0008 /* Core Clock Off */
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
#if !defined(__ADSPBF538__)
/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
#endif
#define BYPASS 0x0100 /* Bypass the PLL */
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5 */
#define GAIN_10 0x0004 /* GAIN = 10 */
#define GAIN_20 0x0008 /* GAIN = 20 */
#define GAIN_50 0x000C /* GAIN = 50 */
#define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
/* CHIPID Masks */
#define CHIPID_VERSION 0xF0000000
#define CHIPID_FAMILY 0x0FFFF000
......
arch/blackfin/mach-bf537/include/mach/blackfin.h
View file @ a8e8e491
......@@ -40,10 +40,4 @@
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
#endif
arch/blackfin/mach-bf537/include/mach/defBF534.h
View file @ a8e8e491
......@@ -958,67 +958,6 @@
** modifier UNLESS the lower order bits are saved and ORed back in when
** the macro is used.
*************************************************************************************/
/*
** ********************* PLL AND RESET MASKS ****************************************/
/* PLL_CTL Masks */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* PLL Not Powered */
#define STOPCK 0x0008 /* Core Clock Off */
#define PDWN 0x0020 /* Enter Deep Sleep Mode */
#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
#define BYPASS 0x0100 /* Bypass the PLL */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* PLL_DIV Macros */
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5 */
#define GAIN_10 0x0004 /* GAIN = 10 */
#define GAIN_20 0x0008 /* GAIN = 20 */
#define GAIN_50 0x000C /* GAIN = 50 */
#define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* CHIPID Masks */
#define CHIPID_VERSION 0xF0000000
......
arch/blackfin/mach-bf538/include/mach/blackfin.h
View file @ a8e8e491
......@@ -37,10 +37,4 @@
#define OFFSET_SCR 0x1C /* SCR Scratch Register */
#define OFFSET_GCTL 0x24 /* Global Control Register */
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
#endif
arch/blackfin/mach-bf538/include/mach/defBF539.h
View file @ a8e8e491
......@@ -1422,81 +1422,6 @@
/* System MMR Register Bits and Macros */
/******************************************************************************* */
/* ********************* PLL AND RESET MASKS ************************ */
/* PLL_CTL Masks */
#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define PLL_OFF 0x0002 /* Shut off PLL clocks */
#define STOPCK 0x0008 /* Core Clock Off */
#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
#define BYPASS 0x0100 /* Bypass the PLL */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
/* PLL_CTL Macros */
#ifdef _MISRA_RULES
#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6)
#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
#else
#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
#endif /* _MISRA_RULES */
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
/* PLL_DIV Macros */
#ifdef _MISRA_RULES
#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
#else
#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
#endif /* _MISRA_RULES */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5 */
#define GAIN_10 0x0004 /* GAIN = 10 */
#define GAIN_20 0x0008 /* GAIN = 20 */
#define GAIN_50 0x000C /* GAIN = 50 */
#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
/* SWRST Mask */
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
......
arch/blackfin/mach-bf548/include/mach/blackfin.h
View file @ a8e8e491
......@@ -64,10 +64,4 @@
#define OFFSET_THR 0x28 /* Transmit Holding register */
#define OFFSET_RBR 0x2C /* Receive Buffer register */
/* PLL_DIV Masks */
#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
#endif
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
View file @ a8e8e491
......@@ -2075,26 +2075,6 @@
#define AFEXIT 0x10 /* Authentication Firmware Exit */
#define SECSTAT 0xe0 /* Secure Status */
/* Bit masks for PLL_DIV */
#define CSEL 0x30 /* Core Select */
#define SSEL 0xf /* System Select */
#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
/* Bit masks for PLL_CTL */
#define MSEL 0x7e00 /* Multiplier Select */
#define BYPASS 0x100 /* PLL Bypass Enable */
#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
#define PDWN 0x20 /* Power Down */
#define STOPCK 0x8 /* Stop Clock */
#define PLL_OFF 0x2 /* Disable PLL */
#define DF 0x1 /* Divide Frequency */
/* SWRST Masks */
#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
......@@ -2102,52 +2082,6 @@
#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* Bit masks for PLL_STAT */
#define PLL_LOCKED 0x20 /* PLL Locked Status */
#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
#define FULL_ON 0x2 /* Full-On Mode */
#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
#define CANWS 0x800 /* CAN Wake-Up Status */
#define USBWS 0x2000 /* USB Wake-Up Status */
#define KPADWS 0x4000 /* Keypad Wake-Up Status */
#define ROTWS 0x8000 /* Rotary Wake-Up Status */
#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
/* Bit masks for VR_CTL */
#define FREQ 0x3 /* Regulator Switching Frequency */
#define GAIN 0xc /* Voltage Output Level Gain */
#define VLEV 0xf0 /* Internal Voltage Level */
#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
#define USBWE 0x800 /* USB Wake-Up Enable */
#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN_5 0x0000 /* GAIN = 5*/
#define GAIN_10 0x0004 /* GAIN = 1*/
#define GAIN_20 0x0008 /* GAIN = 2*/
#define GAIN_50 0x000C /* GAIN = 5*/
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
/* Bit masks for NFC_CTL */
#define WR_DLY 0xf /* Write Strobe Delay */
......
arch/blackfin/mach-bf561/include/mach/defBF561.h
View file @ a8e8e491
......@@ -884,65 +884,11 @@
/* System MMR Register Bits */
/******************************************************************************* */
/* ********************* PLL AND RESET MASKS ************************ */
/* PLL_CTL Masks */
#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
#define STOPCK_OFF 0x00000008 /* Core clock off */
#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
#define BYPASS 0x00000100 /* Bypass the PLL */
/* CHIPID Masks */
#define CHIPID_VERSION 0xF0000000
#define CHIPID_FAMILY 0x0FFFF000
#define CHIPID_MANUFACTURE 0x00000FFE
/* VR_CTL Masks */
#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
#define GAIN 0x000C /* Voltage Level Gain */
#define GAIN_5 0x0000 /* GAIN = 5*/
#define GAIN_10 0x0004 /* GAIN = 1*/
#define GAIN_20 0x0008 /* GAIN = 2*/
#define GAIN_50 0x000C /* GAIN = 5*/
#define VLEV 0x00F0 /* Internal Voltage Level */
#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
/* PLL_DIV Masks */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
#define CSEL 0x30 /* Core Select */
#define SSEL 0xf /* System Select */
#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
/* SICA_SYSCR Masks */
#define COREB_SRAM_INIT 0x0020
......
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