[PATCH] ppc/ppc64: Fix g5 access to PCI IO cycles

Looks like we never needed them, since that bug has been there forever,
I didn't get the right base for the IO cycles on the G5 host bridge
in the first place (I probably misinterpreted some OF forth code or
something like that).

arch/ppc/platforms/pmac_pci.c

@@ -716,7 +716,7 @@ setup_u3_ht(struct pci_controller* hose, struct reg_property *addr)
 	 * properties or figuring out the U3 address space decoding logic and
 	 * then read its configuration register (if any).
 	 */
-	hose->io_base_phys = 0xf4000000 + 0x00400000;
+	hose->io_base_phys = 0xf4000000;
 	hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
 	isa_io_base = (unsigned long) hose->io_base_virt;
 	hose->io_resource.name = np->full_name;

arch/ppc64/kernel/pmac_pci.c

@@ -419,7 +419,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
 	 * properties or figuring out the U3 address space decoding logic and
 	 * then read it's configuration register (if any).
 	 */
-	hose->io_base_phys = 0xf4000000 + 0x00400000;
+	hose->io_base_phys = 0xf4000000;
 	hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
 	isa_io_base = pci_io_base = (unsigned long) hose->io_base_virt;
 	hose->io_resource.name = np->full_name;