Commit aa400ae5 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Ralf Baechle

MIPS: GT641xx: Convert to new irq_chip functions

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2187/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 161d049e
...@@ -29,64 +29,64 @@ ...@@ -29,64 +29,64 @@
static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock); static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
static void ack_gt641xx_irq(unsigned int irq) static void ack_gt641xx_irq(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
u32 cause; u32 cause;
raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
cause = GT_READ(GT_INTRCAUSE_OFS); cause = GT_READ(GT_INTRCAUSE_OFS);
cause &= ~GT641XX_IRQ_TO_BIT(irq); cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRCAUSE_OFS, cause); GT_WRITE(GT_INTRCAUSE_OFS, cause);
raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
} }
static void mask_gt641xx_irq(unsigned int irq) static void mask_gt641xx_irq(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
u32 mask; u32 mask;
raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
mask = GT_READ(GT_INTRMASK_OFS); mask = GT_READ(GT_INTRMASK_OFS);
mask &= ~GT641XX_IRQ_TO_BIT(irq); mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRMASK_OFS, mask); GT_WRITE(GT_INTRMASK_OFS, mask);
raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
} }
static void mask_ack_gt641xx_irq(unsigned int irq) static void mask_ack_gt641xx_irq(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
u32 cause, mask; u32 cause, mask;
raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
mask = GT_READ(GT_INTRMASK_OFS); mask = GT_READ(GT_INTRMASK_OFS);
mask &= ~GT641XX_IRQ_TO_BIT(irq); mask &= ~GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRMASK_OFS, mask); GT_WRITE(GT_INTRMASK_OFS, mask);
cause = GT_READ(GT_INTRCAUSE_OFS); cause = GT_READ(GT_INTRCAUSE_OFS);
cause &= ~GT641XX_IRQ_TO_BIT(irq); cause &= ~GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRCAUSE_OFS, cause); GT_WRITE(GT_INTRCAUSE_OFS, cause);
raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
} }
static void unmask_gt641xx_irq(unsigned int irq) static void unmask_gt641xx_irq(struct irq_data *d)
{ {
unsigned long flags; unsigned long flags;
u32 mask; u32 mask;
raw_spin_lock_irqsave(&gt641xx_irq_lock, flags); raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
mask = GT_READ(GT_INTRMASK_OFS); mask = GT_READ(GT_INTRMASK_OFS);
mask |= GT641XX_IRQ_TO_BIT(irq); mask |= GT641XX_IRQ_TO_BIT(d->irq);
GT_WRITE(GT_INTRMASK_OFS, mask); GT_WRITE(GT_INTRMASK_OFS, mask);
raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags); raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
} }
static struct irq_chip gt641xx_irq_chip = { static struct irq_chip gt641xx_irq_chip = {
.name = "GT641xx", .name = "GT641xx",
.ack = ack_gt641xx_irq, .irq_ack = ack_gt641xx_irq,
.mask = mask_gt641xx_irq, .irq_mask = mask_gt641xx_irq,
.mask_ack = mask_ack_gt641xx_irq, .irq_mask_ack = mask_ack_gt641xx_irq,
.unmask = unmask_gt641xx_irq, .irq_unmask = unmask_gt641xx_irq,
}; };
void gt641xx_irq_dispatch(void) void gt641xx_irq_dispatch(void)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment