Commit aa4c2fdf authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman

ARM: dts: r8a7790: Add missing clocks for secondary CA15 CPU cores

Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU cores are driven by the same clock.
Add the missing clocks properties to fix this.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent fa9f95a3
......@@ -72,6 +72,7 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
......@@ -82,6 +83,7 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a15";
reg = <2>;
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
......@@ -92,6 +94,7 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a15";
reg = <3>;
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
......
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