Commit aa5fec2d authored by Cory Tusar's avatar Cory Tusar Committed by Shawn Guo

ARM: dts: vf610: Nomenclature fixup for PTC12 pin used in RMII mode.

This commit includes a minor nomenclature fixup for boards based on the
Freescale VF610 SoC and which make use of the alternate "RMII1_RXD1"
functionality for pin PTC12.  This brings the macro name in-line with
both the datasheet and other similar macros.
Signed-off-by: default avatarCory Tusar <cory.tusar@pid1solutions.com>
Acked-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent dca97cee
...@@ -140,7 +140,7 @@ VF610_PAD_PTA6__RMII_CLKOUT 0x30d2 ...@@ -140,7 +140,7 @@ VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
......
...@@ -68,7 +68,7 @@ pinctrl_fec1: fec1grp { ...@@ -68,7 +68,7 @@ pinctrl_fec1: fec1grp {
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
......
...@@ -369,7 +369,7 @@ ...@@ -369,7 +369,7 @@
#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1 #define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1
#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0 #define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0
#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0 #define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0
#define VF610_PAD_PTC12__ENET_RMII_RXD1 0x0E4 0x000 ALT1 0x0 #define VF610_PAD_PTC12__ENET_RMII1_RXD1 0x0E4 0x000 ALT1 0x0
#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1 #define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1
#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1 #define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1
#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0 #define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0
......
...@@ -221,7 +221,7 @@ pinctrl_fec1: fec1grp { ...@@ -221,7 +221,7 @@ pinctrl_fec1: fec1grp {
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
......
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