PPC32: Fix host bridge programming on Adirondack "K2" boards.

arch/ppc/platforms/k2_pci.c

@@ -156,6 +156,13 @@ void k2_setup_hoses(void)
 	__raw_writel(0x00000080, K2_PCI32_BAR+PSBAR);	/* Base@0x80 */
 	__raw_writel(0x00000000, K2_PCI32_BAR+PPBAR);
 
+	__raw_writel(0xc0000000, K2_PCI32_BAR+BPMDLK);
+	__raw_writel(0xd0000000, K2_PCI32_BAR+TPMDLK);
+	__raw_writel(0x80000000, K2_PCI32_BAR+BIODLK);
+	__raw_writel(0x80100000, K2_PCI32_BAR+TIODLK);
+	__raw_writel(0xe0008000, K2_PCI32_BAR+DLKCTRL);
+	__raw_writel(0xffffffff, K2_PCI32_BAR+DLKDEV);
+	
 	/* PCI64 mappings */
 	__raw_writel(0x00100000, K2_PCI64_BAR+PIBAR);	/* PCI I/O base */
 	__raw_writel(0x10000000, K2_PCI64_BAR+PMBAR);	/* PCI Mem base */

arch/ppc/syslib/cpc710.h

@@ -61,6 +61,12 @@
 #define BARPP	0x000f8130
 #define PSBAR	0x000f8140
 #define PPBAR	0x000f8150
+#define BPMDLK	0x000f8200      /* Bottom of Peripheral Memory Space */
+#define TPMDLK	0x000f8210      /* Top of Peripheral Memory Space */
+#define BIODLK	0x000f8220      /* Bottom of Peripheral I/O Space */
+#define TIODLK	0x000f8230      /* Top of Perioheral I/O Space */
+#define DLKCTRL	0x000f8240      /* Deadlock control */
+#define DLKDEV	0x000f8250      /* Deadlock device */
 
 /* System standard configuration registers space */
 #define	DCR	0xff200000