Commit af246cc6 authored by Yang Guo's avatar Yang Guo Committed by Daniel Lezcano

clocksource/drivers/arm_arch_timer: Fix CNTPCT_LO and CNTVCT_LO value

CNTPCT_LO and CNTVCT_LO are defined by mistake in commit '8b82c4f8',
so fix them according to the Arm ARM DDI 0487I.a, Table I2-4
"CNTBaseN memory map" as follows:

Offset    Register      Type Description
0x000     CNTPCT[31:0]  RO   Physical Count register.
0x004     CNTPCT[63:32] RO
0x008     CNTVCT[31:0]  RO   Virtual Count register.
0x00C     CNTVCT[63:32] RO

Fixes: 8b82c4f8 ("clocksource/drivers/arm_arch_timer: Move MMIO timer programming over to CVAL")
Cc: stable@vger.kernel.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Signed-off-by: default avatarYang Guo <guoyang2@huawei.com>
Signed-off-by: default avatarShaokun Zhang <zhangshaokun@hisilicon.com>
Link: https://lore.kernel.org/r/20220927033221.49589-1-zhangshaokun@hisilicon.comSigned-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 27b30995
......@@ -44,8 +44,8 @@
#define CNTACR_RWVT BIT(4)
#define CNTACR_RWPT BIT(5)
#define CNTVCT_LO 0x00
#define CNTPCT_LO 0x08
#define CNTPCT_LO 0x00
#define CNTVCT_LO 0x08
#define CNTFRQ 0x10
#define CNTP_CVAL_LO 0x20
#define CNTP_CTL 0x2c
......
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