Commit af3b89d3 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/smu11.0: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: rebase
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a8967967
...@@ -90,36 +90,37 @@ int smu_v11_0_init_microcode(struct smu_context *smu) ...@@ -90,36 +90,37 @@ int smu_v11_0_init_microcode(struct smu_context *smu)
struct amdgpu_firmware_info *ucode = NULL; struct amdgpu_firmware_info *ucode = NULL;
if (amdgpu_sriov_vf(adev) && if (amdgpu_sriov_vf(adev) &&
((adev->asic_type == CHIP_NAVI12) || ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) ||
(adev->asic_type == CHIP_SIENNA_CICHLID))) (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 7))))
return 0; return 0;
switch (adev->asic_type) { switch (adev->ip_versions[MP1_HWIP]) {
case CHIP_ARCTURUS: case IP_VERSION(11, 0, 0):
chip_name = "arcturus";
break;
case CHIP_NAVI10:
chip_name = "navi10"; chip_name = "navi10";
break; break;
case CHIP_NAVI14: case IP_VERSION(11, 0, 5):
chip_name = "navi14"; chip_name = "navi14";
break; break;
case CHIP_NAVI12: case IP_VERSION(11, 0, 9):
chip_name = "navi12"; chip_name = "navi12";
break; break;
case CHIP_SIENNA_CICHLID: case IP_VERSION(11, 0, 7):
chip_name = "sienna_cichlid"; chip_name = "sienna_cichlid";
break; break;
case CHIP_NAVY_FLOUNDER: case IP_VERSION(11, 0, 11):
chip_name = "navy_flounder"; chip_name = "navy_flounder";
break; break;
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(11, 0, 12):
chip_name = "dimgrey_cavefish"; chip_name = "dimgrey_cavefish";
break; break;
case CHIP_BEIGE_GOBY: case IP_VERSION(11, 0, 13):
chip_name = "beige_goby"; chip_name = "beige_goby";
break; break;
default: default:
if (adev->asic_type == CHIP_ARCTURUS) {
chip_name = "arcturus";
break;
}
dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type); dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
return -EINVAL; return -EINVAL;
} }
...@@ -238,38 +239,39 @@ int smu_v11_0_check_fw_version(struct smu_context *smu) ...@@ -238,38 +239,39 @@ int smu_v11_0_check_fw_version(struct smu_context *smu)
if (smu->is_apu) if (smu->is_apu)
adev->pm.fw_version = smu_version; adev->pm.fw_version = smu_version;
switch (smu->adev->asic_type) { switch (adev->ip_versions[MP1_HWIP]) {
case CHIP_ARCTURUS: case IP_VERSION(11, 0, 0):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
break;
case CHIP_NAVI10:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
break; break;
case CHIP_NAVI12: case IP_VERSION(11, 0, 9):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
break; break;
case CHIP_NAVI14: case IP_VERSION(11, 0, 5):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
break; break;
case CHIP_SIENNA_CICHLID: case IP_VERSION(11, 0, 7):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
break; break;
case CHIP_NAVY_FLOUNDER: case IP_VERSION(11, 0, 11):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
break; break;
case CHIP_VANGOGH: case CHIP_VANGOGH:
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
break; break;
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(11, 0, 12):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
break; break;
case CHIP_BEIGE_GOBY: case IP_VERSION(11, 0, 13):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
break; break;
case CHIP_CYAN_SKILLFISH: case IP_VERSION(11, 0, 8):
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
break; break;
default: default:
if (adev->asic_type == CHIP_ARCTURUS) {
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
break;
}
dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type); dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV; smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
break; break;
...@@ -492,8 +494,9 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu) ...@@ -492,8 +494,9 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu)
int smu_v11_0_init_power(struct smu_context *smu) int smu_v11_0_init_power(struct smu_context *smu)
{ {
struct amdgpu_device *adev = smu->adev;
struct smu_power_context *smu_power = &smu->smu_power; struct smu_power_context *smu_power = &smu->smu_power;
size_t size = smu->adev->asic_type == CHIP_VANGOGH ? size_t size = adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ?
sizeof(struct smu_11_5_power_context) : sizeof(struct smu_11_5_power_context) :
sizeof(struct smu_11_0_power_context); sizeof(struct smu_11_0_power_context);
...@@ -750,8 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) ...@@ -750,8 +753,9 @@ int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
/* Navy_Flounder/Dimgrey_Cavefish do not support to change /* Navy_Flounder/Dimgrey_Cavefish do not support to change
* display num currently * display num currently
*/ */
if (adev->asic_type >= CHIP_NAVY_FLOUNDER && if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 11) ||
adev->asic_type <= CHIP_BEIGE_GOBY) adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 5, 0) ||
adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 13))
return 0; return 0;
return smu_cmn_send_smc_msg_with_param(smu, return smu_cmn_send_smc_msg_with_param(smu,
...@@ -1136,15 +1140,15 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) ...@@ -1136,15 +1140,15 @@ int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
int ret = 0; int ret = 0;
struct amdgpu_device *adev = smu->adev; struct amdgpu_device *adev = smu->adev;
switch (adev->asic_type) { switch (adev->ip_versions[MP1_HWIP]) {
case CHIP_NAVI10: case IP_VERSION(11, 0, 0):
case CHIP_NAVI14: case IP_VERSION(11, 0, 5):
case CHIP_NAVI12: case IP_VERSION(11, 0, 9):
case CHIP_SIENNA_CICHLID: case IP_VERSION(11, 0, 7):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(11, 0, 11):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(11, 0, 12):
case CHIP_BEIGE_GOBY: case IP_VERSION(11, 0, 13):
case CHIP_VANGOGH: case IP_VERSION(11, 5, 0):
if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
return 0; return 0;
if (enable) if (enable)
...@@ -1630,11 +1634,11 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) ...@@ -1630,11 +1634,11 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
mutex_lock(&smu_baco->mutex); mutex_lock(&smu_baco->mutex);
if (state == SMU_BACO_STATE_ENTER) { if (state == SMU_BACO_STATE_ENTER) {
switch (adev->asic_type) { switch (adev->ip_versions[MP1_HWIP]) {
case CHIP_SIENNA_CICHLID: case IP_VERSION(11, 0, 7):
case CHIP_NAVY_FLOUNDER: case IP_VERSION(11, 0, 11):
case CHIP_DIMGREY_CAVEFISH: case IP_VERSION(11, 0, 12):
case CHIP_BEIGE_GOBY: case IP_VERSION(11, 0, 13):
if (amdgpu_runtime_pm == 2) if (amdgpu_runtime_pm == 2)
ret = smu_cmn_send_smc_msg_with_param(smu, ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_EnterBaco, SMU_MSG_EnterBaco,
......
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