Commit af696a61 authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau/flcn: reset sec2/gsp falcons harder

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent b826f48a
...@@ -19,4 +19,5 @@ int nvkm_falcon_v1_enable(struct nvkm_falcon *); ...@@ -19,4 +19,5 @@ int nvkm_falcon_v1_enable(struct nvkm_falcon *);
void nvkm_falcon_v1_disable(struct nvkm_falcon *); void nvkm_falcon_v1_disable(struct nvkm_falcon *);
void gp102_sec2_flcn_bind_context(struct nvkm_falcon *, struct nvkm_memory *); void gp102_sec2_flcn_bind_context(struct nvkm_falcon *, struct nvkm_memory *);
int gp102_sec2_flcn_enable(struct nvkm_falcon *);
#endif #endif
...@@ -92,6 +92,7 @@ struct nvkm_falcon_func { ...@@ -92,6 +92,7 @@ struct nvkm_falcon_func {
void (*start)(struct nvkm_falcon *); void (*start)(struct nvkm_falcon *);
int (*enable)(struct nvkm_falcon *falcon); int (*enable)(struct nvkm_falcon *falcon);
void (*disable)(struct nvkm_falcon *falcon); void (*disable)(struct nvkm_falcon *falcon);
int (*reset)(struct nvkm_falcon *);
struct { struct {
u32 head; u32 head;
......
...@@ -47,6 +47,15 @@ gp102_sec2_intr(struct nvkm_sec2 *sec2) ...@@ -47,6 +47,15 @@ gp102_sec2_intr(struct nvkm_sec2 *sec2)
} }
} }
int
gp102_sec2_flcn_enable(struct nvkm_falcon *falcon)
{
nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000001);
udelay(10);
nvkm_falcon_mask(falcon, 0x3c0, 0x00000001, 0x00000000);
return nvkm_falcon_v1_enable(falcon);
}
void void
gp102_sec2_flcn_bind_context(struct nvkm_falcon *falcon, gp102_sec2_flcn_bind_context(struct nvkm_falcon *falcon,
struct nvkm_memory *ctx) struct nvkm_memory *ctx)
...@@ -99,7 +108,7 @@ gp102_sec2_flcn = { ...@@ -99,7 +108,7 @@ gp102_sec2_flcn = {
.clear_interrupt = nvkm_falcon_v1_clear_interrupt, .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
.set_start_addr = nvkm_falcon_v1_set_start_addr, .set_start_addr = nvkm_falcon_v1_set_start_addr,
.start = nvkm_falcon_v1_start, .start = nvkm_falcon_v1_start,
.enable = nvkm_falcon_v1_enable, .enable = gp102_sec2_flcn_enable,
.disable = nvkm_falcon_v1_disable, .disable = nvkm_falcon_v1_disable,
.cmdq = { 0xa00, 0xa04, 8 }, .cmdq = { 0xa00, 0xa04, 8 },
.msgq = { 0xa30, 0xa34, 8 }, .msgq = { 0xa30, 0xa34, 8 },
......
...@@ -32,7 +32,7 @@ gv100_gsp_flcn = { ...@@ -32,7 +32,7 @@ gv100_gsp_flcn = {
.clear_interrupt = nvkm_falcon_v1_clear_interrupt, .clear_interrupt = nvkm_falcon_v1_clear_interrupt,
.set_start_addr = nvkm_falcon_v1_set_start_addr, .set_start_addr = nvkm_falcon_v1_set_start_addr,
.start = nvkm_falcon_v1_start, .start = nvkm_falcon_v1_start,
.enable = nvkm_falcon_v1_enable, .enable = gp102_sec2_flcn_enable,
.disable = nvkm_falcon_v1_disable, .disable = nvkm_falcon_v1_disable,
}; };
......
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