Commit b10eb2d5 authored by Hector Martin's avatar Hector Martin

asm-generic/io.h: implement pci_remap_cfgspace using ioremap_np

Now that we have ioremap_np(), we can make pci_remap_cfgspace() default
to it, falling back to ioremap() on platforms where it is not available.

Remove the arm64 implementation, since that is now redundant. Future
cleanups should be able to do the same for other arches, and eventually
make the generic pci_remap_cfgspace() unconditional.
Acked-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarHector Martin <marcan@marcan.st>
parent 9a63ae85
...@@ -171,16 +171,6 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); ...@@ -171,16 +171,6 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
#define ioremap_np(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE)) #define ioremap_np(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))
/*
* PCI configuration space mapping function.
*
* The PCI specification disallows posted write configuration transactions.
* Add an arch specific pci_remap_cfgspace() definition that is implemented
* through nGnRnE device memory attribute as recommended by the ARM v8
* Architecture reference manual Issue A.k B2.8.2 "Device memory".
*/
#define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))
/* /*
* io{read,write}{16,32,64}be() macros * io{read,write}{16,32,64}be() macros
*/ */
......
...@@ -82,20 +82,20 @@ void devm_memunmap(struct device *dev, void *addr); ...@@ -82,20 +82,20 @@ void devm_memunmap(struct device *dev, void *addr);
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
/* /*
* The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and * The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and
* Posting") mandate non-posted configuration transactions. There is * Posting") mandate non-posted configuration transactions. This default
* no ioremap API in the kernel that can guarantee non-posted write * implementation attempts to use the ioremap_np() API to provide this
* semantics across arches so provide a default implementation for * on arches that support it, and falls back to ioremap() on those that
* mapping PCI config space that defaults to ioremap(); arches * don't. Overriding this function is deprecated; arches that properly
* should override it if they have memory mapping implementations that * support non-posted accesses should implement ioremap_np() instead, which
* guarantee non-posted writes semantics to make the memory mapping * this default implementation can then use to return mappings compliant with
* compliant with the PCI specification. * the PCI specification.
*/ */
#ifndef pci_remap_cfgspace #ifndef pci_remap_cfgspace
#define pci_remap_cfgspace pci_remap_cfgspace #define pci_remap_cfgspace pci_remap_cfgspace
static inline void __iomem *pci_remap_cfgspace(phys_addr_t offset, static inline void __iomem *pci_remap_cfgspace(phys_addr_t offset,
size_t size) size_t size)
{ {
return ioremap(offset, size); return ioremap_np(offset, size) ?: ioremap(offset, size);
} }
#endif #endif
#endif #endif
......
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