Commit b126b027 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville

ath9k: Remove unused workaround

The workaround for ASPM/L0s is needed only for AR9485 1.0,
which was never sold and is not supported by ath9k.
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 413c0303
...@@ -2561,11 +2561,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) ...@@ -2561,11 +2561,6 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
} }
if (AR_SREV_9485_10(ah)) {
pCap->pcie_lcr_extsync_en = true;
pCap->pcie_lcr_offset = 0x80;
}
if (ath9k_hw_dfs_tested(ah)) if (ath9k_hw_dfs_tested(ah))
pCap->hw_caps |= ATH9K_HW_CAP_DFS; pCap->hw_caps |= ATH9K_HW_CAP_DFS;
......
...@@ -273,8 +273,6 @@ struct ath9k_hw_capabilities { ...@@ -273,8 +273,6 @@ struct ath9k_hw_capabilities {
u8 rx_status_len; u8 rx_status_len;
u8 tx_desc_len; u8 tx_desc_len;
u8 txs_len; u8 txs_len;
u16 pcie_lcr_offset;
bool pcie_lcr_extsync_en;
}; };
struct ath9k_ops_config { struct ath9k_ops_config {
...@@ -930,7 +928,6 @@ struct ath_bus_ops { ...@@ -930,7 +928,6 @@ struct ath_bus_ops {
void (*read_cachesize)(struct ath_common *common, int *csz); void (*read_cachesize)(struct ath_common *common, int *csz);
bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
void (*bt_coex_prep)(struct ath_common *common); void (*bt_coex_prep)(struct ath_common *common);
void (*extn_synch_en)(struct ath_common *common);
void (*aspm_init)(struct ath_common *common); void (*aspm_init)(struct ath_common *common);
}; };
......
...@@ -686,9 +686,6 @@ static int ath9k_start(struct ieee80211_hw *hw) ...@@ -686,9 +686,6 @@ static int ath9k_start(struct ieee80211_hw *hw)
spin_unlock_bh(&sc->sc_pcu_lock); spin_unlock_bh(&sc->sc_pcu_lock);
if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
common->bus_ops->extn_synch_en(common);
mutex_unlock(&sc->mutex); mutex_unlock(&sc->mutex);
ath9k_ps_restore(sc); ath9k_ps_restore(sc);
......
...@@ -96,17 +96,6 @@ static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) ...@@ -96,17 +96,6 @@ static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
return true; return true;
} }
static void ath_pci_extn_synch_enable(struct ath_common *common)
{
struct ath_softc *sc = (struct ath_softc *) common->priv;
struct pci_dev *pdev = to_pci_dev(sc->dev);
u8 lnkctl;
pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
lnkctl |= PCI_EXP_LNKCTL_ES;
pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
}
/* Need to be called after we discover btcoex capabilities */ /* Need to be called after we discover btcoex capabilities */
static void ath_pci_aspm_init(struct ath_common *common) static void ath_pci_aspm_init(struct ath_common *common)
{ {
...@@ -153,7 +142,6 @@ static const struct ath_bus_ops ath_pci_bus_ops = { ...@@ -153,7 +142,6 @@ static const struct ath_bus_ops ath_pci_bus_ops = {
.ath_bus_type = ATH_PCI, .ath_bus_type = ATH_PCI,
.read_cachesize = ath_pci_read_cachesize, .read_cachesize = ath_pci_read_cachesize,
.eeprom_read = ath_pci_eeprom_read, .eeprom_read = ath_pci_eeprom_read,
.extn_synch_en = ath_pci_extn_synch_enable,
.aspm_init = ath_pci_aspm_init, .aspm_init = ath_pci_aspm_init,
}; };
......
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