Commit b134b10c authored by Alex Elder's avatar Alex Elder Committed by David S. Miller

net: ipa: update IPA version comments in "ipa_reg.h"

Some definitions in "ipa_reg.h" are only valid for certain versions
of IPA.  In such cases a comment indicates a version or range of
versions where the definition is (or is not) valid.  Almost all such
cases look like "IPA vX.Y", but a few don't include the "IPA" tag.

Update these so they all consistently include "IPA".  And replace
a few lines that talk about "the next bit" in the definition of the
ipa_irq_id enumerated type with a more concise comment using the
"IPA vX.Y" convention.
Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent dd043b39
...@@ -240,25 +240,25 @@ enum ipa_reg_local_pkt_proc_cntxt_field_id { ...@@ -240,25 +240,25 @@ enum ipa_reg_local_pkt_proc_cntxt_field_id {
/* COUNTER_CFG register */ /* COUNTER_CFG register */
enum ipa_reg_counter_cfg_field_id { enum ipa_reg_counter_cfg_field_id {
EOT_COAL_GRANULARITY, /* Not v3.5+ */ EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */
AGGR_GRANULARITY, AGGR_GRANULARITY,
}; };
/* IPA_TX_CFG register */ /* IPA_TX_CFG register */
enum ipa_reg_ipa_tx_cfg_field_id { enum ipa_reg_ipa_tx_cfg_field_id {
TX0_PREFETCH_DISABLE, /* Not v4.0+ */ TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */
TX1_PREFETCH_DISABLE, /* Not v4.0+ */ TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */ PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */ PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */
DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */ DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */
DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */ DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */
DMAW_MAX_BEATS_256_DIS, /* v4.0+ */ DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */
PA_MASK_EN, /* v4.0+ */ PA_MASK_EN, /* IPA v4.0+ */
PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */ PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */
DUAL_TX_ENABLE, /* v4.5+ */ DUAL_TX_ENABLE, /* IPA v4.5+ */
SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */ SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */
SSPND_PA_NO_BQ_STATE, /* v4.2 only */ SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */
HOLB_STICKY_DROP_EN, /* v5.0+ */ HOLB_STICKY_DROP_EN, /* IPA v5.0+ */
}; };
/* FLAVOR_0 register */ /* FLAVOR_0 register */
...@@ -319,8 +319,8 @@ enum ipa_reg_rsrc_grp_rsrc_type_field_id { ...@@ -319,8 +319,8 @@ enum ipa_reg_rsrc_grp_rsrc_type_field_id {
/* ENDP_INIT_CTRL register */ /* ENDP_INIT_CTRL register */
enum ipa_reg_endp_init_ctrl_field_id { enum ipa_reg_endp_init_ctrl_field_id {
ENDP_SUSPEND, /* Not v4.0+ */ ENDP_SUSPEND, /* Not IPA v4.0+ */
ENDP_DELAY, /* Not v4.2+ */ ENDP_DELAY, /* Not IPA v4.2+ */
}; };
/* ENDP_INIT_CFG register */ /* ENDP_INIT_CFG register */
...@@ -359,11 +359,11 @@ enum ipa_reg_endp_init_hdr_field_id { ...@@ -359,11 +359,11 @@ enum ipa_reg_endp_init_hdr_field_id {
HDR_ADDITIONAL_CONST_LEN, HDR_ADDITIONAL_CONST_LEN,
HDR_OFST_PKT_SIZE_VALID, HDR_OFST_PKT_SIZE_VALID,
HDR_OFST_PKT_SIZE, HDR_OFST_PKT_SIZE,
HDR_A5_MUX, /* Not v4.9+ */ HDR_A5_MUX, /* Not IPA v4.9+ */
HDR_LEN_INC_DEAGG_HDR, HDR_LEN_INC_DEAGG_HDR,
HDR_METADATA_REG_VALID, /* Not v4.5+ */ HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */
HDR_LEN_MSB, /* v4.5+ */ HDR_LEN_MSB, /* IPA v4.5+ */
HDR_OFST_METADATA_MSB, /* v4.5+ */ HDR_OFST_METADATA_MSB, /* IPA v4.5+ */
}; };
/* ENDP_INIT_HDR_EXT register */ /* ENDP_INIT_HDR_EXT register */
...@@ -374,23 +374,23 @@ enum ipa_reg_endp_init_hdr_ext_field_id { ...@@ -374,23 +374,23 @@ enum ipa_reg_endp_init_hdr_ext_field_id {
HDR_PAYLOAD_LEN_INC_PADDING, HDR_PAYLOAD_LEN_INC_PADDING,
HDR_TOTAL_LEN_OR_PAD_OFFSET, HDR_TOTAL_LEN_OR_PAD_OFFSET,
HDR_PAD_TO_ALIGNMENT, HDR_PAD_TO_ALIGNMENT,
HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */ HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */
HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */ HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */
HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */ HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */
HDR_BYTES_TO_REMOVE_VALID, /* v5.0+ */ HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */
HDR_BYTES_TO_REMOVE, /* v5.0+ */ HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */
}; };
/* ENDP_INIT_MODE register */ /* ENDP_INIT_MODE register */
enum ipa_reg_endp_init_mode_field_id { enum ipa_reg_endp_init_mode_field_id {
ENDP_MODE, ENDP_MODE,
DCPH_ENABLE, /* v4.5+ */ DCPH_ENABLE, /* IPA v4.5+ */
DEST_PIPE_INDEX, DEST_PIPE_INDEX,
BYTE_THRESHOLD, BYTE_THRESHOLD,
PIPE_REPLICATION_EN, PIPE_REPLICATION_EN,
PAD_EN, PAD_EN,
HDR_FTCH_DISABLE, /* v4.5+ */ HDR_FTCH_DISABLE, /* IPA v4.5+ */
DRBIP_ACL_ENABLE, /* v4.9+ */ DRBIP_ACL_ENABLE, /* IPA v4.9+ */
}; };
/** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */
...@@ -439,10 +439,10 @@ enum ipa_reg_endp_init_hol_block_en_field_id { ...@@ -439,10 +439,10 @@ enum ipa_reg_endp_init_hol_block_en_field_id {
/* ENDP_INIT_HOL_BLOCK_TIMER register */ /* ENDP_INIT_HOL_BLOCK_TIMER register */
enum ipa_reg_endp_init_hol_block_timer_field_id { enum ipa_reg_endp_init_hol_block_timer_field_id {
TIMER_BASE_VALUE, /* Not v4.5+ */ TIMER_BASE_VALUE, /* Not IPA v4.5+ */
TIMER_SCALE, /* v4.2 only */ TIMER_SCALE, /* IPA v4.2 only */
TIMER_LIMIT, /* v4.5+ */ TIMER_LIMIT, /* IPA v4.5+ */
TIMER_GRAN_SEL, /* v4.5+ */ TIMER_GRAN_SEL, /* IPA v4.5+ */
}; };
/* ENDP_INIT_DEAGGR register */ /* ENDP_INIT_DEAGGR register */
...@@ -463,7 +463,7 @@ enum ipa_reg_endp_init_rsrc_grp_field_id { ...@@ -463,7 +463,7 @@ enum ipa_reg_endp_init_rsrc_grp_field_id {
/* ENDP_INIT_SEQ register */ /* ENDP_INIT_SEQ register */
enum ipa_reg_endp_init_seq_field_id { enum ipa_reg_endp_init_seq_field_id {
SEQ_TYPE, SEQ_TYPE,
SEQ_REP_TYPE, /* Not v4.5+ */ SEQ_REP_TYPE, /* Not IPA v4.5+ */
}; };
/** /**
...@@ -512,8 +512,8 @@ enum ipa_seq_rep_type { ...@@ -512,8 +512,8 @@ enum ipa_seq_rep_type {
enum ipa_reg_endp_status_field_id { enum ipa_reg_endp_status_field_id {
STATUS_EN, STATUS_EN,
STATUS_ENDP, STATUS_ENDP,
STATUS_LOCATION, /* Not v4.5+ */ STATUS_LOCATION, /* Not IPA v4.5+ */
STATUS_PKT_SUPPRESS, /* v4.0+ */ STATUS_PKT_SUPPRESS, /* IPA v4.0+ */
}; };
/* ENDP_FILTER_ROUTER_HSH_CFG register */ /* ENDP_FILTER_ROUTER_HSH_CFG register */
...@@ -588,8 +588,7 @@ enum ipa_reg_endp_cache_cfg_field_id { ...@@ -588,8 +588,7 @@ enum ipa_reg_endp_cache_cfg_field_id {
*/ */
enum ipa_irq_id { enum ipa_irq_id {
IPA_IRQ_BAD_SNOC_ACCESS = 0x0, IPA_IRQ_BAD_SNOC_ACCESS = 0x0,
/* The next bit is not present for IPA v3.5+ */ IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */
IPA_IRQ_EOT_COAL = 0x1,
IPA_IRQ_UC_0 = 0x2, IPA_IRQ_UC_0 = 0x2,
IPA_IRQ_UC_1 = 0x3, IPA_IRQ_UC_1 = 0x3,
IPA_IRQ_UC_2 = 0x4, IPA_IRQ_UC_2 = 0x4,
...@@ -610,17 +609,14 @@ enum ipa_irq_id { ...@@ -610,17 +609,14 @@ enum ipa_irq_id {
IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13,
IPA_IRQ_PIPE_RED_ABOVE = 0x14, IPA_IRQ_PIPE_RED_ABOVE = 0x14,
IPA_IRQ_UCP = 0x15, IPA_IRQ_UCP = 0x15,
/* The next bit is not present for IPA v4.5+ */ IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */
IPA_IRQ_DCMP = 0x16,
IPA_IRQ_GSI_EE = 0x17, IPA_IRQ_GSI_EE = 0x17,
IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18,
IPA_IRQ_GSI_UC = 0x19, IPA_IRQ_GSI_UC = 0x19,
/* The next bit is present for IPA v4.5+ */ IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5+ */
IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9+ */
/* The next three bits are present for IPA v4.9+ */ IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9+ */
IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9+ */
IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c,
IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d,
IPA_IRQ_COUNT, /* Last; not an id */ IPA_IRQ_COUNT, /* Last; not an id */
}; };
......
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