Commit b136d72c authored by Clément Péron's avatar Clément Péron Committed by Mauro Carvalho Chehab

media: rc: sunxi: Add RXSTA bits definition

We are using RXINT bits definition when looking at RXSTA register.

These bits are equal but it's not really proper.

Introduce the RXSTA bits and use them to have coherency.
Signed-off-by: default avatarClément Péron <peron.clem@gmail.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarSean Young <sean@mess.org>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 87d06098
...@@ -39,11 +39,11 @@ ...@@ -39,11 +39,11 @@
/* Rx Interrupt Enable */ /* Rx Interrupt Enable */
#define SUNXI_IR_RXINT_REG 0x2C #define SUNXI_IR_RXINT_REG 0x2C
/* Rx FIFO Overflow */ /* Rx FIFO Overflow Interrupt Enable */
#define REG_RXINT_ROI_EN BIT(0) #define REG_RXINT_ROI_EN BIT(0)
/* Rx Packet End */ /* Rx Packet End Interrupt Enable */
#define REG_RXINT_RPEI_EN BIT(1) #define REG_RXINT_RPEI_EN BIT(1)
/* Rx FIFO Data Available */ /* Rx FIFO Data Available Interrupt Enable */
#define REG_RXINT_RAI_EN BIT(4) #define REG_RXINT_RAI_EN BIT(4)
/* Rx FIFO available byte level */ /* Rx FIFO available byte level */
...@@ -51,6 +51,12 @@ ...@@ -51,6 +51,12 @@
/* Rx Interrupt Status */ /* Rx Interrupt Status */
#define SUNXI_IR_RXSTA_REG 0x30 #define SUNXI_IR_RXSTA_REG 0x30
/* Rx FIFO Overflow */
#define REG_RXSTA_ROI REG_RXINT_ROI_EN
/* Rx Packet End */
#define REG_RXSTA_RPE REG_RXINT_RPEI_EN
/* Rx FIFO Data Available */
#define REG_RXSTA_RA REG_RXINT_RAI_EN
/* RX FIFO Get Available Counter */ /* RX FIFO Get Available Counter */
#define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1)) #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1))
/* Clear all interrupt status value */ /* Clear all interrupt status value */
...@@ -110,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) ...@@ -110,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* clean all pending statuses */ /* clean all pending statuses */
writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG);
if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) { if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) {
/* How many messages in fifo */ /* How many messages in fifo */
rc = REG_RXSTA_GET_AC(status); rc = REG_RXSTA_GET_AC(status);
/* Sanity check */ /* Sanity check */
...@@ -126,9 +132,9 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) ...@@ -126,9 +132,9 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
} }
} }
if (status & REG_RXINT_ROI_EN) { if (status & REG_RXSTA_ROI) {
ir_raw_event_reset(ir->rc); ir_raw_event_reset(ir->rc);
} else if (status & REG_RXINT_RPEI_EN) { } else if (status & REG_RXSTA_RPE) {
ir_raw_event_set_idle(ir->rc, true); ir_raw_event_set_idle(ir->rc, true);
ir_raw_event_handle(ir->rc); ir_raw_event_handle(ir->rc);
} }
......
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