Commit b16f8188 authored by Yixian Liu's avatar Yixian Liu Committed by Jason Gunthorpe

RDMA/hns: Refactor eq code for hip06

Considering the compatibility of supporting hip08's eq
process and possible changes of data structure, this patch
refactors the eq code structure of hip06.

We move all the eq process code for hip06 from hns_roce_eq.c
into hns_roce_hw_v1.c, and also for hns_roce_eq.h. With
these changes, it will be convenient to add the eq support
for later hardware version.
Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Reviewed-by: default avatarLijun Ou <oulijun@huawei.com>
Reviewed-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 74482086
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3 ccflags-y := -Idrivers/net/ethernet/hisilicon/hns3
obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o obj-$(CONFIG_INFINIBAND_HNS) += hns-roce.o
hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_eq.o hns_roce_pd.o \ hns-roce-objs := hns_roce_main.o hns_roce_cmd.o hns_roce_pd.o \
hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \ hns_roce_ah.o hns_roce_hem.o hns_roce_mr.o hns_roce_qp.o \
hns_roce_cq.o hns_roce_alloc.o hns_roce_cq.o hns_roce_alloc.o
obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o obj-$(CONFIG_INFINIBAND_HNS_HIP06) += hns-roce-hw-v1.o
......
...@@ -103,6 +103,7 @@ void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, ...@@ -103,6 +103,7 @@ void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
context->out_param = out_param; context->out_param = out_param;
complete(&context->done); complete(&context->done);
} }
EXPORT_SYMBOL_GPL(hns_roce_cmd_event);
/* this should be called with "use_events" */ /* this should be called with "use_events" */
static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param, static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
......
...@@ -196,15 +196,14 @@ void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) ...@@ -196,15 +196,14 @@ void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq)
if (ret) if (ret)
dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret, dev_err(dev, "HW2SW_CQ failed (%d) for CQN %06lx\n", ret,
hr_cq->cqn); hr_cq->cqn);
if (hr_dev->eq_table.eq) {
/* Waiting interrupt process procedure carried out */ /* Waiting interrupt process procedure carried out */
synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq); synchronize_irq(hr_dev->eq_table.eq[hr_cq->vector].irq);
/* wait for all interrupt processed */ /* wait for all interrupt processed */
if (atomic_dec_and_test(&hr_cq->refcount)) if (atomic_dec_and_test(&hr_cq->refcount))
complete(&hr_cq->free); complete(&hr_cq->free);
wait_for_completion(&hr_cq->free); wait_for_completion(&hr_cq->free);
}
spin_lock_irq(&cq_table->lock); spin_lock_irq(&cq_table->lock);
radix_tree_delete(&cq_table->tree, hr_cq->cqn); radix_tree_delete(&cq_table->tree, hr_cq->cqn);
...@@ -460,6 +459,7 @@ void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn) ...@@ -460,6 +459,7 @@ void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn)
++cq->arm_sn; ++cq->arm_sn;
cq->comp(cq); cq->comp(cq);
} }
EXPORT_SYMBOL_GPL(hns_roce_cq_completion);
void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type) void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
{ {
...@@ -482,6 +482,7 @@ void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type) ...@@ -482,6 +482,7 @@ void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type)
if (atomic_dec_and_test(&cq->refcount)) if (atomic_dec_and_test(&cq->refcount))
complete(&cq->free); complete(&cq->free);
} }
EXPORT_SYMBOL_GPL(hns_roce_cq_event);
int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev) int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev)
{ {
......
...@@ -62,12 +62,16 @@ ...@@ -62,12 +62,16 @@
#define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
#define HNS_ROCE_MIN_CQE_CNT 16 #define HNS_ROCE_MIN_CQE_CNT 16
#define HNS_ROCE_MAX_IRQ_NUM 34 #define HNS_ROCE_MAX_IRQ_NUM 128
#define HNS_ROCE_COMP_VEC_NUM 32 #define EQ_ENABLE 1
#define EQ_DISABLE 0
#define HNS_ROCE_AEQE_VEC_NUM 1 #define HNS_ROCE_CEQ 0
#define HNS_ROCE_AEQE_OF_VEC_NUM 1 #define HNS_ROCE_AEQ 1
#define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
#define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
/* 4G/4K = 1M */ /* 4G/4K = 1M */
#define HNS_ROCE_SL_SHIFT 28 #define HNS_ROCE_SL_SHIFT 28
...@@ -485,6 +489,45 @@ struct hns_roce_ib_iboe { ...@@ -485,6 +489,45 @@ struct hns_roce_ib_iboe {
u8 phy_port[HNS_ROCE_MAX_PORTS]; u8 phy_port[HNS_ROCE_MAX_PORTS];
}; };
enum {
HNS_ROCE_EQ_STAT_INVALID = 0,
HNS_ROCE_EQ_STAT_VALID = 2,
};
struct hns_roce_ceqe {
u32 comp;
};
struct hns_roce_aeqe {
u32 asyn;
union {
struct {
u32 qp;
u32 rsv0;
u32 rsv1;
} qp_event;
struct {
u32 cq;
u32 rsv0;
u32 rsv1;
} cq_event;
struct {
u32 ceqe;
u32 rsv0;
u32 rsv1;
} ce_event;
struct {
__le64 out_param;
__le16 token;
u8 status;
u8 rsv0;
} __packed cmd;
} event;
};
struct hns_roce_eq { struct hns_roce_eq {
struct hns_roce_dev *hr_dev; struct hns_roce_dev *hr_dev;
void __iomem *doorbell; void __iomem *doorbell;
...@@ -502,7 +545,7 @@ struct hns_roce_eq { ...@@ -502,7 +545,7 @@ struct hns_roce_eq {
struct hns_roce_eq_table { struct hns_roce_eq_table {
struct hns_roce_eq *eq; struct hns_roce_eq *eq;
void __iomem **eqc_base; void __iomem **eqc_base; /* only for hw v1 */
}; };
struct hns_roce_caps { struct hns_roce_caps {
...@@ -550,7 +593,7 @@ struct hns_roce_caps { ...@@ -550,7 +593,7 @@ struct hns_roce_caps {
u32 pbl_buf_pg_sz; u32 pbl_buf_pg_sz;
u32 pbl_hop_num; u32 pbl_hop_num;
int aeqe_depth; int aeqe_depth;
int ceqe_depth[HNS_ROCE_COMP_VEC_NUM]; int ceqe_depth;
enum ib_mtu max_mtu; enum ib_mtu max_mtu;
u32 qpc_bt_num; u32 qpc_bt_num;
u32 srqc_bt_num; u32 srqc_bt_num;
...@@ -623,6 +666,8 @@ struct hns_roce_hw { ...@@ -623,6 +666,8 @@ struct hns_roce_hw {
int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr); int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr);
int (*destroy_cq)(struct ib_cq *ibcq); int (*destroy_cq)(struct ib_cq *ibcq);
int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period); int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
int (*init_eq)(struct hns_roce_dev *hr_dev);
void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
}; };
struct hns_roce_dev { struct hns_roce_dev {
......
This diff is collapsed.
/*
* Copyright (c) 2016 Hisilicon Limited.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _HNS_ROCE_EQ_H
#define _HNS_ROCE_EQ_H
#define HNS_ROCE_CEQ 1
#define HNS_ROCE_AEQ 2
#define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
#define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
#define HNS_ROCE_CEQC_REG_OFFSET 0x18
#define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x10
#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x10
#define HNS_ROCE_INT_MASK_DISABLE 0
#define HNS_ROCE_INT_MASK_ENABLE 1
#define EQ_ENABLE 1
#define EQ_DISABLE 0
#define CONS_INDEX_MASK 0xffff
#define CEQ_REG_OFFSET 0x18
enum {
HNS_ROCE_EQ_STAT_INVALID = 0,
HNS_ROCE_EQ_STAT_VALID = 2,
};
struct hns_roce_aeqe {
u32 asyn;
union {
struct {
u32 qp;
u32 rsv0;
u32 rsv1;
} qp_event;
struct {
u32 cq;
u32 rsv0;
u32 rsv1;
} cq_event;
struct {
u32 port;
u32 rsv0;
u32 rsv1;
} port_event;
struct {
u32 ceqe;
u32 rsv0;
u32 rsv1;
} ce_event;
struct {
__le64 out_param;
__le16 token;
u8 status;
u8 rsv0;
} __packed cmd;
} event;
};
#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M \
(((1UL << 8) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S)
#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M \
(((1UL << 7) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)
#define HNS_ROCE_AEQE_U32_4_OWNER_S 31
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M \
(((1UL << 24) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S)
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M \
(((1UL << 3) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S)
#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M \
(((1UL << 16) - 1) << HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S)
#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M \
(((1UL << 5) - 1) << HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S)
struct hns_roce_ceqe {
union {
int comp;
} ceqe;
};
#define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S 0
#define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
#define HNS_ROCE_CEQE_CEQE_COMP_CQN_M \
(((1UL << 16) - 1) << HNS_ROCE_CEQE_CEQE_COMP_CQN_S)
#endif /* _HNS_ROCE_EQ_H */
This diff is collapsed.
...@@ -60,8 +60,13 @@ ...@@ -60,8 +60,13 @@
#define HNS_ROCE_V1_GID_NUM 16 #define HNS_ROCE_V1_GID_NUM 16
#define HNS_ROCE_V1_RESV_QP 8 #define HNS_ROCE_V1_RESV_QP 8
#define HNS_ROCE_V1_NUM_COMP_EQE 0x8000 #define HNS_ROCE_V1_MAX_IRQ_NUM 34
#define HNS_ROCE_V1_NUM_ASYNC_EQE 0x400 #define HNS_ROCE_V1_COMP_VEC_NUM 32
#define HNS_ROCE_V1_AEQE_VEC_NUM 1
#define HNS_ROCE_V1_ABNORMAL_VEC_NUM 1
#define HNS_ROCE_V1_COMP_EQE_NUM 0x8000
#define HNS_ROCE_V1_ASYNC_EQE_NUM 0x400
#define HNS_ROCE_V1_QPC_ENTRY_SIZE 256 #define HNS_ROCE_V1_QPC_ENTRY_SIZE 256
#define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8 #define HNS_ROCE_V1_IRRL_ENTRY_SIZE 8
...@@ -159,6 +164,41 @@ ...@@ -159,6 +164,41 @@
#define SDB_INV_CNT_OFFSET 8 #define SDB_INV_CNT_OFFSET 8
#define SDB_ST_CMP_VAL 8 #define SDB_ST_CMP_VAL 8
#define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x10
#define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x10
#define HNS_ROCE_INT_MASK_DISABLE 0
#define HNS_ROCE_INT_MASK_ENABLE 1
#define CEQ_REG_OFFSET 0x18
#define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S 0
#define HNS_ROCE_V1_CONS_IDX_M GENMASK(15, 0)
#define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
#define HNS_ROCE_CEQE_CEQE_COMP_CQN_M GENMASK(31, 16)
#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
#define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M GENMASK(23, 16)
#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
#define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M GENMASK(30, 24)
#define HNS_ROCE_AEQE_U32_4_OWNER_S 31
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M GENMASK(23, 0)
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
#define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M GENMASK(27, 25)
#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
#define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M GENMASK(15, 0)
#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
#define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M GENMASK(4, 0)
struct hns_roce_cq_context { struct hns_roce_cq_context {
u32 cqc_byte_4; u32 cqc_byte_4;
u32 cq_bt_l; u32 cq_bt_l;
......
...@@ -748,12 +748,10 @@ int hns_roce_init(struct hns_roce_dev *hr_dev) ...@@ -748,12 +748,10 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)
goto error_failed_cmd_init; goto error_failed_cmd_init;
} }
if (hr_dev->cmd_mod) { ret = hr_dev->hw->init_eq(hr_dev);
ret = hns_roce_init_eq_table(hr_dev); if (ret) {
if (ret) { dev_err(dev, "eq init failed!\n");
dev_err(dev, "eq init failed!\n"); goto error_failed_eq_table;
goto error_failed_eq_table;
}
} }
if (hr_dev->cmd_mod) { if (hr_dev->cmd_mod) {
...@@ -805,8 +803,7 @@ int hns_roce_init(struct hns_roce_dev *hr_dev) ...@@ -805,8 +803,7 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)
hns_roce_cmd_use_polling(hr_dev); hns_roce_cmd_use_polling(hr_dev);
error_failed_use_event: error_failed_use_event:
if (hr_dev->cmd_mod) hr_dev->hw->cleanup_eq(hr_dev);
hns_roce_cleanup_eq_table(hr_dev);
error_failed_eq_table: error_failed_eq_table:
hns_roce_cmd_cleanup(hr_dev); hns_roce_cmd_cleanup(hr_dev);
...@@ -837,8 +834,7 @@ void hns_roce_exit(struct hns_roce_dev *hr_dev) ...@@ -837,8 +834,7 @@ void hns_roce_exit(struct hns_roce_dev *hr_dev)
if (hr_dev->cmd_mod) if (hr_dev->cmd_mod)
hns_roce_cmd_use_polling(hr_dev); hns_roce_cmd_use_polling(hr_dev);
if (hr_dev->cmd_mod) hr_dev->hw->cleanup_eq(hr_dev);
hns_roce_cleanup_eq_table(hr_dev);
hns_roce_cmd_cleanup(hr_dev); hns_roce_cmd_cleanup(hr_dev);
if (hr_dev->hw->cmq_exit) if (hr_dev->hw->cmq_exit)
hr_dev->hw->cmq_exit(hr_dev); hr_dev->hw->cmq_exit(hr_dev);
......
...@@ -65,6 +65,7 @@ void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type) ...@@ -65,6 +65,7 @@ void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
if (atomic_dec_and_test(&qp->refcount)) if (atomic_dec_and_test(&qp->refcount))
complete(&qp->free); complete(&qp->free);
} }
EXPORT_SYMBOL_GPL(hns_roce_qp_event);
static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp, static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
enum hns_roce_event type) enum hns_roce_event type)
......
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