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Commit b324c67d authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull device tree conversions for arm-soc, part 1, from Olof Johansson:
 "The spear3xx, lpc32xx, shmobile and mmp platforms are joining the game
  of booting using device trees, which is a great step forward for them.
  at91 and spear have pretty much completed this process with a huge
  amount of work being put into at91.  The other platforms are
  continuing the process.

  We finally start to see the payback on this investment, as new
  machines are getting supported purely by adding a .dts source file
  that can be completely independent of the kernel source."

Fix up trivial conflict in arch/arm/Kconfig

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
  ARM: at91: Add ADC driver to at91sam9260/at91sam9g20 dtsi files
  arm/dts: omap4-panda: Add LEDs support
  arm/dts: omap4-sdp: Add LEDs support
  arm/dts: twl4030: Add twl4030-gpio node
  OMAP4: devices: Do not create mcpdm device if the dtb has been provided
  OMAP4: devices: Do not create dmic device if the dtb has been provided
  Documentation: update docs for mmp dt
  ARM: dts: refresh dts file for arch mmp
  ARM: mmp: support pxa910 with device tree
  ARM: mmp: support mmp2 with device tree
  gpio: pxa: parse gpio from DTS file
  ARM: mmp: support DT in timer
  ARM: mmp: support DT in irq
  ARM: mmp: append CONFIG_MACH_MMP2_DT
  ARM: mmp: fix build issue on mmp with device tree
  ARM: ux500: Enable PRCMU Timer 4 (clocksource) for Device Tree
  ARM: ux500: Disable SMSC911x platform code registration when DT is enabled
  ARM: ux500: Fork cpu-db8500 platform_devs for sequential DT enablement
  ARM: ux500: Do not attempt to register non-existent i2c devices on Snowball
  ARM: SPEAr3xx: Correct keyboard data passed from DT
  ...
parents 8dca6010 396d81cd
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Documentation/arm/SPEAr/overview.txt
View file @ b324c67d
......@@ -17,14 +17,14 @@ Introduction
SPEAr (Platform)
- SPEAr3XX (3XX SOC series, based on ARM9)
- SPEAr300 (SOC)
- SPEAr300_EVB (Evaluation Board)
- SPEAr300 Evaluation Board
- SPEAr310 (SOC)
- SPEAr310_EVB (Evaluation Board)
- SPEAr310 Evaluation Board
- SPEAr320 (SOC)
- SPEAr320_EVB (Evaluation Board)
- SPEAr320 Evaluation Board
- SPEAr6XX (6XX SOC series, based on ARM9)
- SPEAr600 (SOC)
- SPEAr600_EVB (Evaluation Board)
- SPEAr600 Evaluation Board
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
......@@ -51,10 +51,11 @@ Introduction
Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
mach-spear* also contains board specific files for each machine type.
mach-spear* doesn't contains board specific files as they fully support
Flattened Device Tree.
Document Author
---------------
Viresh Kumar, (c) 2010 ST Microelectronics
Viresh Kumar <viresh.kumar@st.com>, (c) 2010-2012 ST Microelectronics
Documentation/devicetree/bindings/arm/lpc32xx-mic.txt 0 → 100644
View file @ b324c67d
* NXP LPC32xx Main Interrupt Controller
(MIC, including SIC1 and SIC2 secondary controllers)
Required properties:
- compatible: Should be "nxp,lpc3220-mic"
- interrupt-controller: Identifies the node as an interrupt controller.
- interrupt-parent: Empty for the interrupt controller itself
- #interrupt-cells: The number of cells to define the interrupts. Should be 2.
The first cell is the IRQ number
The second cell is used to specify mode:
1 = low-to-high edge triggered
2 = high-to-low edge triggered
4 = active high level-sensitive
8 = active low level-sensitive
Default for internal sources should be set to 4 (active high).
- reg: Should contain MIC registers location and length
Examples:
/*
* MIC
*/
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
interrupt-controller;
interrupt-parent;
#interrupt-cells = <2>;
reg = <0x40008000 0xC000>;
};
/*
* ADC
*/
adc@40048000 {
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupt-parent = <&mic>;
interrupts = <39 4>;
};
Documentation/devicetree/bindings/arm/lpc32xx.txt 0 → 100644
View file @ b324c67d
NXP LPC32xx Platforms Device Tree Bindings
------------------------------------------
Boards with the NXP LPC32xx SoC shall have the following properties:
Required root node property:
compatible: must be "nxp,lpc3220", "nxp,lpc3230", "nxp,lpc3240" or "nxp,lpc3250"
Documentation/devicetree/bindings/arm/mrvl/intc.txt 0 → 100644
View file @ b324c67d
* Marvell MMP Interrupt controller
Required properties:
- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
"mrvl,mmp2-mux-intc"
- reg : Address and length of the register set of the interrupt controller.
If the interrupt controller is intc, address and length means the range
of the whold interrupt controller. If the interrupt controller is mux-intc,
address and length means one register. Since address of mux-intc is in the
range of intc. mux-intc is secondary interrupt controller.
- reg-names : Name of the register set of the interrupt controller. It's
only required in mux-intc interrupt controller.
- interrupts : Should be the port interrupt shared by mux interrupts. It's
only required in mux-intc interrupt controller.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source.
- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
controller.
- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge
detection first.
Example:
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
intcmux4@d4282150 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x150 0x4>, <0x168 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
Documentation/devicetree/bindings/arm/mrvl.txt → Documentation/devicetree/bindings/arm/mrvl/mrvl.txt
View file @ b324c67d
......@@ -4,3 +4,11 @@ Marvell Platforms Device Tree Bindings
PXA168 Aspenite Board
Required root node properties:
- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
PXA910 DKB Board
Required root node properties:
- compatible = "mrvl,pxa910-dkb";
MMP2 Brownstone Board
Required root node properties:
- compatible = "mrvl,mmp2-brownstone";
Documentation/devicetree/bindings/arm/mrvl/timer.txt 0 → 100644
View file @ b324c67d
* Marvell MMP Timer controller
Required properties:
- compatible : Should be "mrvl,mmp-timer".
- reg : Address and length of the register set of timer controller.
- interrupts : Should be the interrupt number.
Example:
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};
Documentation/devicetree/bindings/arm/spear.txt
View file @ b324c67d
......@@ -6,3 +6,21 @@ Boards with the ST SPEAr600 SoC shall have the following properties:
Required root node property:
compatible = "st,spear600";
Boards with the ST SPEAr300 SoC shall have the following properties:
Required root node property:
compatible = "st,spear300";
Boards with the ST SPEAr310 SoC shall have the following properties:
Required root node property:
compatible = "st,spear310";
Boards with the ST SPEAr320 SoC shall have the following properties:
Required root node property:
compatible = "st,spear320";
Documentation/devicetree/bindings/gpio/gpio-nmk.txt 0 → 100644
View file @ b324c67d
Nomadik GPIO controller
Required properties:
- compatible : Should be "st,nomadik-gpio".
- reg : Physical base address and length of the controller's registers.
- interrupts : The interrupt outputs from the controller.
- #gpio-cells : Should be two:
The first cell is the pin number.
The second cell is used to specify optional parameters:
- bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
- gpio-controller : Marks the device node as a GPIO controller.
- interrupt-controller : Marks the device node as an interrupt controller.
- gpio-bank : Specifies which bank a controller owns.
- st,supports-sleepmode : Specifies whether controller can sleep or not
Example:
gpio1: gpio@8012e080 {
compatible = "st,nomadik-gpio";
reg = <0x8012e080 0x80>;
interrupts = <0 120 0x4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
supports-sleepmode;
gpio-bank = <1>;
};
Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
View file @ b324c67d
......@@ -3,19 +3,25 @@
Required properties:
- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all gpio pins, if
- interrupt-name : Should be the name of irq resource.
one number.
- interrupts : Should be the port interrupt shared by all gpio pins.
There're three gpio interrupts in arch-pxa, and they're gpio0,
gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
gpio_mux.
- interrupt-name : Should be the name of irq resource. Each interrupt
binds its interrupt-name.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be one. It is the pin number.
Example:
gpio: gpio@d4019000 {
compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
compatible = "mrvl,mmp-gpio";
reg = <0xd4019000 0x1000>;
interrupts = <49>, <17>, <18>;
interrupt-name = "gpio_mux", "gpio0", "gpio1";
interrupts = <49>;
interrupt-name = "gpio_mux";
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
......
Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
View file @ b324c67d
......@@ -3,34 +3,31 @@
Required properties :
- reg : Offset and length of the register set for the device
- compatible : should be "mrvl,mmp-twsi" where CHIP is the name of a
- compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
as shown in the example below.
Recommended properties :
- interrupts : <a b> where a is the interrupt number and b is a
field that represents an encoding of the sense and level
information for the interrupt. This should be encoded based on
the information in section 2) depending on the type of interrupt
controller you have.
- interrupts : the interrupt number
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
services interrupts for this device. If the parent is the default
interrupt controller in device tree, it could be ignored.
- mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
status register of i2c controller instead.
- mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
Examples:
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
};
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4025000 0x1000>;
interrupts = <58>;
};
......
Documentation/devicetree/bindings/i2c/pnx.txt 0 → 100644
View file @ b324c67d
* NXP PNX I2C Controller
Required properties:
- reg: Offset and length of the register set for the device
- compatible: should be "nxp,pnx-i2c"
- interrupts: configure one interrupt line
- #address-cells: always 1 (for i2c addresses)
- #size-cells: always 0
- interrupt-parent: the phandle for the interrupt controller that
services interrupts for this device.
Optional properties:
- clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz
Examples:
i2c1: i2c@400a0000 {
compatible = "nxp,pnx-i2c";
reg = <0x400a0000 0x100>;
interrupt-parent = <&mic>;
interrupts = <51 0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@400a8000 {
compatible = "nxp,pnx-i2c";
reg = <0x400a8000 0x100>;
interrupt-parent = <&mic>;
interrupts = <50 0>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
};
Documentation/devicetree/bindings/net/lpc-eth.txt 0 → 100644
View file @ b324c67d
* NXP LPC32xx SoC Ethernet Controller
Required properties:
- compatible: Should be "nxp,lpc-eth"
- reg: Address and length of the register set for the device
- interrupts: Should contain ethernet controller interrupt
Optional properties:
- phy-mode: String, operation mode of the PHY interface.
Supported values are: "mii", "rmii" (default)
- use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
- local-mac-address : 6 bytes, mac address
Example:
mac: ethernet@31060000 {
compatible = "nxp,lpc-eth";
reg = <0x31060000 0x1000>;
interrupt-parent = <&mic>;
interrupts = <29 0>;
phy-mode = "rmii";
use-iram;
};
arch/arm/Kconfig
View file @ b324c67d
......@@ -571,6 +571,7 @@ config ARCH_LPC32XX
select USB_ARCH_HAS_OHCI
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select USE_OF
help
Support for the NXP LPC32XX family of processors
......@@ -606,6 +607,7 @@ config ARCH_MMP
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select GPIO_PXA
select IRQ_DOMAIN
select PLAT_PXA
select SPARSE_IRQ
select GENERIC_ALLOCATOR
......
arch/arm/boot/dts/at91sam9260.dtsi 0 → 100644
View file @ b324c67d
/*
* at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
* 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
model = "Atmel AT91SAM9260 family SoC";
compatible = "atmel,at91sam9260";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
serial4 = &usart3;
serial5 = &usart4;
serial6 = &usart5;
gpio0 = &pioA;
gpio1 = &pioB;
gpio2 = &pioC;
tcb0 = &tcb0;
tcb1 = &tcb1;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory {
reg = <0x20000000 0x04000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <2>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
reg = <0xfffff000 0x200>;
};
ramc0: ramc@ffffea00 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffea00 0x200>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
};
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 4>;
};
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffa0000 0x100>;
interrupts = <17 4 18 4 19 4>;
};
tcb1: timer@fffdc000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffdc000 0x100>;
interrupts = <26 4 27 4 28 4>;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x100>;
interrupts = <2 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x100>;
interrupts = <3 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x100>;
interrupts = <4 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4>;
status = "disabled";
};
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
interrupts = <6 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
interrupts = <7 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart2: serial@fffb8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
interrupts = <8 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart3: serial@fffd0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd0000 0x200>;
interrupts = <23 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart4: serial@fffd4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd4000 0x200>;
interrupts = <24 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart5: serial@fffd8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd8000 0x200>;
interrupts = <25 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
macb0: ethernet@fffc4000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xfffc4000 0x100>;
interrupts = <21 4>;
status = "disabled";
};
usb1: gadget@fffa4000 {
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 4>;
status = "disabled";
};
adc0: adc@fffe0000 {
compatible = "atmel,at91sam9260-adc";
reg = <0xfffe0000 0x100>;
interrupts = <5 4>;
atmel,adc-use-external-triggers;
atmel,adc-channels-used = <0xf>;
atmel,adc-vref = <3300>;
atmel,adc-num-channels = <4>;
atmel,adc-startup-time = <15>;
atmel,adc-channel-base = <0x30>;
atmel,adc-drdy-mask = <0x10000>;
atmel,adc-status-register = <0x1c>;
atmel,adc-trigger-register = <0x04>;
trigger@0 {
trigger-name = "timer-counter-0";
trigger-value = <0x1>;
};
trigger@1 {
trigger-name = "timer-counter-1";
trigger-value = <0x3>;
};
trigger@2 {
trigger-name = "timer-counter-2";
trigger-value = <0x5>;
};
trigger@3 {
trigger-name = "external";
trigger-value = <0x13>;
trigger-external;
};
};
};
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
0xffffe800 0x200
>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
gpios = <&pioC 13 0
&pioC 14 0
0
>;
status = "disabled";
};
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 4>;
status = "disabled";
};
};
i2c@0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 0 /* sda */
&pioA 24 0 /* scl */
>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
arch/arm/boot/dts/at91sam9263.dtsi 0 → 100644
View file @ b324c67d
/*
* at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 only.
*/
/include/ "skeleton.dtsi"
/ {
model = "Atmel AT91SAM9263 family SoC";
compatible = "atmel,at91sam9263";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
gpio0 = &pioA;
gpio1 = &pioB;
gpio2 = &pioC;
gpio3 = &pioD;
gpio4 = &pioE;
tcb0 = &tcb0;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory {
reg = <0x20000000 0x08000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <2>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
reg = <0xfffff000 0x200>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
};
ramc: ramc@ffffe200 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffe200 0x200
0xffffe800 0x200>;
};
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 4>;
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <19 4>;
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x100>;
interrupts = <2 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x100>;
interrupts = <3 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x100>;
interrupts = <4 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x100>;
interrupts = <4 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x100>;
interrupts = <4 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
dbgu: serial@ffffee00 {
compatible = "atmel,at91sam9260-usart";
reg = <0xffffee00 0x200>;
interrupts = <1 4>;
status = "disabled";
};
usart0: serial@fff8c000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff8c000 0x200>;
interrupts = <7 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart1: serial@fff90000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff90000 0x200>;
interrupts = <8 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart2: serial@fff94000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfff94000 0x200>;
interrupts = <9 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
macb0: ethernet@fffbc000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xfffbc000 0x100>;
interrupts = <21 4>;
status = "disabled";
};
usb1: gadget@fff78000 {
compatible = "atmel,at91rm9200-udc";
reg = <0xfff78000 0x4000>;
interrupts = <24 4>;
status = "disabled";
};
};
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
0xffffe000 0x200
>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
gpios = <&pioA 22 0
&pioD 15 0
0
>;
status = "disabled";
};
usb0: ohci@00a00000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00a00000 0x100000>;
interrupts = <29 4>;
status = "disabled";
};
};
i2c@0 {
compatible = "i2c-gpio";
gpios = <&pioB 4 0 /* sda */
&pioB 5 0 /* scl */
>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
arch/arm/boot/dts/at91sam9263ek.dts 0 → 100644
View file @ b324c67d
/*
* at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 only
*/
/dts-v1/;
/include/ "at91sam9263.dtsi"
/ {
model = "Atmel at91sam9263ek";
compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <16367660>;
};
};
ahb {
apb {
dbgu: serial@ffffee00 {
status = "okay";
};
usart0: serial@fff8c000 {
status = "okay";
};
macb0: ethernet@fffbc000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fff78000 {
atmel,vbus-gpio = <&pioA 25 0>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt = <1>;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x20000>;
};
barebox@20000 {
label = "barebox";
reg = <0x20000 0x40000>;
};
bareboxenv@60000 {
label = "bareboxenv";
reg = <0x60000 0x20000>;
};
bareboxenv2@80000 {
label = "bareboxenv2";
reg = <0x80000 0x20000>;
};
oftree@80000 {
label = "oftree";
reg = <0xa0000 0x20000>;
};
kernel@a0000 {
label = "kernel";
reg = <0xc0000 0x400000>;
};
rootfs@4a0000 {
label = "rootfs";
reg = <0x4c0000 0x7800000>;
};
data@7ca0000 {
label = "data";
reg = <0x7cc0000 0x8340000>;
};
};
usb0: ohci@00a00000 {
num-ports = <2>;
status = "okay";
atmel,vbus-gpio = <&pioA 24 0
&pioA 21 0
>;
};
};
leds {
compatible = "gpio-leds";
d3 {
label = "d3";
gpios = <&pioB 7 0>;
linux,default-trigger = "heartbeat";
};
d2 {
label = "d2";
gpios = <&pioC 29 1>;
linux,default-trigger = "nand-disk";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
left_click {
label = "left_click";
gpios = <&pioC 5 1>;
linux,code = <272>;
gpio-key,wakeup;
};
right_click {
label = "right_click";
gpios = <&pioC 4 1>;
linux,code = <273>;
gpio-key,wakeup;
};
};
i2c@0 {
status = "okay";
24c512@50 {
compatible = "24c512";
reg = <0x50>;
pagesize = <128>;
};
};
};
arch/arm/boot/dts/at91sam9g20.dtsi
View file @ b324c67d
/*
* at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
*
* Copyright (C) 2011 Atmel,
* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
* 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 or later.
* Licensed under GPLv2.
*/
/include/ "skeleton.dtsi"
/include/ "at91sam9260.dtsi"
/ {
model = "Atmel AT91SAM9G20 family SoC";
compatible = "atmel,at91sam9g20";
interrupt-parent = <&aic>;
aliases {
serial0 = &dbgu;
serial1 = &usart0;
serial2 = &usart1;
serial3 = &usart2;
serial4 = &usart3;
serial5 = &usart4;
serial6 = &usart5;
gpio0 = &pioA;
gpio1 = &pioB;
gpio2 = &pioC;
tcb0 = &tcb0;
tcb1 = &tcb1;
};
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory {
reg = <0x20000000 0x08000000>;
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
apb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
aic: interrupt-controller@fffff000 {
#interrupt-cells = <2>;
compatible = "atmel,at91rm9200-aic";
interrupt-controller;
reg = <0xfffff000 0x200>;
};
ramc0: ramc@ffffea00 {
compatible = "atmel,at91sam9260-sdramc";
reg = <0xffffea00 0x200>;
};
pmc: pmc@fffffc00 {
compatible = "atmel,at91rm9200-pmc";
reg = <0xfffffc00 0x100>;
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
};
pit: timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0xf>;
interrupts = <1 4>;
};
tcb0: timer@fffa0000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffa0000 0x100>;
interrupts = <17 4 18 4 19 4>;
};
tcb1: timer@fffdc000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffdc000 0x100>;
interrupts = <26 4 27 4 28 4>;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x100>;
interrupts = <2 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x100>;
interrupts = <3 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x100>;
interrupts = <4 4>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
};
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4>;
status = "disabled";
};
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
interrupts = <6 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
interrupts = <7 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart2: serial@fffb8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
interrupts = <8 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart3: serial@fffd0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd0000 0x200>;
interrupts = <23 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart4: serial@fffd4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd4000 0x200>;
interrupts = <24 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
usart5: serial@fffd8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd8000 0x200>;
interrupts = <25 4>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
};
macb0: ethernet@fffc4000 {
compatible = "cdns,at32ap7000-macb", "cdns,macb";
reg = <0xfffc4000 0x100>;
interrupts = <21 4>;
status = "disabled";
};
usb1: gadget@fffa4000 {
compatible = "atmel,at91rm9200-udc";
reg = <0xfffa4000 0x4000>;
interrupts = <10 4>;
status = "disabled";
adc0: adc@fffe0000 {
atmel,adc-startup-time = <40>;
};
};
nand0: nand@40000000 {
compatible = "atmel,at91rm9200-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
0xffffe800 0x200
>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
gpios = <&pioC 13 0
&pioC 14 0
0
>;
status = "disabled";
};
usb0: ohci@00500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 4>;
status = "disabled";
};
};
i2c@0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 0 /* sda */
&pioA 24 0 /* scl */
>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
arch/arm/boot/dts/at91sam9g20ek.dts 0 → 100644
View file @ b324c67d
/*
* at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2.
*/
/dts-v1/;
/include/ "at91sam9g20ek_common.dtsi"
/ {
model = "Atmel at91sam9g20ek";
compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
leds {
compatible = "gpio-leds";
ds1 {
label = "ds1";
gpios = <&pioA 9 0>;
linux,default-trigger = "heartbeat";
};
ds5 {
label = "ds5";
gpios = <&pioA 6 1>;
};
};
};
arch/arm/boot/dts/at91sam9g20ek_2mmc.dts 0 → 100644
View file @ b324c67d
/*
* at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2.
*/
/dts-v1/;
/include/ "at91sam9g20ek_common.dtsi"
/ {
model = "Atmel at91sam9g20ek 2 mmc";
compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
leds {
compatible = "gpio-leds";
ds1 {
label = "ds1";
gpios = <&pioB 9 0>;
linux,default-trigger = "heartbeat";
};
ds5 {
label = "ds5";
gpios = <&pioB 8 1>;
};
};
};
arch/arm/boot/dts/at91sam9g20ek_common.dtsi 0 → 100644
View file @ b324c67d
/*
* at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2.
*/
/include/ "at91sam9g20.dtsi"
/ {
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@fffb0000 {
status = "okay";
};
usart1: serial@fffb4000 {
status = "okay";
};
macb0: ethernet@fffc4000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 0>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x20000>;
};
barebox@20000 {
label = "barebox";
reg = <0x20000 0x40000>;
};
bareboxenv@60000 {
label = "bareboxenv";
reg = <0x60000 0x20000>;
};
bareboxenv2@80000 {
label = "bareboxenv2";
reg = <0x80000 0x20000>;
};
oftree@80000 {
label = "oftree";
reg = <0xa0000 0x20000>;
};
kernel@a0000 {
label = "kernel";
reg = <0xc0000 0x400000>;
};
rootfs@4a0000 {
label = "rootfs";
reg = <0x4c0000 0x7800000>;
};
data@7ca0000 {
label = "data";
reg = <0x7cc0000 0x8340000>;
};
};
usb0: ohci@00500000 {
num-ports = <2>;
status = "okay";
};
};
i2c@0 {
status = "okay";
24c512@50 {
compatible = "24c512";
reg = <0x50>;
};
wm8731@1b {
compatible = "wm8731";
reg = <0x1b>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
btn3 {
label = "Buttin 3";
gpios = <&pioA 30 1>;
linux,code = <0x103>;
gpio-key,wakeup;
};
btn4 {
label = "Buttin 4";
gpios = <&pioA 31 1>;
linux,code = <0x104>;
gpio-key,wakeup;
};
};
};
arch/arm/boot/dts/db8500.dtsi
View file @ b324c67d
......@@ -55,83 +55,101 @@ rtc@80154000 {
gpio0: gpio@8012e000 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8012e000 0x80>;
interrupts = <0 119 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <0>;
};
gpio1: gpio@8012e080 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8012e080 0x80>;
interrupts = <0 120 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <1>;
};
gpio2: gpio@8000e000 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8000e000 0x80>;
interrupts = <0 121 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <2>;
};
gpio3: gpio@8000e080 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8000e080 0x80>;
interrupts = <0 122 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <3>;
};
gpio4: gpio@8000e100 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8000e100 0x80>;
interrupts = <0 123 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <4>;
};
gpio5: gpio@8000e180 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8000e180 0x80>;
interrupts = <0 124 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <5>;
};
gpio6: gpio@8011e000 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8011e000 0x80>;
interrupts = <0 125 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <6>;
};
gpio7: gpio@8011e080 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0x8011e080 0x80>;
interrupts = <0 126 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <7>;
};
gpio8: gpio@a03fe000 {
compatible = "stericsson,db8500-gpio",
"stmicroelectronics,nomadik-gpio";
"st,nomadik-gpio";
reg = <0xa03fe000 0x80>;
interrupts = <0 127 0x4>;
supports-sleepmode;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <8>;
};
usb@a03e0000 {
......@@ -153,7 +171,13 @@ prcmu@80157000 {
reg = <0x80157000 0x1000>;
interrupts = <46 47>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges;
prcmu-timer-4@80157450 {
compatible = "stericsson,db8500-prcmu-timer-4";
reg = <0x80157450 0xC>;
};
ab8500@5 {
compatible = "stericsson,ab8500";
......@@ -163,7 +187,7 @@ ab8500@5 {
};
i2c@80004000 {
compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
reg = <0x80004000 0x1000>;
interrupts = <0 21 0x4>;
#address-cells = <1>;
......@@ -171,7 +195,7 @@ i2c@80004000 {
};
i2c@80122000 {
compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
reg = <0x80122000 0x1000>;
interrupts = <0 22 0x4>;
#address-cells = <1>;
......@@ -179,7 +203,7 @@ i2c@80122000 {
};
i2c@80128000 {
compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
reg = <0x80128000 0x1000>;
interrupts = <0 55 0x4>;
#address-cells = <1>;
......@@ -187,7 +211,7 @@ i2c@80128000 {
};
i2c@80110000 {
compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
reg = <0x80110000 0x1000>;
interrupts = <0 12 0x4>;
#address-cells = <1>;
......@@ -195,7 +219,7 @@ i2c@80110000 {
};
i2c@8012a000 {
compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
reg = <0x8012a000 0x1000>;
interrupts = <0 51 0x4>;
#address-cells = <1>;
......@@ -270,5 +294,14 @@ sdi@80008000 {
interrupts = <0 100 0x4>;
status = "disabled";
};
external-bus@50000000 {
compatible = "simple-bus";
reg = <0x50000000 0x4000000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50000000 0x4000000>;
status = "disabled";
};
};
};
arch/arm/boot/dts/ethernut5.dts 0 → 100644
View file @ b324c67d
/*
* ethernut5.dts - Device Tree file for Ethernut 5 board
*
* Copyright (C) 2012 egnite GmbH <info@egnite.de>
*
* Licensed under GPLv2.
*/
/dts-v1/;
/include/ "at91sam9260.dtsi"
/ {
model = "Ethernut 5";
compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
chosen {
bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
};
memory {
reg = <0x20000000 0x08000000>;
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@fffb0000 {
status = "okay";
};
usart1: serial@fffb4000 {
status = "okay";
};
macb0: ethernet@fffc4000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 0>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
gpios = <0
&pioC 14 0
0
>;
root@0 {
label = "root";
reg = <0x0 0x08000000>;
};
data@20000 {
label = "data";
reg = <0x08000000 0x38000000>;
};
};
usb0: ohci@00500000 {
num-ports = <2>;
status = "okay";
};
};
i2c@0 {
status = "okay";
pcf8563@50 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
};
arch/arm/boot/dts/kizbox.dts 0 → 100644
View file @ b324c67d
/*
* kizbox.dts - Device Tree file for Overkiz Kizbox board
*
* Copyright (C) 2012 Boris BREZILLON <linux-arm@overkiz.com>
*
* Licensed under GPLv2.
*/
/dts-v1/;
/include/ "at91sam9g20.dtsi"
/ {
model = "Overkiz kizbox";
compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9";
chosen {
bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root";
};
memory {
reg = <0x20000000 0x2000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
usart0: serial@fffb0000 {
status = "okay";
};
usart1: serial@fffb4000 {
status = "okay";
};
macb0: ethernet@fffc4000 {
phy-mode = "mii";
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
status = "okay";
bootloaderkernel@0 {
label = "bootloader-kernel";
reg = <0x0 0xc0000>;
};
ubi@c0000 {
label = "ubi";
reg = <0xc0000 0x7f40000>;
};
};
usb0: ohci@00500000 {
num-ports = <1>;
status = "okay";
};
};
i2c@0 {
status = "okay";
pcf8563@51 {
/* nxp pcf8563 rtc */
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
leds {
compatible = "gpio-leds";
led1g {
label = "led1:green";
gpios = <&pioB 0 1>;
linux,default-trigger = "none";
};
led1r {
label = "led1:red";
gpios = <&pioB 1 1>;
linux,default-trigger = "none";
};
led2g {
label = "led2:green";
gpios = <&pioB 2 1>;
linux,default-trigger = "none";
default-state = "on";
};
led2r {
label = "led2:red";
gpios = <&pioB 3 1>;
linux,default-trigger = "none";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
reset {
label = "reset";
gpios = <&pioB 30 1>;
linux,code = <0x100>;
gpio-key,wakeup;
};
mode {
label = "mode";
gpios = <&pioB 31 1>;
linux,code = <0x101>;
gpio-key,wakeup;
};
};
};
\ No newline at end of file
arch/arm/boot/dts/lpc32xx.dtsi 0 → 100644
View file @ b324c67d
/*
* NXP LPC32xx SoC
*
* Copyright 2012 Roland Stigge <stigge@antcom.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
compatible = "nxp,lpc3220";
interrupt-parent = <&mic>;
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x20000000 0x20000000 0x30000000>;
/*
* Enable either SLC or MLC
*/
slc: flash@20020000 {
compatible = "nxp,lpc3220-slc";
reg = <0x20020000 0x1000>;
status = "disable";
};
mlc: flash@200B0000 {
compatible = "nxp,lpc3220-mlc";
reg = <0x200B0000 0x1000>;
status = "disable";
};
dma@31000000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0x31000000 0x1000>;
interrupts = <0x1c 0>;
};
/*
* Enable either ohci or usbd (gadget)!
*/
ohci@31020000 {
compatible = "nxp,ohci-nxp", "usb-ohci";
reg = <0x31020000 0x300>;
interrupts = <0x3b 0>;
status = "disable";
};
usbd@31020000 {
compatible = "nxp,lpc3220-udc";
reg = <0x31020000 0x300>;
interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
status = "disable";
};
clcd@31040000 {
compatible = "arm,pl110", "arm,primecell";
reg = <0x31040000 0x1000>;
interrupts = <0x0e 0>;
status = "disable";
};
mac: ethernet@31060000 {
compatible = "nxp,lpc-eth";
reg = <0x31060000 0x1000>;
interrupts = <0x1d 0>;
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x20000000 0x20000000 0x30000000>;
ssp0: ssp@20084000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x20084000 0x1000>;
interrupts = <0x14 0>;
};
spi1: spi@20088000 {
compatible = "nxp,lpc3220-spi";
reg = <0x20088000 0x1000>;
};
ssp1: ssp@2008c000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x2008c000 0x1000>;
interrupts = <0x15 0>;
};
spi2: spi@20090000 {
compatible = "nxp,lpc3220-spi";
reg = <0x20090000 0x1000>;
};
i2s0: i2s@20094000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x20094000 0x1000>;
};
sd@20098000 {
compatible = "arm,pl180", "arm,primecell";
reg = <0x20098000 0x1000>;
interrupts = <0x0f 0>, <0x0d 0>;
};
i2s1: i2s@2009C000 {
compatible = "nxp,lpc3220-i2s";
reg = <0x2009C000 0x1000>;
};
uart3: serial@40080000 {
compatible = "nxp,serial";
reg = <0x40080000 0x1000>;
};
uart4: serial@40088000 {
compatible = "nxp,serial";
reg = <0x40088000 0x1000>;
};
uart5: serial@40090000 {
compatible = "nxp,serial";
reg = <0x40090000 0x1000>;
};
uart6: serial@40098000 {
compatible = "nxp,serial";
reg = <0x40098000 0x1000>;
};
i2c1: i2c@400A0000 {
compatible = "nxp,pnx-i2c";
reg = <0x400A0000 0x100>;
interrupts = <0x33 0>;
#address-cells = <1>;
#size-cells = <0>;
pnx,timeout = <0x64>;
};
i2c2: i2c@400A8000 {
compatible = "nxp,pnx-i2c";
reg = <0x400A8000 0x100>;
interrupts = <0x32 0>;
#address-cells = <1>;
#size-cells = <0>;
pnx,timeout = <0x64>;
};
i2cusb: i2c@31020300 {
compatible = "nxp,pnx-i2c";
reg = <0x31020300 0x100>;
interrupts = <0x3f 0>;
#address-cells = <1>;
#size-cells = <0>;
pnx,timeout = <0x64>;
};
};
fab {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x20000000 0x20000000 0x30000000>;
/*
* MIC Interrupt controller includes:
* MIC @40008000
* SIC1 @4000C000
* SIC2 @40010000
*/
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
interrupt-controller;
reg = <0x40008000 0xC000>;
#interrupt-cells = <2>;
};
uart1: serial@40014000 {
compatible = "nxp,serial";
reg = <0x40014000 0x1000>;
};
uart2: serial@40018000 {
compatible = "nxp,serial";
reg = <0x40018000 0x1000>;
};
uart7: serial@4001C000 {
compatible = "nxp,serial";
reg = <0x4001C000 0x1000>;
};
rtc@40024000 {
compatible = "nxp,lpc3220-rtc";
reg = <0x40024000 0x1000>;
interrupts = <0x34 0>;
};
gpio: gpio@40028000 {
compatible = "nxp,lpc3220-gpio";
reg = <0x40028000 0x1000>;
/* create a private address space for enumeration */
#address-cells = <1>;
#size-cells = <0>;
gpio_p0: gpio-bank@0 {
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
};
gpio_p1: gpio-bank@1 {
gpio-controller;
#gpio-cells = <2>;
reg = <1>;
};
gpio_p2: gpio-bank@2 {
gpio-controller;
#gpio-cells = <2>;
reg = <2>;
};
gpio_p3: gpio-bank@3 {
gpio-controller;
#gpio-cells = <2>;
reg = <3>;
};
gpi_p3: gpio-bank@4 {
gpio-controller;
#gpio-cells = <2>;
reg = <4>;
};
gpo_p3: gpio-bank@5 {
gpio-controller;
#gpio-cells = <2>;
reg = <5>;
};
};
watchdog@4003C000 {
compatible = "nxp,pnx4008-wdt";
reg = <0x4003C000 0x1000>;
};
/*
* TSC vs. ADC: Since those two share the same
* hardware, you need to choose from one of the
* following two and do 'status = "okay";' for one of
* them
*/
adc@40048000 {
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupts = <0x27 0>;
status = "disable";
};
tsc@40048000 {
compatible = "nxp,lpc3220-tsc";
reg = <0x40048000 0x1000>;
interrupts = <0x27 0>;
status = "disable";
};
key@40050000 {
compatible = "nxp,lpc3220-key";
reg = <0x40050000 0x1000>;
};
};
};
};
arch/arm/boot/dts/mmp2-brownstone.dts 0 → 100644
View file @ b324c67d
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
/include/ "mmp2.dtsi"
/ {
model = "Marvell MMP2 Aspenite Development Board";
compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
chosen {
bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
};
memory {
reg = <0x00000000 0x04000000>;
};
soc {
apb@d4000000 {
uart3: uart@d4018000 {
status = "okay";
};
twsi1: i2c@d4011000 {
status = "okay";
};
rtc: rtc@d4010000 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/mmp2.dtsi 0 → 100644
View file @ b324c67d
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
i2c0 = &twsi1;
i2c1 = &twsi2;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4200000 0x00200000>;
ranges;
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp2-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
intcmux4@d4282150 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <4>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x150 0x4>, <0x168 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
intcmux5: interrupt-controller@d4282154 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <5>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x154 0x4>, <0x16c 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
mrvl,clr-mfp-irq = <1>;
};
intcmux9: interrupt-controller@d4282180 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <9>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x180 0x4>, <0x17c 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <3>;
};
intcmux17: interrupt-controller@d4282158 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <17>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x158 0x4>, <0x170 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <5>;
};
intcmux35: interrupt-controller@d428215c {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <35>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x15c 0x4>, <0x174 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <15>;
};
intcmux51: interrupt-controller@d4282160 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <51>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x160 0x4>, <0x178 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
intcmux55: interrupt-controller@d4282188 {
compatible = "mrvl,mmp2-mux-intc";
interrupts = <55>;
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x188 0x4>, <0x184 0x4>;
reg-names = "mux status", "mux mask";
mrvl,intc-nr-irqs = <2>;
};
};
apb@d4000000 { /* APB */
compatible = "mrvl,apb-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4000000 0x00200000>;
ranges;
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};
uart1: uart@d4030000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4030000 0x1000>;
interrupts = <27>;
status = "disabled";
};
uart2: uart@d4017000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4017000 0x1000>;
interrupts = <28>;
status = "disabled";
};
uart3: uart@d4018000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4018000 0x1000>;
interrupts = <24>;
status = "disabled";
};
uart4: uart@d4016000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4016000 0x1000>;
interrupts = <46>;
status = "disabled";
};
gpio@d4019000 {
compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
interrupt-controller;
#interrupt-cells = <1>;
ranges;
gcb0: gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gcb1: gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gcb2: gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gcb3: gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
gcb4: gpio@d4019104 {
reg = <0xd4019104 0x4>;
};
gcb5: gpio@d4019108 {
reg = <0xd4019108 0x4>;
};
};
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
status = "disabled";
};
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4025000 0x1000>;
interrupts = <58>;
status = "disabled";
};
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
interrupts = <1 0>;
interrupt-names = "rtc 1Hz", "rtc alarm";
interrupt-parent = <&intcmux5>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/omap3-beagle.dts
View file @ b324c67d
......@@ -18,3 +18,52 @@ memory {
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
vsim: regulator@10 {
compatible = "ti,twl4030-vsim";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
/include/ "twl4030.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in the EEPROM
* as EDID data.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&mmc1 {
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
ti,bus-width = <8>;
};
&mmc2 {
status = "disable";
};
&mmc3 {
status = "disable";
};
arch/arm/boot/dts/omap3.dtsi
View file @ b324c67d
......@@ -69,6 +69,60 @@ intc: interrupt-controller@48200000 {
reg = <0x48200000 0x1000>;
};
gpio1: gpio@48310000 {
compatible = "ti,omap3-gpio";
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio2: gpio@49050000 {
compatible = "ti,omap3-gpio";
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio3: gpio@49052000 {
compatible = "ti,omap3-gpio";
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio4: gpio@49054000 {
compatible = "ti,omap3-gpio";
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio5: gpio@49056000 {
compatible = "ti,omap3-gpio";
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio6: gpio@49058000 {
compatible = "ti,omap3-gpio";
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: serial@4806a000 {
compatible = "ti,omap3-uart";
ti,hwmods = "uart1";
......@@ -113,5 +167,53 @@ i2c3: i2c@48060000 {
#size-cells = <0>;
ti,hwmods = "i2c3";
};
mcspi1: spi@48098000 {
compatible = "ti,omap2-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
};
mcspi2: spi@4809a000 {
compatible = "ti,omap2-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
};
mcspi3: spi@480b8000 {
compatible = "ti,omap2-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
};
mcspi4: spi@480ba000 {
compatible = "ti,omap2-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
};
mmc1: mmc@4809c000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc1";
ti,dual-volt;
};
mmc2: mmc@480b4000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc2";
};
mmc3: mmc@480ad000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc3";
};
};
};
arch/arm/boot/dts/omap4-panda.dts
View file @ b324c67d
......@@ -17,4 +17,75 @@ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
leds {
compatible = "gpio-leds";
heartbeat {
label = "pandaboard::status1";
gpios = <&gpio1 7 0>;
linux,default-trigger = "heartbeat";
};
mmc {
label = "pandaboard::status2";
gpios = <&gpio1 8 0>;
linux,default-trigger = "mmc0";
};
};
};
&i2c1 {
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
interrupt-parent = <&gic>;
};
};
/include/ "twl6030.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in their EEPROM as EDID data.
* The EEPROM is connected as I2C slave device.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&i2c4 {
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc>;
ti,bus-width = <8>;
};
&mmc2 {
status = "disable";
};
&mmc3 {
status = "disable";
};
&mmc4 {
status = "disable";
};
&mmc5 {
ti,non-removable;
ti,bus-width = <4>;
};
arch/arm/boot/dts/omap4-sdp.dts
View file @ b324c67d
......@@ -17,4 +17,144 @@ memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
vdd_eth: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "VDD_ETH";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 16 0>; /* gpio line 48 */
enable-active-high;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
debug0 {
label = "omap4:green:debug0";
gpios = <&gpio2 29 0>; /* 61 */
};
debug1 {
label = "omap4:green:debug1";
gpios = <&gpio1 30 0>; /* 30 */
};
debug2 {
label = "omap4:green:debug2";
gpios = <&gpio1 7 0>; /* 7 */
};
debug3 {
label = "omap4:green:debug3";
gpios = <&gpio1 8 0>; /* 8 */
};
debug4 {
label = "omap4:green:debug4";
gpios = <&gpio2 18 0>; /* 50 */
};
user1 {
label = "omap4:blue:user";
gpios = <&gpio6 9 0>; /* 169 */
};
user2 {
label = "omap4:red:user";
gpios = <&gpio6 10 0>; /* 170 */
};
user3 {
label = "omap4:green:user";
gpios = <&gpio5 11 0>; /* 139 */
};
};
};
&i2c1 {
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
interrupt-parent = <&gic>;
};
};
/include/ "twl6030.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <400000>;
/*
* Temperature Sensor
* http://www.ti.com/lit/ds/symlink/tmp105.pdf
*/
tmp105@48 {
compatible = "ti,tmp105";
reg = <0x48>;
};
/*
* Ambient Light Sensor
* http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
*/
bh1780@29 {
compatible = "rohm,bh1780";
reg = <0x29>;
};
};
&i2c4 {
clock-frequency = <400000>;
/*
* 3-Axis Digital Compass
* http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
*/
hmc5843@1e {
compatible = "honeywell,hmc5843";
reg = <0x1e>;
};
};
&mcspi1 {
eth@0 {
compatible = "ks8851";
spi-max-frequency = <24000000>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <2>; /* gpio line 34 */
vdd-supply = <&vdd_eth>;
};
};
&mmc1 {
vmmc-supply = <&vmmc>;
ti,bus-width = <8>;
};
&mmc2 {
vmmc-supply = <&vaux1>;
ti,bus-width = <8>;
ti,non-removable;
};
&mmc3 {
status = "disable";
};
&mmc4 {
status = "disable";
};
&mmc5 {
ti,bus-width = <4>;
ti,non-removable;
};
arch/arm/boot/dts/omap4.dtsi
View file @ b324c67d
......@@ -104,6 +104,60 @@ gic: interrupt-controller@48241000 {
<0x48240100 0x0100>;
};
gpio1: gpio@4a310000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio2: gpio@48055000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio3: gpio@48057000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio4: gpio@48059000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio5: gpio@4805b000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
gpio6: gpio@4805d000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
ti,hwmods = "uart1";
......@@ -155,5 +209,68 @@ i2c4: i2c@48350000 {
#size-cells = <0>;
ti,hwmods = "i2c4";
};
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
};
mcspi2: spi@4809a000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
};
mcspi3: spi@480b8000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
};
mcspi4: spi@480ba000 {
compatible = "ti,omap4-mcspi";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
};
mmc1: mmc@4809c000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
};
mmc2: mmc@480b4000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc2";
ti,needs-special-reset;
};
mmc3: mmc@480ad000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc3";
ti,needs-special-reset;
};
mmc4: mmc@480d1000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc4";
ti,needs-special-reset;
};
mmc5: mmc@480d5000 {
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc5";
ti,needs-special-reset;
};
};
};
arch/arm/boot/dts/phy3250.dts 0 → 100644
View file @ b324c67d
/*
* PHYTEC phyCORE-LPC3250 board
*
* Copyright 2012 Roland Stigge <stigge@antcom.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "lpc32xx.dtsi"
/ {
model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
compatible = "phytec,phy3250", "nxp,lpc3250";
#address-cells = <1>;
#size-cells = <1>;
memory {
device_type = "memory";
reg = <0 0x4000000>;
};
ahb {
mac: ethernet@31060000 {
phy-mode = "rmii";
use-iram;
};
/* Here, choose exactly one from: ohci, usbd */
ohci@31020000 {
transceiver = <&isp1301>;
status = "okay";
};
/*
usbd@31020000 {
transceiver = <&isp1301>;
status = "okay";
};
*/
clcd@31040000 {
status = "okay";
};
/* 64MB Flash via SLC NAND controller */
slc: flash@20020000 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
mtd0@00000000 {
label = "phy3250-boot";
reg = <0x00000000 0x00064000>;
read-only;
};
mtd1@00064000 {
label = "phy3250-uboot";
reg = <0x00064000 0x00190000>;
read-only;
};
mtd2@001f4000 {
label = "phy3250-ubt-prms";
reg = <0x001f4000 0x00010000>;
};
mtd3@00204000 {
label = "phy3250-kernel";
reg = <0x00204000 0x00400000>;
};
mtd4@00604000 {
label = "phy3250-rootfs";
reg = <0x00604000 0x039fc000>;
};
};
apb {
i2c1: i2c@400A0000 {
clock-frequency = <100000>;
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
uda1380: uda1380@18 {
compatible = "nxp,uda1380";
reg = <0x18>;
power-gpio = <&gpio 0x59 0>;
reset-gpio = <&gpio 0x51 0>;
dac-clk = "wspll";
};
};
i2c2: i2c@400A8000 {
clock-frequency = <100000>;
};
i2cusb: i2c@31020300 {
clock-frequency = <100000>;
isp1301: usb-transceiver@2c {
compatible = "nxp,isp1301";
reg = <0x2c>;
};
};
ssp0: ssp@20084000 {
eeprom: at25@0 {
compatible = "atmel,at25";
};
};
};
fab {
tsc@40048000 {
status = "okay";
};
};
};
leds {
compatible = "gpio-leds";
led0 {
gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
linux,default-trigger = "heartbeat";
default-state = "off";
};
led1 {
gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
linux,default-trigger = "timer";
default-state = "off";
};
};
};
arch/arm/boot/dts/pxa168.dtsi
View file @ b324c67d
......@@ -18,13 +18,6 @@ aliases {
i2c1 = &twsi2;
};
intc: intc-interrupt-controller@d4282000 {
compatible = "mrvl,mmp-intc", "mrvl,intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
......@@ -32,6 +25,23 @@ soc {
interrupt-parent = <&intc>;
ranges;
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4200000 0x00200000>;
ranges;
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
};
apb@d4000000 { /* APB */
compatible = "mrvl,apb-bus", "simple-bus";
#address-cells = <1>;
......@@ -39,40 +49,65 @@ apb@d4000000 { /* APB */
reg = <0xd4000000 0x00200000>;
ranges;
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};
uart1: uart@d4017000 {
compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
compatible = "mrvl,mmp-uart";
reg = <0xd4017000 0x1000>;
interrupts = <27>;
status = "disabled";
};
uart2: uart@d4018000 {
compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
compatible = "mrvl,mmp-uart";
reg = <0xd4018000 0x1000>;
interrupts = <28>;
status = "disabled";
};
uart3: uart@d4026000 {
compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
compatible = "mrvl,mmp-uart";
reg = <0xd4026000 0x1000>;
interrupts = <29>;
status = "disabled";
};
gpio: gpio@d4019000 {
compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
gpio@d4019000 {
compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <1>;
ranges;
gcb0: gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gcb1: gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gcb2: gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gcb3: gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
};
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
......@@ -80,7 +115,7 @@ twsi1: i2c@d4011000 {
};
twsi2: i2c@d4025000 {
compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
compatible = "mrvl,mmp-twsi";
reg = <0xd4025000 0x1000>;
interrupts = <58>;
status = "disabled";
......
arch/arm/boot/dts/pxa910-dkb.dts 0 → 100644
View file @ b324c67d
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
/include/ "pxa910.dtsi"
/ {
model = "Marvell PXA910 DKB Development Board";
compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
chosen {
bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
};
memory {
reg = <0x00000000 0x10000000>;
};
soc {
apb@d4000000 {
uart1: uart@d4017000 {
status = "okay";
};
twsi1: i2c@d4011000 {
status = "okay";
};
rtc: rtc@d4010000 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/pxa910.dtsi 0 → 100644
View file @ b324c67d
/*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Author: Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
i2c0 = &twsi1;
i2c1 = &twsi2;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
axi@d4200000 { /* AXI */
compatible = "mrvl,axi-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4200000 0x00200000>;
ranges;
intc: interrupt-controller@d4282000 {
compatible = "mrvl,mmp-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0xd4282000 0x1000>;
mrvl,intc-nr-irqs = <64>;
};
};
apb@d4000000 { /* APB */
compatible = "mrvl,apb-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4000000 0x00200000>;
ranges;
timer0: timer@d4014000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4014000 0x100>;
interrupts = <13>;
};
timer1: timer@d4016000 {
compatible = "mrvl,mmp-timer";
reg = <0xd4016000 0x100>;
interrupts = <29>;
status = "disabled";
};
uart1: uart@d4017000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4017000 0x1000>;
interrupts = <27>;
status = "disabled";
};
uart2: uart@d4018000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4018000 0x1000>;
interrupts = <28>;
status = "disabled";
};
uart3: uart@d4036000 {
compatible = "mrvl,mmp-uart";
reg = <0xd4036000 0x1000>;
interrupts = <59>;
status = "disabled";
};
gpio@d4019000 {
compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <49>;
interrupt-names = "gpio_mux";
interrupt-controller;
#interrupt-cells = <1>;
ranges;
gcb0: gpio@d4019000 {
reg = <0xd4019000 0x4>;
};
gcb1: gpio@d4019004 {
reg = <0xd4019004 0x4>;
};
gcb2: gpio@d4019008 {
reg = <0xd4019008 0x4>;
};
gcb3: gpio@d4019100 {
reg = <0xd4019100 0x4>;
};
};
twsi1: i2c@d4011000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4011000 0x1000>;
interrupts = <7>;
mrvl,i2c-fast-mode;
status = "disabled";
};
twsi2: i2c@d4037000 {
compatible = "mrvl,mmp-twsi";
reg = <0xd4037000 0x1000>;
interrupts = <54>;
status = "disabled";
};
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
interrupts = <5 6>;
interrupt-names = "rtc 1Hz", "rtc alarm";
status = "disabled";
};
};
};
};
arch/arm/boot/dts/sh7372.dtsi 0 → 100644
View file @ b324c67d
/*
* Device Tree Source for the sh7372 SoC
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "renesas,sh7372";
cpus {
cpu@0 {
compatible = "arm,cortex-a8";
};
};
};
arch/arm/boot/dts/snowball.dts
View file @ b324c67d
......@@ -30,35 +30,35 @@ button@1 {
wakeup = <1>;
linux,code = <2>;
label = "userpb";
gpios = <&gpio1 0>;
gpios = <&gpio1 0 0>;
};
button@2 {
debounce_interval = <50>;
wakeup = <1>;
linux,code = <3>;
label = "userpb";
gpios = <&gpio4 23>;
label = "extkb1";
gpios = <&gpio4 23 0>;
};
button@3 {
debounce_interval = <50>;
wakeup = <1>;
linux,code = <4>;
label = "userpb";
gpios = <&gpio4 23>;
label = "extkb2";
gpios = <&gpio4 24 0>;
};
button@4 {
debounce_interval = <50>;
wakeup = <1>;
linux,code = <5>;
label = "userpb";
gpios = <&gpio5 1>;
label = "extkb3";
gpios = <&gpio5 1 0>;
};
button@5 {
debounce_interval = <50>;
wakeup = <1>;
linux,code = <6>;
label = "userpb";
gpios = <&gpio5 2>;
label = "extkb4";
gpios = <&gpio5 2 0>;
};
};
......@@ -73,17 +73,19 @@ used-led {
soc-u9500 {
external-bus@50000000 {
compatible = "simple-bus";
reg = <0x50000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ethernet@50000000 {
compatible = "smsc,9111";
reg = <0x50000000 0x10000>;
interrupts = <12>;
status = "okay";
ethernet@0 {
compatible = "smsc,lan9115";
reg = <0 0x10000>;
interrupts = <12 0x1>;
interrupt-parent = <&gpio4>;
reg-shift = <1>;
reg-io-width = <2>;
smsc,force-internal-phy;
smsc,irq-active-high;
smsc,irq-push-pull;
};
};
......
arch/arm/boot/dts/spear300-evb.dts 0 → 100644
View file @ b324c67d
/*
* DTS file for SPEAr300 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear300.dtsi"
/ {
model = "ST SPEAr300 Evaluation Board";
compatible = "st,spear300-evb", "st,spear300";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
clcd@60000000 {
status = "okay";
};
dma@fc400000 {
status = "okay";
};
fsmc: flash@94000000 {
status = "okay";
};
gmac: eth@e0800000 {
status = "okay";
};
sdhci@70000000 {
int-gpio = <&gpio1 0 0>;
power-gpio = <&gpio1 2 1>;
status = "okay";
};
smi: flash@fc000000 {
status = "okay";
};
spi0: spi@d0100000 {
status = "okay";
};
ehci@e1800000 {
status = "okay";
};
ohci@e1900000 {
status = "okay";
};
ohci@e2100000 {
status = "okay";
};
apb {
gpio0: gpio@fc980000 {
status = "okay";
};
gpio1: gpio@a9000000 {
status = "okay";
};
i2c0: i2c@d0180000 {
status = "okay";
};
kbd@a0000000 {
linux,keymap = < 0x00000001
0x00010002
0x00020003
0x00030004
0x00040005
0x00050006
0x00060007
0x00070008
0x00080009
0x0100000a
0x0101000c
0x0102000d
0x0103000e
0x0104000f
0x01050010
0x01060011
0x01070012
0x01080013
0x02000014
0x02010015
0x02020016
0x02030017
0x02040018
0x02050019
0x0206001a
0x0207001b
0x0208001c
0x0300001d
0x0301001e
0x0302001f
0x03030020
0x03040021
0x03050022
0x03060023
0x03070024
0x03080025
0x04000026
0x04010027
0x04020028
0x04030029
0x0404002a
0x0405002b
0x0406002c
0x0407002d
0x0408002e
0x0500002f
0x05010030
0x05020031
0x05030032
0x05040033
0x05050034
0x05060035
0x05070036
0x05080037
0x06000038
0x06010039
0x0602003a
0x0603003b
0x0604003c
0x0605003d
0x0606003e
0x0607003f
0x06080040
0x07000041
0x07010042
0x07020043
0x07030044
0x07040045
0x07050046
0x07060047
0x07070048
0x07080049
0x0800004a
0x0801004b
0x0802004c
0x0803004d
0x0804004e
0x0805004f
0x08060050
0x08070051
0x08080052 >;
autorepeat;
st,mode = <0>;
status = "okay";
};
rtc@fc900000 {
status = "okay";
};
serial@d0000000 {
status = "okay";
};
wdt@fc880000 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/spear300.dtsi 0 → 100644
View file @ b324c67d
/*
* DTS file for SPEAr300 SoC
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear3xx.dtsi"
/ {
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x60000000 0x60000000 0x50000000
0xd0000000 0xd0000000 0x30000000>;
clcd@60000000 {
compatible = "arm,clcd-pl110", "arm,primecell";
reg = <0x60000000 0x1000>;
interrupts = <30>;
status = "disabled";
};
fsmc: flash@94000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x94000000 0x1000 /* FSMC Register */
0x80000000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
sdhci@70000000 {
compatible = "st,sdhci-spear";
reg = <0x70000000 0x100>;
interrupts = <1>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xa0000000 0xa0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
gpio1: gpio@a9000000 {
#gpio-cells = <2>;
compatible = "arm,pl061", "arm,primecell";
gpio-controller;
reg = <0xa9000000 0x1000>;
status = "disabled";
};
kbd@a0000000 {
compatible = "st,spear300-kbd";
reg = <0xa0000000 0x1000>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/spear310-evb.dts 0 → 100644
View file @ b324c67d
/*
* DTS file for SPEAr310 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear310.dtsi"
/ {
model = "ST SPEAr310 Evaluation Board";
compatible = "st,spear310-evb", "st,spear310";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
dma@fc400000 {
status = "okay";
};
fsmc: flash@44000000 {
status = "okay";
};
gmac: eth@e0800000 {
status = "okay";
};
smi: flash@fc000000 {
status = "okay";
clock-rate=<50000000>;
flash@f8000000 {
label = "m25p64";
reg = <0xf8000000 0x800000>;
#address-cells = <1>;
#size-cells = <1>;
st,smi-fast-mode;
};
};
spi0: spi@d0100000 {
status = "okay";
};
ehci@e1800000 {
status = "okay";
};
ohci@e1900000 {
status = "okay";
};
ohci@e2100000 {
status = "okay";
};
apb {
gpio0: gpio@fc980000 {
status = "okay";
};
i2c0: i2c@d0180000 {
status = "okay";
};
rtc@fc900000 {
status = "okay";
};
serial@d0000000 {
status = "okay";
};
serial@b2000000 {
status = "okay";
};
serial@b2080000 {
status = "okay";
};
serial@b2100000 {
status = "okay";
};
serial@b2180000 {
status = "okay";
};
serial@b2200000 {
status = "okay";
};
wdt@fc880000 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/spear310.dtsi 0 → 100644
View file @ b324c67d
/*
* DTS file for SPEAr310 SoC
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear3xx.dtsi"
/ {
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x40000000 0x40000000 0x10000000
0xb0000000 0xb0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
fsmc: flash@44000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x44000000 0x1000 /* FSMC Register */
0x40000000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
st,ale-off = <0x10000>;
st,cle-off = <0x20000>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xb0000000 0xb0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
serial@b2000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2000000 0x1000>;
status = "disabled";
};
serial@b2080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2080000 0x1000>;
status = "disabled";
};
serial@b2100000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2100000 0x1000>;
status = "disabled";
};
serial@b2180000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2180000 0x1000>;
status = "disabled";
};
serial@b2200000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb2200000 0x1000>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/spear320-evb.dts 0 → 100644
View file @ b324c67d
/*
* DTS file for SPEAr320 Evaluation Baord
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "spear320.dtsi"
/ {
model = "ST SPEAr300 Evaluation Board";
compatible = "st,spear300-evb", "st,spear300";
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0 0x40000000>;
};
ahb {
clcd@90000000 {
status = "okay";
};
dma@fc400000 {
status = "okay";
};
fsmc: flash@4c000000 {
status = "okay";
};
gmac: eth@e0800000 {
status = "okay";
};
sdhci@70000000 {
power-gpio = <&gpio0 2 1>;
power_always_enb;
status = "okay";
};
smi: flash@fc000000 {
status = "okay";
};
spi0: spi@d0100000 {
status = "okay";
};
spi1: spi@a5000000 {
status = "okay";
};
spi2: spi@a6000000 {
status = "okay";
};
ehci@e1800000 {
status = "okay";
};
ohci@e1900000 {
status = "okay";
};
ohci@e2100000 {
status = "okay";
};
apb {
gpio0: gpio@fc980000 {
status = "okay";
};
i2c0: i2c@d0180000 {
status = "okay";
};
i2c1: i2c@a7000000 {
status = "okay";
};
rtc@fc900000 {
status = "okay";
};
serial@d0000000 {
status = "okay";
};
serial@a3000000 {
status = "okay";
};
serial@a4000000 {
status = "okay";
};
wdt@fc880000 {
status = "okay";
};
};
};
};
arch/arm/boot/dts/spear320.dtsi 0 → 100644
View file @ b324c67d
/*
* DTS file for SPEAr320 SoC
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "spear3xx.dtsi"
/ {
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0x40000000 0x40000000 0x70000000
0xd0000000 0xd0000000 0x30000000>;
clcd@90000000 {
compatible = "arm,clcd-pl110", "arm,primecell";
reg = <0x90000000 0x1000>;
interrupts = <33>;
status = "disabled";
};
fsmc: flash@4c000000 {
compatible = "st,spear600-fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x4c000000 0x1000 /* FSMC Register */
0x50000000 0x0010>; /* NAND Base */
reg-names = "fsmc_regs", "nand_data";
st,ale-off = <0x20000>;
st,cle-off = <0x10000>;
status = "disabled";
};
sdhci@70000000 {
compatible = "st,sdhci-spear";
reg = <0x70000000 0x100>;
interrupts = <29>;
status = "disabled";
};
spi1: spi@a5000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa5000000 0x1000>;
status = "disabled";
};
spi2: spi@a6000000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xa6000000 0x1000>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xa0000000 0xa0000000 0x10000000
0xd0000000 0xd0000000 0x30000000>;
i2c1: i2c@a7000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xa7000000 0x1000>;
status = "disabled";
};
serial@a3000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa3000000 0x1000>;
status = "disabled";
};
serial@a4000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xa4000000 0x1000>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/spear3xx.dtsi 0 → 100644
View file @ b324c67d
/*
* DTS file for all SPEAr3xx SoCs
*
* Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "skeleton.dtsi"
/ {
interrupt-parent = <&vic>;
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
};
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
ahb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xd0000000 0xd0000000 0x30000000>;
vic: interrupt-controller@f1100000 {
compatible = "arm,pl190-vic";
interrupt-controller;
reg = <0xf1100000 0x1000>;
#interrupt-cells = <1>;
};
dma@fc400000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0xfc400000 0x1000>;
interrupt-parent = <&vic>;
interrupts = <8>;
status = "disabled";
};
gmac: eth@e0800000 {
compatible = "st,spear600-gmac";
reg = <0xe0800000 0x8000>;
interrupts = <23 22>;
interrupt-names = "macirq", "eth_wake_irq";
status = "disabled";
};
smi: flash@fc000000 {
compatible = "st,spear600-smi";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xfc000000 0x1000>;
interrupts = <9>;
status = "disabled";
};
spi0: spi@d0100000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0xd0100000 0x1000>;
interrupts = <20>;
status = "disabled";
};
ehci@e1800000 {
compatible = "st,spear600-ehci", "usb-ehci";
reg = <0xe1800000 0x1000>;
interrupts = <26>;
status = "disabled";
};
ohci@e1900000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe1900000 0x1000>;
interrupts = <25>;
status = "disabled";
};
ohci@e2100000 {
compatible = "st,spear600-ohci", "usb-ohci";
reg = <0xe2100000 0x1000>;
interrupts = <27>;
status = "disabled";
};
apb {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0xd0000000 0xd0000000 0x30000000>;
gpio0: gpio@fc980000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0xfc980000 0x1000>;
interrupts = <11>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};
i2c0: i2c@d0180000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,designware-i2c";
reg = <0xd0180000 0x1000>;
interrupts = <21>;
status = "disabled";
};
rtc@fc900000 {
compatible = "st,spear-rtc";
reg = <0xfc900000 0x1000>;
interrupts = <10>;
status = "disabled";
};
serial@d0000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xd0000000 0x1000>;
interrupts = <19>;
status = "disabled";
};
wdt@fc880000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0xfc880000 0x1000>;
interrupts = <12>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/spear600-evb.dts
View file @ b324c67d
......@@ -24,6 +24,10 @@ memory {
};
ahb {
dma@fc400000 {
status = "okay";
};
gmac: ethernet@e0800000 {
phy-mode = "gmii";
status = "okay";
......
arch/arm/boot/dts/spear600.dtsi
View file @ b324c67d
......@@ -45,6 +45,14 @@ vic1: interrupt-controller@f1000000 {
#interrupt-cells = <1>;
};
dma@fc400000 {
compatible = "arm,pl080", "arm,primecell";
reg = <0xfc400000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <10>;
status = "disabled";
};
gmac: ethernet@e0800000 {
compatible = "st,spear600-gmac";
reg = <0xe0800000 0x8000>;
......
arch/arm/boot/dts/tny_a9260.dts 0 → 100644
View file @ b324c67d
/*
* tny_a9260.dts - Device Tree file for Caloa TNY A9260 board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2.
*/
/dts-v1/;
/include/ "at91sam9260.dtsi"
/include/ "tny_a9260_common.dtsi"
/ {
model = "Calao TNY A9260";
compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9";
};
arch/arm/boot/dts/tny_a9260_common.dtsi 0 → 100644
View file @ b324c67d
/*
* tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2.
*/
/ {
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x20000>;
};
barebox@20000 {
label = "barebox";
reg = <0x20000 0x40000>;
};
bareboxenv@60000 {
label = "bareboxenv";
reg = <0x60000 0x20000>;
};
bareboxenv2@80000 {
label = "bareboxenv2";
reg = <0x80000 0x20000>;
};
oftree@80000 {
label = "oftree";
reg = <0xa0000 0x20000>;
};
kernel@a0000 {
label = "kernel";
reg = <0xc0000 0x400000>;
};
rootfs@4a0000 {
label = "rootfs";
reg = <0x4c0000 0x7800000>;
};
data@7ca0000 {
label = "data";
reg = <0x7cc0000 0x8340000>;
};
};
};
};
arch/arm/boot/dts/tny_a9263.dts 0 → 100644
View file @ b324c67d
/*
* usb_a9263.dts - Device Tree file for Caloa USB A9293 board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 only
*/
/dts-v1/;
/include/ "at91sam9263.dtsi"
/ {
model = "Calao TNY A9263";
compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
};
ahb {
apb {
dbgu: serial@ffffee00 {
status = "okay";
};
usb1: gadget@fff78000 {
atmel,vbus-gpio = <&pioB 11 0>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x20000>;
};
barebox@20000 {
label = "barebox";
reg = <0x20000 0x40000>;
};
bareboxenv@60000 {
label = "bareboxenv";
reg = <0x60000 0x20000>;
};
bareboxenv2@80000 {
label = "bareboxenv2";
reg = <0x80000 0x20000>;
};
oftree@80000 {
label = "oftree";
reg = <0xa0000 0x20000>;
};
kernel@a0000 {
label = "kernel";
reg = <0xc0000 0x400000>;
};
rootfs@4a0000 {
label = "rootfs";
reg = <0x4c0000 0x7800000>;
};
data@7ca0000 {
label = "data";
reg = <0x7cc0000 0x8340000>;
};
};
};
i2c@0 {
status = "okay";
};
};
arch/arm/boot/dts/tny_a9g20.dts 0 → 100644
View file @ b324c67d
/*
* tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2.
*/
/dts-v1/;
/include/ "at91sam9g20.dtsi"
/include/ "tny_a9260_common.dtsi"
/ {
model = "Calao TNY A9G20";
compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
};
arch/arm/boot/dts/twl4030.dtsi 0 → 100644
View file @ b324c67d
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Integrated Power Management Chip
*/
&twl {
compatible = "ti,twl4030";
interrupt-controller;
#interrupt-cells = <1>;
rtc {
compatible = "ti,twl4030-rtc";
interrupts = <11>;
};
vdac: regulator@0 {
compatible = "ti,twl4030-vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vpll2: regulator@1 {
compatible = "ti,twl4030-vpll2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vmmc1: regulator@2 {
compatible = "ti,twl4030-vmmc1";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <3150000>;
};
twl_gpio: gpio {
compatible = "ti,twl4030-gpio";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
};
};
arch/arm/boot/dts/twl6030.dtsi 0 → 100644
View file @ b324c67d
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Integrated Power Management Chip
* http://www.ti.com/lit/ds/symlink/twl6030.pdf
*/
&twl {
compatible = "ti,twl6030";
interrupt-controller;
#interrupt-cells = <1>;
rtc {
compatible = "ti,twl4030-rtc";
interrupts = <11>;
};
vaux1: regulator@0 {
compatible = "ti,twl6030-vaux1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
vaux2: regulator@1 {
compatible = "ti,twl6030-vaux2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2800000>;
};
vaux3: regulator@2 {
compatible = "ti,twl6030-vaux3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
vmmc: regulator@3 {
compatible = "ti,twl6030-vmmc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
};
vpp: regulator@4 {
compatible = "ti,twl6030-vpp";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2500000>;
};
vusim: regulator@5 {
compatible = "ti,twl6030-vusim";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2900000>;
};
vdac: regulator@6 {
compatible = "ti,twl6030-vdac";
};
vana: regulator@7 {
compatible = "ti,twl6030-vana";
};
vcxio: regulator@8 {
compatible = "ti,twl6030-vcxio";
};
vusb: regulator@9 {
compatible = "ti,twl6030-vusb";
};
v1v8: regulator@10 {
compatible = "ti,twl6030-v1v8";
};
v2v1: regulator@11 {
compatible = "ti,twl6030-v2v1";
};
clk32kg: regulator@12 {
compatible = "ti,twl6030-clk32kg";
};
};
arch/arm/boot/dts/usb_a9260.dts 0 → 100644
View file @ b324c67d
/*
* usb_a9260.dts - Device Tree file for Caloa USB A9260 board
*
* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
/include/ "at91sam9260.dtsi"
/include/ "usb_a9260_common.dtsi"
/ {
model = "Calao USB A9260";
compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
memory {
reg = <0x20000000 0x4000000>;
};
};
arch/arm/boot/dts/usb_a9260_common.dtsi 0 → 100644
View file @ b324c67d
/*
* usb_a926x.dts - Device Tree file for Caloa USB A926x board
*
* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 or later.
*/
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
macb0: ethernet@fffc4000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 0>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x20000>;
};
barebox@20000 {
label = "barebox";
reg = <0x20000 0x40000>;
};
bareboxenv@60000 {
label = "bareboxenv";
reg = <0x60000 0x20000>;
};
bareboxenv2@80000 {
label = "bareboxenv2";
reg = <0x80000 0x20000>;
};
oftree@80000 {
label = "oftree";
reg = <0xa0000 0x20000>;
};
kernel@a0000 {
label = "kernel";
reg = <0xc0000 0x400000>;
};
rootfs@4a0000 {
label = "rootfs";
reg = <0x4c0000 0x7800000>;
};
data@7ca0000 {
label = "data";
reg = <0x7cc0000 0x8340000>;
};
};
usb0: ohci@00500000 {
num-ports = <2>;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
user_led {
label = "user_led";
gpios = <&pioB 21 1>;
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user_pb {
label = "user_pb";
gpios = <&pioB 10 1>;
linux,code = <28>;
gpio-key,wakeup;
};
};
i2c@0 {
status = "okay";
};
};
arch/arm/boot/dts/usb_a9263.dts 0 → 100644
View file @ b324c67d
/*
* usb_a9263.dts - Device Tree file for Caloa USB A9293 board
*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Licensed under GPLv2 only
*/
/dts-v1/;
/include/ "at91sam9263.dtsi"
/ {
model = "Calao USB A9263";
compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9";
chosen {
bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
};
ahb {
apb {
dbgu: serial@ffffee00 {
status = "okay";
};
macb0: ethernet@fffbc000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fff78000 {
atmel,vbus-gpio = <&pioB 11 0>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x20000>;
};
barebox@20000 {
label = "barebox";
reg = <0x20000 0x40000>;
};
bareboxenv@60000 {
label = "bareboxenv";
reg = <0x60000 0x20000>;
};
bareboxenv2@80000 {
label = "bareboxenv2";
reg = <0x80000 0x20000>;
};
oftree@80000 {
label = "oftree";
reg = <0xa0000 0x20000>;
};
kernel@a0000 {
label = "kernel";
reg = <0xc0000 0x400000>;
};
rootfs@4a0000 {
label = "rootfs";
reg = <0x4c0000 0x7800000>;
};
data@7ca0000 {
label = "data";
reg = <0x7cc0000 0x8340000>;
};
};
usb0: ohci@00a00000 {
num-ports = <2>;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
user_led {
label = "user_led";
gpios = <&pioB 21 0>;
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user_pb {
label = "user_pb";
gpios = <&pioB 10 1>;
linux,code = <28>;
gpio-key,wakeup;
};
};
i2c@0 {
status = "okay";
};
};
arch/arm/boot/dts/usb_a9g20.dts
View file @ b324c67d
......@@ -7,6 +7,7 @@
*/
/dts-v1/;
/include/ "at91sam9g20.dtsi"
/include/ "usb_a9260_common.dtsi"
/ {
model = "Calao USB A9G20";
......@@ -20,108 +21,7 @@ memory {
reg = <0x20000000 0x4000000>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
};
ahb {
apb {
dbgu: serial@fffff200 {
status = "okay";
};
macb0: ethernet@fffc4000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 0>;
status = "okay";
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x20000>;
};
barebox@20000 {
label = "barebox";
reg = <0x20000 0x40000>;
};
bareboxenv@60000 {
label = "bareboxenv";
reg = <0x60000 0x20000>;
};
bareboxenv2@80000 {
label = "bareboxenv2";
reg = <0x80000 0x20000>;
};
kernel@a0000 {
label = "kernel";
reg = <0xa0000 0x400000>;
};
rootfs@4a0000 {
label = "rootfs";
reg = <0x4a0000 0x7800000>;
};
data@7ca0000 {
label = "data";
reg = <0x7ca0000 0x8360000>;
};
};
usb0: ohci@00500000 {
num-ports = <2>;
status = "okay";
};
};
leds {
compatible = "gpio-leds";
user_led {
label = "user_led";
gpios = <&pioB 21 1>;
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
user_pb {
label = "user_pb";
gpios = <&pioB 10 1>;
linux,code = <28>;
gpio-key,wakeup;
};
};
i2c@0 {
status = "okay";
rv3029c2@56 {
compatible = "rv3029c2";
reg = <0x56>;
......
arch/arm/configs/lpc32xx_defconfig
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arch/arm/configs/spear6xx_defconfig
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arch/arm/mach-at91/Makefile.boot
View file @ b324c67d
......@@ -14,7 +14,19 @@ initrd_phys-y := 0x20410000
endif
# Keep dtb files sorted alphabetically for each SoC
# sam9260
dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
# sam9263
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9263.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb
# sam9g20
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += kizbox.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
# sam9g45
dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
......
arch/arm/mach-at91/at91sam9260_devices.c
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arch/arm/mach-at91/at91sam9263.c
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arch/arm/mach-at91/at91sam9263_devices.c
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arch/arm/mach-at91/at91sam9g45_devices.c
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arch/arm/mach-at91/board-usb-a926x.c
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......@@ -171,6 +171,10 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
.name = "bareboxenv2",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_128K,
}, {
.name = "oftree",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_128K,
}, {
.name = "kernel",
.offset = MTDPART_OFS_NXTBLK,
......
arch/arm/mach-lpc32xx/Kconfig
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arch/arm/mach-mmp/include/mach/irqs.h
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arch/arm/mach-pnx4008/i2c.c
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arch/arm/mach-shmobile/include/mach/intc.h
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arch/arm/mach-shmobile/include/mach/irqs.h
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arch/arm/mach-shmobile/intc-sh7372.c
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